| T1246 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.1984441987 |
|
|
Jun 05 07:26:12 PM PDT 24 |
Jun 05 07:31:19 PM PDT 24 |
3546098031 ps |
| T110 |
/workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.3420472149 |
|
|
Jun 05 07:37:41 PM PDT 24 |
Jun 05 08:12:39 PM PDT 24 |
17252307078 ps |
| T1247 |
/workspace/coverage/default/2.rom_e2e_shutdown_output.2398054428 |
|
|
Jun 05 07:41:49 PM PDT 24 |
Jun 05 08:31:31 PM PDT 24 |
25428955260 ps |
| T1248 |
/workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.3534014774 |
|
|
Jun 05 07:19:36 PM PDT 24 |
Jun 05 07:43:19 PM PDT 24 |
8481648412 ps |
| T311 |
/workspace/coverage/default/33.chip_sw_all_escalation_resets.550508358 |
|
|
Jun 05 07:43:56 PM PDT 24 |
Jun 05 07:55:37 PM PDT 24 |
6573522800 ps |
| T1249 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod_end.569867796 |
|
|
Jun 05 07:44:06 PM PDT 24 |
Jun 05 08:41:48 PM PDT 24 |
14672719592 ps |
| T101 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.868775153 |
|
|
Jun 05 07:29:53 PM PDT 24 |
Jun 05 07:36:54 PM PDT 24 |
7424932084 ps |
| T1250 |
/workspace/coverage/default/38.chip_sw_all_escalation_resets.36992695 |
|
|
Jun 05 07:45:18 PM PDT 24 |
Jun 05 07:55:59 PM PDT 24 |
6036378022 ps |
| T1251 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.122872979 |
|
|
Jun 05 07:28:39 PM PDT 24 |
Jun 05 07:41:18 PM PDT 24 |
4905663513 ps |
| T757 |
/workspace/coverage/default/62.chip_sw_all_escalation_resets.2144426257 |
|
|
Jun 05 07:48:51 PM PDT 24 |
Jun 05 07:58:28 PM PDT 24 |
5055931288 ps |
| T1252 |
/workspace/coverage/default/3.chip_sw_data_integrity_escalation.289775109 |
|
|
Jun 05 07:41:04 PM PDT 24 |
Jun 05 07:53:54 PM PDT 24 |
5938719780 ps |
| T133 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3058335778 |
|
|
Jun 05 07:26:22 PM PDT 24 |
Jun 05 07:33:14 PM PDT 24 |
5916915648 ps |
| T798 |
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.19755494 |
|
|
Jun 05 07:42:16 PM PDT 24 |
Jun 05 07:49:10 PM PDT 24 |
3088216350 ps |
| T1253 |
/workspace/coverage/default/0.chip_sw_example_rom.1138939298 |
|
|
Jun 05 07:12:06 PM PDT 24 |
Jun 05 07:14:03 PM PDT 24 |
2685134136 ps |
| T273 |
/workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.2341238909 |
|
|
Jun 05 07:23:19 PM PDT 24 |
Jun 05 07:36:17 PM PDT 24 |
5679269030 ps |
| T13 |
/workspace/coverage/default/0.chip_sw_sleep_pin_wake.1616126476 |
|
|
Jun 05 07:10:47 PM PDT 24 |
Jun 05 07:16:51 PM PDT 24 |
5616661944 ps |
| T1254 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.1032331417 |
|
|
Jun 05 07:23:11 PM PDT 24 |
Jun 05 09:14:18 PM PDT 24 |
22026143417 ps |
| T1255 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.363488098 |
|
|
Jun 05 07:20:52 PM PDT 24 |
Jun 05 08:18:46 PM PDT 24 |
14766101058 ps |
| T1256 |
/workspace/coverage/default/2.chip_sw_edn_sw_mode.3619170210 |
|
|
Jun 05 07:34:24 PM PDT 24 |
Jun 05 08:05:43 PM PDT 24 |
10185267768 ps |
| T1257 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.1672611865 |
|
|
Jun 05 07:22:10 PM PDT 24 |
Jun 05 08:30:32 PM PDT 24 |
14612168472 ps |
| T1258 |
/workspace/coverage/default/54.chip_sw_all_escalation_resets.2569233104 |
|
|
Jun 05 07:47:00 PM PDT 24 |
Jun 05 07:58:03 PM PDT 24 |
5059044088 ps |
| T1259 |
/workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.58693921 |
|
|
Jun 05 07:15:50 PM PDT 24 |
Jun 05 07:24:05 PM PDT 24 |
4758477464 ps |
| T1260 |
/workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.1659997671 |
|
|
Jun 05 07:34:22 PM PDT 24 |
Jun 05 07:40:54 PM PDT 24 |
3888442176 ps |
| T1261 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.741132366 |
|
|
Jun 05 07:14:30 PM PDT 24 |
Jun 05 07:49:47 PM PDT 24 |
12546631280 ps |
| T1262 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2206935008 |
|
|
Jun 05 07:14:32 PM PDT 24 |
Jun 05 07:32:27 PM PDT 24 |
11393379025 ps |
| T816 |
/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.2373134908 |
|
|
Jun 05 07:42:40 PM PDT 24 |
Jun 05 07:47:47 PM PDT 24 |
3004718586 ps |
| T1263 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.2559046181 |
|
|
Jun 05 07:12:12 PM PDT 24 |
Jun 05 07:40:31 PM PDT 24 |
10446528002 ps |
| T88 |
/workspace/coverage/default/51.chip_sw_all_escalation_resets.2308702348 |
|
|
Jun 05 07:47:02 PM PDT 24 |
Jun 05 07:59:28 PM PDT 24 |
6257933320 ps |
| T708 |
/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.88817197 |
|
|
Jun 05 07:17:12 PM PDT 24 |
Jun 05 07:26:31 PM PDT 24 |
5622667509 ps |
| T1264 |
/workspace/coverage/default/39.chip_sw_all_escalation_resets.2831299885 |
|
|
Jun 05 07:46:20 PM PDT 24 |
Jun 05 07:56:32 PM PDT 24 |
4781230712 ps |
| T1265 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.3685538006 |
|
|
Jun 05 07:20:49 PM PDT 24 |
Jun 05 07:32:01 PM PDT 24 |
4162304344 ps |
| T1266 |
/workspace/coverage/default/1.chip_sw_kmac_entropy.857964671 |
|
|
Jun 05 07:20:49 PM PDT 24 |
Jun 05 07:25:57 PM PDT 24 |
2778720888 ps |
| T393 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1257323963 |
|
|
Jun 05 07:14:43 PM PDT 24 |
Jun 05 07:43:47 PM PDT 24 |
22240307368 ps |
| T1267 |
/workspace/coverage/default/0.chip_sw_hmac_enc_idle.1878545023 |
|
|
Jun 05 07:16:39 PM PDT 24 |
Jun 05 07:21:08 PM PDT 24 |
3120361804 ps |
| T1268 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.4072660041 |
|
|
Jun 05 07:22:22 PM PDT 24 |
Jun 05 07:38:14 PM PDT 24 |
5617514460 ps |
| T40 |
/workspace/coverage/default/0.chip_sw_gpio.1485800722 |
|
|
Jun 05 07:11:57 PM PDT 24 |
Jun 05 07:19:02 PM PDT 24 |
3366925040 ps |
| T1269 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.2969563165 |
|
|
Jun 05 07:31:49 PM PDT 24 |
Jun 05 07:44:51 PM PDT 24 |
4401392596 ps |
| T206 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.2824091298 |
|
|
Jun 05 07:34:53 PM PDT 24 |
Jun 05 08:04:26 PM PDT 24 |
25226637544 ps |
| T1270 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.3328979795 |
|
|
Jun 05 07:22:04 PM PDT 24 |
Jun 05 07:27:12 PM PDT 24 |
2545317153 ps |
| T1271 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2387903962 |
|
|
Jun 05 07:15:14 PM PDT 24 |
Jun 05 08:21:12 PM PDT 24 |
24696613611 ps |
| T1272 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.2262022476 |
|
|
Jun 05 07:32:17 PM PDT 24 |
Jun 05 07:36:45 PM PDT 24 |
2916303016 ps |
| T1273 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.2913915195 |
|
|
Jun 05 07:20:55 PM PDT 24 |
Jun 05 08:02:03 PM PDT 24 |
28434471190 ps |
| T359 |
/workspace/coverage/default/1.chip_sw_aon_timer_irq.1596713378 |
|
|
Jun 05 07:23:38 PM PDT 24 |
Jun 05 07:31:36 PM PDT 24 |
3780031240 ps |
| T1274 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.316126159 |
|
|
Jun 05 07:12:23 PM PDT 24 |
Jun 05 08:22:00 PM PDT 24 |
17295426930 ps |
| T754 |
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2954482207 |
|
|
Jun 05 07:47:08 PM PDT 24 |
Jun 05 07:54:33 PM PDT 24 |
3668247264 ps |
| T1275 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.2592830070 |
|
|
Jun 05 07:25:41 PM PDT 24 |
Jun 05 08:54:32 PM PDT 24 |
26684870240 ps |
| T1276 |
/workspace/coverage/default/2.chip_sw_aon_timer_irq.3740848164 |
|
|
Jun 05 07:34:20 PM PDT 24 |
Jun 05 07:39:40 PM PDT 24 |
3201057928 ps |
| T158 |
/workspace/coverage/default/0.chip_plic_all_irqs_10.983138447 |
|
|
Jun 05 07:15:10 PM PDT 24 |
Jun 05 07:26:15 PM PDT 24 |
3783498500 ps |
| T1277 |
/workspace/coverage/default/0.chip_sw_edn_kat.261462141 |
|
|
Jun 05 07:13:25 PM PDT 24 |
Jun 05 07:23:26 PM PDT 24 |
2928933304 ps |
| T818 |
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.1836654529 |
|
|
Jun 05 07:40:40 PM PDT 24 |
Jun 05 07:46:20 PM PDT 24 |
3390047976 ps |
| T89 |
/workspace/coverage/default/93.chip_sw_all_escalation_resets.1723100018 |
|
|
Jun 05 07:50:19 PM PDT 24 |
Jun 05 08:01:08 PM PDT 24 |
5662303320 ps |
| T1278 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.4002774479 |
|
|
Jun 05 07:13:44 PM PDT 24 |
Jun 05 07:44:41 PM PDT 24 |
7082476520 ps |
| T380 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.2441468832 |
|
|
Jun 05 07:37:07 PM PDT 24 |
Jun 05 07:42:07 PM PDT 24 |
2882322224 ps |
| T1279 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.1753141387 |
|
|
Jun 05 07:29:07 PM PDT 24 |
Jun 05 07:52:31 PM PDT 24 |
5168783448 ps |
| T699 |
/workspace/coverage/default/1.chip_sw_edn_boot_mode.923219122 |
|
|
Jun 05 07:25:01 PM PDT 24 |
Jun 05 07:35:21 PM PDT 24 |
3111835980 ps |
| T162 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.3630250224 |
|
|
Jun 05 07:30:30 PM PDT 24 |
Jun 05 07:32:18 PM PDT 24 |
2794117939 ps |
| T1280 |
/workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.3926515136 |
|
|
Jun 05 07:24:42 PM PDT 24 |
Jun 05 07:33:08 PM PDT 24 |
3982567384 ps |
| T263 |
/workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1247687901 |
|
|
Jun 05 07:37:37 PM PDT 24 |
Jun 05 07:45:54 PM PDT 24 |
4065707920 ps |
| T1281 |
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.2703945772 |
|
|
Jun 05 07:44:32 PM PDT 24 |
Jun 05 08:47:41 PM PDT 24 |
14118766416 ps |
| T853 |
/workspace/coverage/default/5.chip_sw_all_escalation_resets.3055556358 |
|
|
Jun 05 07:41:57 PM PDT 24 |
Jun 05 07:55:36 PM PDT 24 |
6503600570 ps |
| T259 |
/workspace/coverage/default/0.chip_sw_plic_sw_irq.4205065976 |
|
|
Jun 05 07:16:54 PM PDT 24 |
Jun 05 07:20:48 PM PDT 24 |
2601268708 ps |
| T821 |
/workspace/coverage/default/78.chip_sw_all_escalation_resets.2543501368 |
|
|
Jun 05 07:49:25 PM PDT 24 |
Jun 05 07:58:44 PM PDT 24 |
4710679472 ps |
| T1282 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.25181131 |
|
|
Jun 05 07:31:39 PM PDT 24 |
Jun 05 07:33:36 PM PDT 24 |
1990008351 ps |
| T1283 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.2488252135 |
|
|
Jun 05 07:22:17 PM PDT 24 |
Jun 05 08:16:21 PM PDT 24 |
13862458520 ps |
| T1284 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.3313063773 |
|
|
Jun 05 07:30:58 PM PDT 24 |
Jun 05 07:36:27 PM PDT 24 |
2998381758 ps |
| T149 |
/workspace/coverage/default/0.chip_jtag_csr_rw.2052670239 |
|
|
Jun 05 07:06:10 PM PDT 24 |
Jun 05 07:11:29 PM PDT 24 |
4669159912 ps |
| T755 |
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.965595593 |
|
|
Jun 05 07:42:33 PM PDT 24 |
Jun 05 07:48:43 PM PDT 24 |
3521623096 ps |
| T1285 |
/workspace/coverage/default/4.chip_tap_straps_prod.1501686381 |
|
|
Jun 05 07:40:15 PM PDT 24 |
Jun 05 07:42:32 PM PDT 24 |
2193200823 ps |
| T1286 |
/workspace/coverage/default/9.chip_sw_all_escalation_resets.791343298 |
|
|
Jun 05 07:42:51 PM PDT 24 |
Jun 05 07:54:59 PM PDT 24 |
4430445934 ps |
| T1287 |
/workspace/coverage/default/2.rom_keymgr_functest.3084779493 |
|
|
Jun 05 07:40:31 PM PDT 24 |
Jun 05 07:49:04 PM PDT 24 |
4801023800 ps |
| T1288 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.885784665 |
|
|
Jun 05 07:15:00 PM PDT 24 |
Jun 05 07:27:57 PM PDT 24 |
4417669788 ps |
| T1289 |
/workspace/coverage/default/65.chip_sw_all_escalation_resets.1696700439 |
|
|
Jun 05 07:47:54 PM PDT 24 |
Jun 05 07:56:10 PM PDT 24 |
4795131712 ps |
| T1290 |
/workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.489912505 |
|
|
Jun 05 07:26:02 PM PDT 24 |
Jun 05 07:33:48 PM PDT 24 |
9819062757 ps |
| T1291 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.33187074 |
|
|
Jun 05 07:23:19 PM PDT 24 |
Jun 05 08:39:56 PM PDT 24 |
18024072760 ps |
| T1292 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.2378570217 |
|
|
Jun 05 07:22:04 PM PDT 24 |
Jun 05 07:38:36 PM PDT 24 |
5865000810 ps |
| T836 |
/workspace/coverage/default/82.chip_sw_all_escalation_resets.2459004843 |
|
|
Jun 05 07:49:00 PM PDT 24 |
Jun 05 07:58:15 PM PDT 24 |
4528173576 ps |
| T1293 |
/workspace/coverage/default/2.chip_sw_kmac_app_rom.421819028 |
|
|
Jun 05 07:34:03 PM PDT 24 |
Jun 05 07:39:34 PM PDT 24 |
2981543960 ps |
| T53 |
/workspace/coverage/default/1.chip_sw_spi_device_tpm.3812457611 |
|
|
Jun 05 07:20:35 PM PDT 24 |
Jun 05 07:25:21 PM PDT 24 |
3675457317 ps |
| T1294 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.1344728747 |
|
|
Jun 05 07:13:00 PM PDT 24 |
Jun 05 07:24:43 PM PDT 24 |
5416258460 ps |
| T1295 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod.2370654550 |
|
|
Jun 05 07:34:42 PM PDT 24 |
Jun 05 08:42:09 PM PDT 24 |
14534280099 ps |
| T1296 |
/workspace/coverage/default/1.chip_sw_kmac_smoketest.4264289846 |
|
|
Jun 05 07:29:43 PM PDT 24 |
Jun 05 07:36:30 PM PDT 24 |
3193529352 ps |
| T1297 |
/workspace/coverage/default/1.chip_sw_aes_enc.3217650279 |
|
|
Jun 05 07:24:08 PM PDT 24 |
Jun 05 07:28:03 PM PDT 24 |
2403039528 ps |
| T539 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.582539387 |
|
|
Jun 05 07:35:59 PM PDT 24 |
Jun 05 07:48:16 PM PDT 24 |
4716083523 ps |
| T1298 |
/workspace/coverage/default/0.chip_tap_straps_rma.2649428995 |
|
|
Jun 05 07:13:13 PM PDT 24 |
Jun 05 07:19:31 PM PDT 24 |
4800378506 ps |
| T1299 |
/workspace/coverage/default/0.rom_e2e_asm_init_prod.1044448184 |
|
|
Jun 05 07:24:15 PM PDT 24 |
Jun 05 08:28:57 PM PDT 24 |
13933280432 ps |
| T1300 |
/workspace/coverage/default/0.chip_sw_data_integrity_escalation.4191050558 |
|
|
Jun 05 07:11:15 PM PDT 24 |
Jun 05 07:25:39 PM PDT 24 |
5177034840 ps |
| T715 |
/workspace/coverage/default/31.chip_sw_all_escalation_resets.3201514956 |
|
|
Jun 05 07:45:03 PM PDT 24 |
Jun 05 07:53:34 PM PDT 24 |
4427900208 ps |
| T1301 |
/workspace/coverage/default/0.chip_sw_aes_masking_off.3554545607 |
|
|
Jun 05 07:14:30 PM PDT 24 |
Jun 05 07:18:30 PM PDT 24 |
2535142016 ps |
| T1302 |
/workspace/coverage/default/1.chip_sw_hmac_enc_idle.270957490 |
|
|
Jun 05 07:25:59 PM PDT 24 |
Jun 05 07:31:17 PM PDT 24 |
3470599914 ps |
| T235 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.2947449515 |
|
|
Jun 05 07:25:14 PM PDT 24 |
Jun 05 08:31:00 PM PDT 24 |
17420782132 ps |
| T802 |
/workspace/coverage/default/42.chip_sw_all_escalation_resets.3655460066 |
|
|
Jun 05 07:46:41 PM PDT 24 |
Jun 05 07:57:34 PM PDT 24 |
5645530168 ps |
| T799 |
/workspace/coverage/default/53.chip_sw_all_escalation_resets.1642214212 |
|
|
Jun 05 07:48:38 PM PDT 24 |
Jun 05 07:58:28 PM PDT 24 |
4961483980 ps |
| T1303 |
/workspace/coverage/default/1.chip_sw_aes_idle.3179793729 |
|
|
Jun 05 07:22:44 PM PDT 24 |
Jun 05 07:28:18 PM PDT 24 |
3302816854 ps |
| T139 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.157629784 |
|
|
Jun 05 07:15:35 PM PDT 24 |
Jun 05 07:21:36 PM PDT 24 |
5039959916 ps |
| T1304 |
/workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.4279861335 |
|
|
Jun 05 07:33:06 PM PDT 24 |
Jun 05 08:23:16 PM PDT 24 |
11545529052 ps |
| T1305 |
/workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.2464985767 |
|
|
Jun 05 07:34:32 PM PDT 24 |
Jun 05 07:59:31 PM PDT 24 |
8068751688 ps |
| T805 |
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.2905910233 |
|
|
Jun 05 07:41:08 PM PDT 24 |
Jun 05 07:48:03 PM PDT 24 |
4101192960 ps |
| T790 |
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.2197200994 |
|
|
Jun 05 07:49:58 PM PDT 24 |
Jun 05 07:56:51 PM PDT 24 |
3618844328 ps |
| T90 |
/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.1084939534 |
|
|
Jun 05 07:40:44 PM PDT 24 |
Jun 05 07:46:37 PM PDT 24 |
3400504328 ps |
| T1306 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.2744396736 |
|
|
Jun 05 07:20:49 PM PDT 24 |
Jun 05 07:27:43 PM PDT 24 |
4157104400 ps |
| T1307 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.2413403491 |
|
|
Jun 05 07:25:33 PM PDT 24 |
Jun 05 07:35:21 PM PDT 24 |
4466503766 ps |
| T701 |
/workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.4181376075 |
|
|
Jun 05 07:40:28 PM PDT 24 |
Jun 05 10:09:23 PM PDT 24 |
45097801832 ps |
| T1308 |
/workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.2452822809 |
|
|
Jun 05 07:21:35 PM PDT 24 |
Jun 05 07:29:09 PM PDT 24 |
3688288372 ps |
| T1309 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1640320188 |
|
|
Jun 05 07:22:12 PM PDT 24 |
Jun 05 07:32:37 PM PDT 24 |
7613103280 ps |
| T22 |
/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.1984193707 |
|
|
Jun 05 07:32:41 PM PDT 24 |
Jun 05 07:37:39 PM PDT 24 |
3344802870 ps |
| T1310 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1057323326 |
|
|
Jun 05 07:23:55 PM PDT 24 |
Jun 05 08:27:25 PM PDT 24 |
12972244932 ps |
| T155 |
/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.170008831 |
|
|
Jun 05 07:30:14 PM PDT 24 |
Jun 05 10:24:47 PM PDT 24 |
59201093477 ps |
| T826 |
/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2135468019 |
|
|
Jun 05 07:44:34 PM PDT 24 |
Jun 05 07:52:52 PM PDT 24 |
3688398952 ps |
| T1311 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.3426022688 |
|
|
Jun 05 07:32:42 PM PDT 24 |
Jun 05 07:43:34 PM PDT 24 |
5486876020 ps |
| T330 |
/workspace/coverage/default/0.chip_sw_entropy_src_csrng.4186294274 |
|
|
Jun 05 07:14:28 PM PDT 24 |
Jun 05 07:44:08 PM PDT 24 |
7257410934 ps |
| T716 |
/workspace/coverage/default/15.chip_sw_all_escalation_resets.2083808184 |
|
|
Jun 05 07:43:21 PM PDT 24 |
Jun 05 07:54:30 PM PDT 24 |
4990268012 ps |
| T1312 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.3300058433 |
|
|
Jun 05 07:15:07 PM PDT 24 |
Jun 05 07:20:46 PM PDT 24 |
2711190240 ps |
| T1313 |
/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.696479304 |
|
|
Jun 05 07:44:40 PM PDT 24 |
Jun 05 07:52:48 PM PDT 24 |
3796162264 ps |
| T1314 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.1525680092 |
|
|
Jun 05 07:18:42 PM PDT 24 |
Jun 05 10:50:32 PM PDT 24 |
76581456012 ps |
| T813 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.2289677708 |
|
|
Jun 05 07:34:06 PM PDT 24 |
Jun 05 07:42:24 PM PDT 24 |
4065874960 ps |
| T1315 |
/workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.4250087698 |
|
|
Jun 05 07:20:13 PM PDT 24 |
Jun 05 07:25:57 PM PDT 24 |
2695385560 ps |
| T1316 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.1878104722 |
|
|
Jun 05 07:14:04 PM PDT 24 |
Jun 05 07:28:41 PM PDT 24 |
8968193760 ps |
| T756 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.3318390726 |
|
|
Jun 05 07:23:41 PM PDT 24 |
Jun 05 07:30:05 PM PDT 24 |
4011215680 ps |
| T1317 |
/workspace/coverage/default/1.chip_sw_aes_entropy.789830898 |
|
|
Jun 05 07:22:59 PM PDT 24 |
Jun 05 07:28:43 PM PDT 24 |
2898140810 ps |
| T1318 |
/workspace/coverage/default/2.chip_sival_flash_info_access.1842312824 |
|
|
Jun 05 07:30:10 PM PDT 24 |
Jun 05 07:35:32 PM PDT 24 |
3107117080 ps |
| T256 |
/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.1291986823 |
|
|
Jun 05 07:44:50 PM PDT 24 |
Jun 05 07:50:31 PM PDT 24 |
3371021560 ps |
| T1319 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.3104610634 |
|
|
Jun 05 07:20:58 PM PDT 24 |
Jun 05 08:47:20 PM PDT 24 |
45250936965 ps |
| T1320 |
/workspace/coverage/default/2.chip_sw_aon_timer_smoketest.3435782355 |
|
|
Jun 05 07:38:40 PM PDT 24 |
Jun 05 07:42:57 PM PDT 24 |
2730946900 ps |
| T180 |
/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.3327414851 |
|
|
Jun 05 07:19:54 PM PDT 24 |
Jun 05 08:38:54 PM PDT 24 |
43562390244 ps |
| T1321 |
/workspace/coverage/default/2.chip_sw_aes_smoketest.3964441967 |
|
|
Jun 05 07:38:01 PM PDT 24 |
Jun 05 07:42:51 PM PDT 24 |
2921525152 ps |
| T1322 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod.1247646209 |
|
|
Jun 05 07:42:59 PM PDT 24 |
Jun 05 08:34:12 PM PDT 24 |
14672650472 ps |
| T1323 |
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.334574506 |
|
|
Jun 05 07:49:42 PM PDT 24 |
Jun 05 07:55:40 PM PDT 24 |
3730553918 ps |
| T50 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3833523844 |
|
|
Jun 05 07:31:23 PM PDT 24 |
Jun 05 07:39:06 PM PDT 24 |
5366864616 ps |
| T1324 |
/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.485360297 |
|
|
Jun 05 07:45:00 PM PDT 24 |
Jun 05 07:53:02 PM PDT 24 |
4571933824 ps |
| T219 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.3903811047 |
|
|
Jun 05 07:11:25 PM PDT 24 |
Jun 05 08:17:12 PM PDT 24 |
20087186504 ps |
| T163 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.1426466234 |
|
|
Jun 05 07:20:06 PM PDT 24 |
Jun 05 07:22:39 PM PDT 24 |
2283814037 ps |
| T1325 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3926193363 |
|
|
Jun 05 07:31:50 PM PDT 24 |
Jun 05 07:57:26 PM PDT 24 |
12389181571 ps |
| T1326 |
/workspace/coverage/default/0.chip_sw_gpio_smoketest.2285688666 |
|
|
Jun 05 07:18:56 PM PDT 24 |
Jun 05 07:24:08 PM PDT 24 |
2962088897 ps |
| T1327 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.1948657983 |
|
|
Jun 05 07:22:05 PM PDT 24 |
Jun 05 08:16:06 PM PDT 24 |
13517803330 ps |
| T1328 |
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.1734850727 |
|
|
Jun 05 07:41:47 PM PDT 24 |
Jun 05 08:25:20 PM PDT 24 |
13597530280 ps |
| T1329 |
/workspace/coverage/default/0.chip_sw_ast_clk_outputs.82517171 |
|
|
Jun 05 07:14:17 PM PDT 24 |
Jun 05 07:29:44 PM PDT 24 |
7924269016 ps |
| T340 |
/workspace/coverage/default/2.chip_sw_entropy_src_csrng.2236732093 |
|
|
Jun 05 07:34:49 PM PDT 24 |
Jun 05 08:00:40 PM PDT 24 |
7815479228 ps |
| T423 |
/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.4175233947 |
|
|
Jun 05 07:36:10 PM PDT 24 |
Jun 05 07:45:04 PM PDT 24 |
4993300280 ps |
| T1330 |
/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.4106621316 |
|
|
Jun 05 07:22:39 PM PDT 24 |
Jun 05 07:49:42 PM PDT 24 |
12766624038 ps |
| T1331 |
/workspace/coverage/default/3.chip_tap_straps_rma.1947788040 |
|
|
Jun 05 07:39:43 PM PDT 24 |
Jun 05 07:49:08 PM PDT 24 |
6110852803 ps |
| T1332 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1451454925 |
|
|
Jun 05 07:40:42 PM PDT 24 |
Jun 05 07:51:46 PM PDT 24 |
4328534600 ps |
| T188 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.1617509150 |
|
|
Jun 05 07:31:18 PM PDT 24 |
Jun 05 07:43:04 PM PDT 24 |
4915945770 ps |
| T1333 |
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.1879143449 |
|
|
Jun 05 07:41:06 PM PDT 24 |
Jun 05 07:52:58 PM PDT 24 |
6295905528 ps |
| T248 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.2128653258 |
|
|
Jun 05 07:20:27 PM PDT 24 |
Jun 05 08:49:05 PM PDT 24 |
47164083391 ps |
| T1334 |
/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.2636828847 |
|
|
Jun 05 07:37:03 PM PDT 24 |
Jun 05 07:40:55 PM PDT 24 |
2742555339 ps |
| T1335 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.1619072255 |
|
|
Jun 05 07:21:44 PM PDT 24 |
Jun 05 07:30:02 PM PDT 24 |
6451073818 ps |
| T1336 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.1624375103 |
|
|
Jun 05 07:29:40 PM PDT 24 |
Jun 05 07:40:01 PM PDT 24 |
4297297360 ps |
| T1337 |
/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.1040019774 |
|
|
Jun 05 07:42:34 PM PDT 24 |
Jun 05 07:49:54 PM PDT 24 |
3334650640 ps |
| T278 |
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.1853841746 |
|
|
Jun 05 07:41:55 PM PDT 24 |
Jun 05 07:56:01 PM PDT 24 |
5272200536 ps |
| T279 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.2575023381 |
|
|
Jun 05 07:32:58 PM PDT 24 |
Jun 05 08:26:20 PM PDT 24 |
20492057967 ps |
| T280 |
/workspace/coverage/default/60.chip_sw_all_escalation_resets.2242213746 |
|
|
Jun 05 07:47:16 PM PDT 24 |
Jun 05 08:00:19 PM PDT 24 |
5731031110 ps |
| T281 |
/workspace/coverage/default/1.chip_sw_entropy_src_kat_test.2314924287 |
|
|
Jun 05 07:24:16 PM PDT 24 |
Jun 05 07:27:47 PM PDT 24 |
2590235128 ps |
| T282 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.374001962 |
|
|
Jun 05 07:34:47 PM PDT 24 |
Jun 05 07:45:42 PM PDT 24 |
4257431548 ps |
| T283 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.3628116193 |
|
|
Jun 05 07:14:50 PM PDT 24 |
Jun 05 07:24:53 PM PDT 24 |
5361405862 ps |
| T284 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.4181401675 |
|
|
Jun 05 07:27:51 PM PDT 24 |
Jun 05 07:35:55 PM PDT 24 |
4401368776 ps |
| T285 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.2435786401 |
|
|
Jun 05 07:34:25 PM PDT 24 |
Jun 05 08:00:15 PM PDT 24 |
6667151402 ps |
| T286 |
/workspace/coverage/default/0.chip_sw_kmac_mode_cshake.3727396697 |
|
|
Jun 05 07:14:31 PM PDT 24 |
Jun 05 07:18:35 PM PDT 24 |
2473621464 ps |
| T16 |
/workspace/coverage/default/0.chip_sw_sleep_pin_retention.2973374242 |
|
|
Jun 05 07:10:36 PM PDT 24 |
Jun 05 07:15:42 PM PDT 24 |
4441012290 ps |
| T1338 |
/workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3602003431 |
|
|
Jun 05 07:33:56 PM PDT 24 |
Jun 05 07:44:46 PM PDT 24 |
7647484544 ps |
| T1339 |
/workspace/coverage/default/2.chip_sw_power_sleep_load.1424160757 |
|
|
Jun 05 07:39:29 PM PDT 24 |
Jun 05 07:51:16 PM PDT 24 |
10702280082 ps |
| T1340 |
/workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.4102410151 |
|
|
Jun 05 07:42:25 PM PDT 24 |
Jun 05 07:45:37 PM PDT 24 |
3229300286 ps |
| T1341 |
/workspace/coverage/default/1.chip_sw_uart_smoketest.3249875571 |
|
|
Jun 05 07:33:30 PM PDT 24 |
Jun 05 07:37:17 PM PDT 24 |
3515422712 ps |
| T1342 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx.2123206821 |
|
|
Jun 05 07:10:38 PM PDT 24 |
Jun 05 07:21:30 PM PDT 24 |
4493793188 ps |
| T1343 |
/workspace/coverage/default/3.chip_tap_straps_prod.1623637799 |
|
|
Jun 05 07:39:58 PM PDT 24 |
Jun 05 07:55:52 PM PDT 24 |
9846455852 ps |
| T1344 |
/workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.3102095955 |
|
|
Jun 05 07:12:12 PM PDT 24 |
Jun 05 07:21:33 PM PDT 24 |
5220427974 ps |
| T1345 |
/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.3858878777 |
|
|
Jun 05 07:12:48 PM PDT 24 |
Jun 05 07:21:25 PM PDT 24 |
4126888760 ps |
| T1346 |
/workspace/coverage/default/4.chip_sw_all_escalation_resets.1767593709 |
|
|
Jun 05 07:40:31 PM PDT 24 |
Jun 05 07:54:10 PM PDT 24 |
6576042368 ps |
| T416 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.3327921811 |
|
|
Jun 05 07:36:24 PM PDT 24 |
Jun 05 07:58:55 PM PDT 24 |
21494233274 ps |
| T1347 |
/workspace/coverage/default/0.chip_tap_straps_testunlock0.3655900434 |
|
|
Jun 05 07:14:45 PM PDT 24 |
Jun 05 07:18:19 PM PDT 24 |
3026131231 ps |
| T1348 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.1512858073 |
|
|
Jun 05 07:35:17 PM PDT 24 |
Jun 05 07:41:37 PM PDT 24 |
3198243800 ps |
| T1349 |
/workspace/coverage/default/0.rom_e2e_shutdown_exception_c.1110104363 |
|
|
Jun 05 07:19:07 PM PDT 24 |
Jun 05 08:16:08 PM PDT 24 |
13917639640 ps |
| T366 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.411916388 |
|
|
Jun 05 07:28:56 PM PDT 24 |
Jun 05 07:38:23 PM PDT 24 |
6079942450 ps |
| T1350 |
/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.678617314 |
|
|
Jun 05 07:38:47 PM PDT 24 |
Jun 05 08:15:15 PM PDT 24 |
25379388800 ps |
| T23 |
/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3016429307 |
|
|
Jun 05 07:14:29 PM PDT 24 |
Jun 05 07:20:18 PM PDT 24 |
3400486370 ps |
| T1351 |
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.1855554099 |
|
|
Jun 05 07:42:22 PM PDT 24 |
Jun 05 08:07:37 PM PDT 24 |
8879892912 ps |
| T377 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.514696076 |
|
|
Jun 05 07:34:50 PM PDT 24 |
Jun 05 07:53:40 PM PDT 24 |
10846712678 ps |
| T1352 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.310518747 |
|
|
Jun 05 07:18:52 PM PDT 24 |
Jun 05 07:22:58 PM PDT 24 |
2967009660 ps |
| T1353 |
/workspace/coverage/default/1.chip_sw_example_manufacturer.4059556275 |
|
|
Jun 05 07:17:59 PM PDT 24 |
Jun 05 07:22:04 PM PDT 24 |
2529085120 ps |
| T1354 |
/workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.318362607 |
|
|
Jun 05 07:38:59 PM PDT 24 |
Jun 05 07:48:14 PM PDT 24 |
7144610322 ps |
| T1355 |
/workspace/coverage/default/0.chip_sw_aes_entropy.3911727120 |
|
|
Jun 05 07:11:49 PM PDT 24 |
Jun 05 07:15:23 PM PDT 24 |
2733157340 ps |
| T247 |
/workspace/coverage/default/1.chip_sw_flash_init.2215938164 |
|
|
Jun 05 07:20:59 PM PDT 24 |
Jun 05 07:54:31 PM PDT 24 |
16606978242 ps |
| T1356 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.1594102052 |
|
|
Jun 05 07:31:36 PM PDT 24 |
Jun 05 07:33:58 PM PDT 24 |
2467421255 ps |
| T1357 |
/workspace/coverage/default/1.rom_e2e_asm_init_dev.24888855 |
|
|
Jun 05 07:32:12 PM PDT 24 |
Jun 05 08:33:15 PM PDT 24 |
14130296824 ps |
| T700 |
/workspace/coverage/default/2.chip_sw_edn_boot_mode.1942568599 |
|
|
Jun 05 07:32:57 PM PDT 24 |
Jun 05 07:40:49 PM PDT 24 |
3335764958 ps |
| T138 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.686925478 |
|
|
Jun 05 07:26:01 PM PDT 24 |
Jun 05 07:41:37 PM PDT 24 |
6481631362 ps |
| T1358 |
/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.2567236293 |
|
|
Jun 05 07:42:00 PM PDT 24 |
Jun 05 09:00:44 PM PDT 24 |
23264678584 ps |
| T1359 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod_end.2399245578 |
|
|
Jun 05 07:33:16 PM PDT 24 |
Jun 05 08:19:11 PM PDT 24 |
14150986577 ps |
| T1360 |
/workspace/coverage/default/3.chip_tap_straps_dev.3435843965 |
|
|
Jun 05 07:40:33 PM PDT 24 |
Jun 05 07:57:12 PM PDT 24 |
9251509766 ps |
| T830 |
/workspace/coverage/default/34.chip_sw_all_escalation_resets.298679483 |
|
|
Jun 05 07:44:55 PM PDT 24 |
Jun 05 07:55:19 PM PDT 24 |
4311268330 ps |
| T1361 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.388246110 |
|
|
Jun 05 07:22:33 PM PDT 24 |
Jun 05 08:35:06 PM PDT 24 |
14170281052 ps |
| T1362 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.1706998766 |
|
|
Jun 05 07:25:06 PM PDT 24 |
Jun 05 07:39:01 PM PDT 24 |
9111633238 ps |
| T1363 |
/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.4049086801 |
|
|
Jun 05 07:45:48 PM PDT 24 |
Jun 05 07:52:17 PM PDT 24 |
3717641640 ps |
| T1364 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2498249866 |
|
|
Jun 05 07:21:50 PM PDT 24 |
Jun 05 07:42:44 PM PDT 24 |
13594505825 ps |
| T1365 |
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.2418815543 |
|
|
Jun 05 07:42:05 PM PDT 24 |
Jun 05 07:47:09 PM PDT 24 |
3094986020 ps |
| T1366 |
/workspace/coverage/default/2.chip_sw_kmac_mode_cshake.400142557 |
|
|
Jun 05 07:35:21 PM PDT 24 |
Jun 05 07:38:44 PM PDT 24 |
3025875320 ps |
| T535 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.3322493368 |
|
|
Jun 05 07:32:44 PM PDT 24 |
Jun 05 07:49:02 PM PDT 24 |
4953256040 ps |
| T335 |
/workspace/coverage/default/0.chip_plic_all_irqs_20.572334019 |
|
|
Jun 05 07:12:56 PM PDT 24 |
Jun 05 07:26:04 PM PDT 24 |
5362311166 ps |
| T1367 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_peri.4141820398 |
|
|
Jun 05 07:27:48 PM PDT 24 |
Jun 05 07:55:26 PM PDT 24 |
12179584744 ps |
| T236 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.2244120281 |
|
|
Jun 05 07:13:17 PM PDT 24 |
Jun 05 08:15:04 PM PDT 24 |
14460001060 ps |
| T1368 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_status.1829709243 |
|
|
Jun 05 07:25:56 PM PDT 24 |
Jun 05 07:29:31 PM PDT 24 |
1931742147 ps |
| T1369 |
/workspace/coverage/default/63.chip_sw_all_escalation_resets.2110654354 |
|
|
Jun 05 07:48:17 PM PDT 24 |
Jun 05 07:56:55 PM PDT 24 |
4740231008 ps |
| T274 |
/workspace/coverage/default/35.chip_sw_all_escalation_resets.960842223 |
|
|
Jun 05 07:43:59 PM PDT 24 |
Jun 05 07:52:16 PM PDT 24 |
5177603580 ps |
| T1370 |
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.529167188 |
|
|
Jun 05 07:41:26 PM PDT 24 |
Jun 05 07:49:28 PM PDT 24 |
6759826280 ps |
| T1371 |
/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.1582998623 |
|
|
Jun 05 07:13:33 PM PDT 24 |
Jun 05 07:24:23 PM PDT 24 |
4904835992 ps |
| T1372 |
/workspace/coverage/default/0.chip_sw_alert_handler_entropy.3866511005 |
|
|
Jun 05 07:14:40 PM PDT 24 |
Jun 05 07:20:12 PM PDT 24 |
3139064998 ps |
| T1373 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.53521243 |
|
|
Jun 05 07:31:23 PM PDT 24 |
Jun 05 07:43:31 PM PDT 24 |
4930122930 ps |
| T833 |
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.2275204579 |
|
|
Jun 05 07:48:25 PM PDT 24 |
Jun 05 07:54:55 PM PDT 24 |
4006679756 ps |
| T1374 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1036669375 |
|
|
Jun 05 07:29:46 PM PDT 24 |
Jun 05 07:40:05 PM PDT 24 |
5448126952 ps |
| T1375 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3322972477 |
|
|
Jun 05 07:14:43 PM PDT 24 |
Jun 05 07:20:57 PM PDT 24 |
3193037553 ps |
| T1376 |
/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.1558035475 |
|
|
Jun 05 07:45:28 PM PDT 24 |
Jun 05 07:52:46 PM PDT 24 |
3692153856 ps |
| T1377 |
/workspace/coverage/default/19.chip_sw_uart_rand_baudrate.3183903740 |
|
|
Jun 05 07:44:32 PM PDT 24 |
Jun 05 08:06:23 PM PDT 24 |
7768670688 ps |
| T792 |
/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.2739197868 |
|
|
Jun 05 07:44:45 PM PDT 24 |
Jun 05 07:51:43 PM PDT 24 |
3609937000 ps |
| T1378 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.4128484184 |
|
|
Jun 05 07:31:49 PM PDT 24 |
Jun 05 08:01:16 PM PDT 24 |
8112890897 ps |
| T1379 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.453920517 |
|
|
Jun 05 07:30:34 PM PDT 24 |
Jun 05 07:46:00 PM PDT 24 |
5869943790 ps |
| T1380 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.1276244346 |
|
|
Jun 05 07:20:46 PM PDT 24 |
Jun 05 08:49:40 PM PDT 24 |
46779815440 ps |
| T181 |
/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.322488555 |
|
|
Jun 05 07:11:23 PM PDT 24 |
Jun 05 08:35:23 PM PDT 24 |
43321358418 ps |
| T1381 |
/workspace/coverage/default/2.chip_sw_entropy_src_smoketest.2749031233 |
|
|
Jun 05 07:39:52 PM PDT 24 |
Jun 05 07:49:08 PM PDT 24 |
4558815132 ps |
| T183 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.895181777 |
|
|
Jun 05 07:15:22 PM PDT 24 |
Jun 05 07:29:54 PM PDT 24 |
8035416596 ps |
| T1382 |
/workspace/coverage/default/0.rom_e2e_smoke.2533795162 |
|
|
Jun 05 07:20:28 PM PDT 24 |
Jun 05 08:21:06 PM PDT 24 |
14640621288 ps |
| T1383 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.1299791468 |
|
|
Jun 05 07:41:17 PM PDT 24 |
Jun 05 07:54:01 PM PDT 24 |
4598832532 ps |
| T1384 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.4131431307 |
|
|
Jun 05 07:15:05 PM PDT 24 |
Jun 05 07:21:05 PM PDT 24 |
3527167866 ps |
| T1385 |
/workspace/coverage/default/1.chip_sw_kmac_idle.272746925 |
|
|
Jun 05 07:24:22 PM PDT 24 |
Jun 05 07:29:47 PM PDT 24 |
3174258980 ps |
| T200 |
/workspace/coverage/default/0.chip_sw_usbdev_vbus.1609278289 |
|
|
Jun 05 07:13:15 PM PDT 24 |
Jun 05 07:16:47 PM PDT 24 |
2690791236 ps |
| T1386 |
/workspace/coverage/default/2.chip_sw_rv_timer_smoketest.3076896353 |
|
|
Jun 05 07:39:12 PM PDT 24 |
Jun 05 07:44:34 PM PDT 24 |
2824907470 ps |
| T1387 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.3120936506 |
|
|
Jun 05 07:32:40 PM PDT 24 |
Jun 05 07:38:57 PM PDT 24 |
3089462620 ps |
| T1388 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3412304011 |
|
|
Jun 05 07:12:53 PM PDT 24 |
Jun 05 08:25:06 PM PDT 24 |
39267973668 ps |
| T383 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.4024321839 |
|
|
Jun 05 07:31:39 PM PDT 24 |
Jun 05 07:48:02 PM PDT 24 |
5094403820 ps |
| T264 |
/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3783353985 |
|
|
Jun 05 07:14:28 PM PDT 24 |
Jun 05 07:24:12 PM PDT 24 |
4440774544 ps |
| T1389 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.2277289949 |
|
|
Jun 05 07:12:56 PM PDT 24 |
Jun 05 08:53:19 PM PDT 24 |
25414991132 ps |
| T1390 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.177131730 |
|
|
Jun 05 07:28:15 PM PDT 24 |
Jun 05 07:32:11 PM PDT 24 |
2581809516 ps |
| T1391 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.1971593745 |
|
|
Jun 05 07:21:27 PM PDT 24 |
Jun 05 07:40:19 PM PDT 24 |
7077366708 ps |
| T1392 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.909909771 |
|
|
Jun 05 07:41:14 PM PDT 24 |
Jun 05 07:52:49 PM PDT 24 |
4243930680 ps |
| T804 |
/workspace/coverage/default/64.chip_sw_all_escalation_resets.544273915 |
|
|
Jun 05 07:47:52 PM PDT 24 |
Jun 05 07:58:32 PM PDT 24 |
5350286392 ps |
| T845 |
/workspace/coverage/default/30.chip_sw_all_escalation_resets.1914143595 |
|
|
Jun 05 07:43:37 PM PDT 24 |
Jun 05 07:52:38 PM PDT 24 |
4381362740 ps |
| T73 |
/workspace/coverage/cover_reg_top/26.xbar_smoke.1690801504 |
|
|
Jun 05 06:50:24 PM PDT 24 |
Jun 05 06:50:35 PM PDT 24 |
221265348 ps |
| T74 |
/workspace/coverage/cover_reg_top/25.xbar_random_slow_rsp.853744407 |
|
|
Jun 05 06:50:14 PM PDT 24 |
Jun 05 07:04:45 PM PDT 24 |
52349045811 ps |
| T75 |
/workspace/coverage/cover_reg_top/58.xbar_error_random.4187596062 |
|
|
Jun 05 06:56:41 PM PDT 24 |
Jun 05 06:56:54 PM PDT 24 |
275967353 ps |
| T127 |
/workspace/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.197852659 |
|
|
Jun 05 06:51:25 PM PDT 24 |
Jun 05 06:53:52 PM PDT 24 |
174547954 ps |
| T128 |
/workspace/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.1005254776 |
|
|
Jun 05 07:00:12 PM PDT 24 |
Jun 05 07:08:26 PM PDT 24 |
11850887791 ps |
| T440 |
/workspace/coverage/cover_reg_top/61.xbar_error_random.391312266 |
|
|
Jun 05 06:57:08 PM PDT 24 |
Jun 05 06:57:40 PM PDT 24 |
317085105 ps |
| T536 |
/workspace/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.1647919011 |
|
|
Jun 05 06:56:17 PM PDT 24 |
Jun 05 07:29:39 PM PDT 24 |
100696964887 ps |
| T439 |
/workspace/coverage/cover_reg_top/33.xbar_error_random.872316076 |
|
|
Jun 05 06:52:00 PM PDT 24 |
Jun 05 06:52:37 PM PDT 24 |
395778655 ps |
| T537 |
/workspace/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.3381286329 |
|
|
Jun 05 07:01:24 PM PDT 24 |
Jun 05 07:09:47 PM PDT 24 |
9569039565 ps |
| T441 |
/workspace/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.1362014654 |
|
|
Jun 05 06:55:06 PM PDT 24 |
Jun 05 06:56:01 PM PDT 24 |
3130134521 ps |
| T442 |
/workspace/coverage/cover_reg_top/71.xbar_random_large_delays.3921160302 |
|
|
Jun 05 06:59:04 PM PDT 24 |
Jun 05 07:00:44 PM PDT 24 |
9031483195 ps |
| T448 |
/workspace/coverage/cover_reg_top/9.xbar_smoke_zero_delays.2850776192 |
|
|
Jun 05 06:45:24 PM PDT 24 |
Jun 05 06:45:31 PM PDT 24 |
42312294 ps |
| T548 |
/workspace/coverage/cover_reg_top/94.xbar_smoke_zero_delays.3232678636 |
|
|
Jun 05 07:02:55 PM PDT 24 |
Jun 05 07:03:01 PM PDT 24 |
44227558 ps |
| T547 |
/workspace/coverage/cover_reg_top/73.xbar_same_source.3849562104 |
|
|
Jun 05 06:59:22 PM PDT 24 |
Jun 05 06:59:44 PM PDT 24 |
255755343 ps |
| T545 |
/workspace/coverage/cover_reg_top/26.xbar_random_large_delays.2700342069 |
|
|
Jun 05 06:50:32 PM PDT 24 |
Jun 05 06:52:55 PM PDT 24 |
13779546787 ps |
| T419 |
/workspace/coverage/cover_reg_top/93.xbar_stress_all.2352812437 |
|
|
Jun 05 07:02:55 PM PDT 24 |
Jun 05 07:06:51 PM PDT 24 |
2808355564 ps |