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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.06 95.60 94.23 95.49 95.03 96.47 99.51


Total test records in report: 2881
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T271 /workspace/coverage/default/1.chip_sw_data_integrity_escalation.1707268848 Jun 06 04:16:48 PM PDT 24 Jun 06 04:31:47 PM PDT 24 6214812608 ps
T948 /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.903569083 Jun 06 04:11:45 PM PDT 24 Jun 06 04:38:46 PM PDT 24 9881065366 ps
T949 /workspace/coverage/default/0.chip_sw_edn_sw_mode.4260960996 Jun 06 04:14:04 PM PDT 24 Jun 06 04:58:23 PM PDT 24 10186096264 ps
T311 /workspace/coverage/default/10.chip_sw_all_escalation_resets.1050874817 Jun 06 04:40:39 PM PDT 24 Jun 06 04:49:12 PM PDT 24 4439495140 ps
T735 /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.97570540 Jun 06 04:47:47 PM PDT 24 Jun 06 04:56:59 PM PDT 24 3810850536 ps
T376 /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.3655645813 Jun 06 04:44:18 PM PDT 24 Jun 06 04:51:30 PM PDT 24 3974420244 ps
T84 /workspace/coverage/default/1.chip_jtag_mem_access.2464003681 Jun 06 04:16:41 PM PDT 24 Jun 06 04:42:56 PM PDT 24 13829075800 ps
T145 /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.4284615101 Jun 06 04:31:31 PM PDT 24 Jun 06 04:36:11 PM PDT 24 3245142312 ps
T174 /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.2013569185 Jun 06 04:11:33 PM PDT 24 Jun 06 04:14:29 PM PDT 24 3274336333 ps
T363 /workspace/coverage/default/1.chip_sival_flash_info_access.3703474147 Jun 06 04:19:41 PM PDT 24 Jun 06 04:24:52 PM PDT 24 3523290050 ps
T950 /workspace/coverage/default/1.chip_sw_aes_entropy.1612513414 Jun 06 04:22:33 PM PDT 24 Jun 06 04:27:31 PM PDT 24 3205349184 ps
T951 /workspace/coverage/default/2.rom_e2e_asm_init_dev.2849602443 Jun 06 04:41:21 PM PDT 24 Jun 06 05:29:10 PM PDT 24 14566014528 ps
T365 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.2401120018 Jun 06 04:27:30 PM PDT 24 Jun 06 04:38:43 PM PDT 24 4829915348 ps
T952 /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.2046710939 Jun 06 04:09:48 PM PDT 24 Jun 06 04:19:12 PM PDT 24 4392591912 ps
T202 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.4249419246 Jun 06 04:31:05 PM PDT 24 Jun 06 04:40:42 PM PDT 24 4650971349 ps
T953 /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.611251390 Jun 06 04:27:23 PM PDT 24 Jun 06 04:35:34 PM PDT 24 5530440120 ps
T257 /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.607311382 Jun 06 04:18:42 PM PDT 24 Jun 06 04:23:59 PM PDT 24 3221045428 ps
T781 /workspace/coverage/default/1.chip_sw_all_escalation_resets.3138966348 Jun 06 04:15:20 PM PDT 24 Jun 06 04:23:59 PM PDT 24 5960080112 ps
T180 /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.39217387 Jun 06 04:13:28 PM PDT 24 Jun 06 04:17:21 PM PDT 24 2857236500 ps
T295 /workspace/coverage/default/23.chip_sw_all_escalation_resets.1578023828 Jun 06 04:41:17 PM PDT 24 Jun 06 04:51:39 PM PDT 24 5396184674 ps
T296 /workspace/coverage/default/1.chip_sw_aes_idle.3143258959 Jun 06 04:21:16 PM PDT 24 Jun 06 04:25:37 PM PDT 24 2617726830 ps
T297 /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.349766160 Jun 06 04:20:53 PM PDT 24 Jun 06 04:25:05 PM PDT 24 3476692824 ps
T298 /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.314477230 Jun 06 04:41:26 PM PDT 24 Jun 06 05:11:53 PM PDT 24 8400728376 ps
T299 /workspace/coverage/default/0.chip_sw_aes_masking_off.2734118013 Jun 06 04:12:05 PM PDT 24 Jun 06 04:17:04 PM PDT 24 2857666529 ps
T300 /workspace/coverage/default/1.chip_sw_edn_sw_mode.3889169760 Jun 06 04:20:42 PM PDT 24 Jun 06 05:04:22 PM PDT 24 10648169454 ps
T89 /workspace/coverage/default/2.chip_sw_alert_handler_entropy.2317191252 Jun 06 04:30:06 PM PDT 24 Jun 06 04:37:44 PM PDT 24 3126849385 ps
T301 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.3891851339 Jun 06 04:34:10 PM PDT 24 Jun 06 05:28:38 PM PDT 24 14806525850 ps
T302 /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.3129243931 Jun 06 04:18:43 PM PDT 24 Jun 06 04:29:02 PM PDT 24 4301532668 ps
T954 /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.4103407030 Jun 06 04:40:39 PM PDT 24 Jun 06 04:47:47 PM PDT 24 6429383832 ps
T133 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3805142005 Jun 06 04:32:26 PM PDT 24 Jun 06 04:41:24 PM PDT 24 4963990344 ps
T360 /workspace/coverage/default/75.chip_sw_all_escalation_resets.3487084447 Jun 06 04:45:30 PM PDT 24 Jun 06 04:55:23 PM PDT 24 4163575168 ps
T269 /workspace/coverage/default/2.rom_e2e_shutdown_output.1401888133 Jun 06 04:38:20 PM PDT 24 Jun 06 05:40:29 PM PDT 24 24702231420 ps
T387 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.1649946457 Jun 06 04:20:54 PM PDT 24 Jun 06 05:52:27 PM PDT 24 22805780956 ps
T955 /workspace/coverage/default/1.chip_sw_hmac_oneshot.392895167 Jun 06 04:24:17 PM PDT 24 Jun 06 04:30:30 PM PDT 24 2621631416 ps
T956 /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.2461088690 Jun 06 04:12:18 PM PDT 24 Jun 06 04:19:31 PM PDT 24 3003557240 ps
T780 /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.1705167260 Jun 06 04:48:24 PM PDT 24 Jun 06 04:54:28 PM PDT 24 4048043052 ps
T715 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.28182420 Jun 06 04:12:19 PM PDT 24 Jun 06 04:14:26 PM PDT 24 2365226999 ps
T957 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.2404079240 Jun 06 04:26:14 PM PDT 24 Jun 06 05:58:11 PM PDT 24 21857911684 ps
T958 /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.968746448 Jun 06 04:31:06 PM PDT 24 Jun 06 04:40:25 PM PDT 24 7341302392 ps
T175 /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.1231883752 Jun 06 04:12:49 PM PDT 24 Jun 06 04:15:20 PM PDT 24 3569482198 ps
T716 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.420261525 Jun 06 04:18:50 PM PDT 24 Jun 06 04:20:31 PM PDT 24 2203538868 ps
T829 /workspace/coverage/default/6.chip_sw_all_escalation_resets.1383698910 Jun 06 04:40:32 PM PDT 24 Jun 06 04:49:46 PM PDT 24 4934278600 ps
T763 /workspace/coverage/default/88.chip_sw_all_escalation_resets.1396087683 Jun 06 04:46:12 PM PDT 24 Jun 06 04:54:28 PM PDT 24 5666646064 ps
T959 /workspace/coverage/default/1.chip_sw_edn_auto_mode.1687954840 Jun 06 04:22:34 PM PDT 24 Jun 06 04:46:34 PM PDT 24 5876244546 ps
T960 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.1667046822 Jun 06 04:24:36 PM PDT 24 Jun 06 04:36:32 PM PDT 24 6484187600 ps
T786 /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.973390481 Jun 06 04:43:02 PM PDT 24 Jun 06 04:49:09 PM PDT 24 3710225306 ps
T961 /workspace/coverage/default/2.chip_sw_aes_smoketest.1453248873 Jun 06 04:37:04 PM PDT 24 Jun 06 04:41:26 PM PDT 24 3163327900 ps
T845 /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.35357934 Jun 06 04:46:07 PM PDT 24 Jun 06 04:52:23 PM PDT 24 3505968420 ps
T7 /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.4226201794 Jun 06 04:37:22 PM PDT 24 Jun 06 04:45:30 PM PDT 24 5102429376 ps
T442 /workspace/coverage/default/99.chip_sw_all_escalation_resets.2346741058 Jun 06 04:47:08 PM PDT 24 Jun 06 04:56:38 PM PDT 24 5340986212 ps
T207 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.1643031049 Jun 06 04:38:10 PM PDT 24 Jun 06 04:50:20 PM PDT 24 4873270824 ps
T443 /workspace/coverage/default/0.rom_e2e_asm_init_rma.409323878 Jun 06 04:23:06 PM PDT 24 Jun 06 05:21:17 PM PDT 24 14802682536 ps
T444 /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.3040198040 Jun 06 04:27:20 PM PDT 24 Jun 06 04:35:30 PM PDT 24 5201929660 ps
T445 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1806684741 Jun 06 04:26:19 PM PDT 24 Jun 06 05:28:25 PM PDT 24 14307007472 ps
T123 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1205249181 Jun 06 04:21:27 PM PDT 24 Jun 06 04:41:35 PM PDT 24 7789291433 ps
T11 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.4222993524 Jun 06 04:33:51 PM PDT 24 Jun 06 04:53:49 PM PDT 24 21530844390 ps
T446 /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.1634243306 Jun 06 04:28:33 PM PDT 24 Jun 06 04:55:39 PM PDT 24 8587111256 ps
T13 /workspace/coverage/default/0.chip_sw_sleep_pin_retention.3935719245 Jun 06 04:09:26 PM PDT 24 Jun 06 04:15:52 PM PDT 24 4821706360 ps
T151 /workspace/coverage/default/1.chip_sw_otbn_smoketest.1203768435 Jun 06 04:29:02 PM PDT 24 Jun 06 04:47:34 PM PDT 24 5337798184 ps
T333 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.3429802326 Jun 06 04:11:38 PM PDT 24 Jun 06 04:24:06 PM PDT 24 4911105638 ps
T962 /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.636776100 Jun 06 04:15:34 PM PDT 24 Jun 06 04:19:24 PM PDT 24 2895993880 ps
T963 /workspace/coverage/default/2.chip_sw_aes_idle.374024219 Jun 06 04:31:48 PM PDT 24 Jun 06 04:36:05 PM PDT 24 2108121416 ps
T787 /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.2217901002 Jun 06 04:41:54 PM PDT 24 Jun 06 04:48:19 PM PDT 24 4082535320 ps
T964 /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.915761653 Jun 06 04:44:27 PM PDT 24 Jun 06 04:51:59 PM PDT 24 4134381112 ps
T229 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.854595462 Jun 06 04:24:09 PM PDT 24 Jun 06 04:32:10 PM PDT 24 5768773532 ps
T965 /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.439691985 Jun 06 04:32:53 PM PDT 24 Jun 06 04:36:34 PM PDT 24 3223840348 ps
T134 /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.2627203172 Jun 06 04:11:29 PM PDT 24 Jun 06 04:26:10 PM PDT 24 6452341924 ps
T92 /workspace/coverage/default/25.chip_sw_all_escalation_resets.4278252821 Jun 06 04:41:05 PM PDT 24 Jun 06 04:49:07 PM PDT 24 3890314976 ps
T97 /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.843528045 Jun 06 04:17:03 PM PDT 24 Jun 06 04:27:28 PM PDT 24 5349770564 ps
T98 /workspace/coverage/default/0.chip_sw_otbn_randomness.2747933902 Jun 06 04:11:07 PM PDT 24 Jun 06 04:28:03 PM PDT 24 6022852900 ps
T99 /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.4225697959 Jun 06 04:13:04 PM PDT 24 Jun 06 04:17:52 PM PDT 24 3166300496 ps
T100 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2046403574 Jun 06 04:34:11 PM PDT 24 Jun 06 04:40:04 PM PDT 24 3739945232 ps
T101 /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.1141417788 Jun 06 04:41:08 PM PDT 24 Jun 06 05:04:20 PM PDT 24 7993410336 ps
T102 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.1699981625 Jun 06 04:29:04 PM PDT 24 Jun 06 04:44:30 PM PDT 24 5053876708 ps
T103 /workspace/coverage/default/0.chip_sw_aes_smoketest.875109969 Jun 06 04:15:02 PM PDT 24 Jun 06 04:19:56 PM PDT 24 2862222280 ps
T104 /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.1991579201 Jun 06 04:40:59 PM PDT 24 Jun 06 04:47:57 PM PDT 24 3373671500 ps
T105 /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.443037185 Jun 06 04:29:35 PM PDT 24 Jun 06 04:37:15 PM PDT 24 3444220610 ps
T966 /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.2846156203 Jun 06 04:39:19 PM PDT 24 Jun 06 05:02:28 PM PDT 24 8711863112 ps
T456 /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.3265639340 Jun 06 04:28:25 PM PDT 24 Jun 06 04:32:19 PM PDT 24 3002413232 ps
T826 /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.1922701482 Jun 06 04:42:17 PM PDT 24 Jun 06 04:49:29 PM PDT 24 4336420860 ps
T967 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.2830565571 Jun 06 04:21:29 PM PDT 24 Jun 06 05:41:12 PM PDT 24 17456573060 ps
T163 /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2666542352 Jun 06 04:09:49 PM PDT 24 Jun 06 04:11:22 PM PDT 24 2400982300 ps
T784 /workspace/coverage/default/45.chip_sw_all_escalation_resets.2879598956 Jun 06 04:42:40 PM PDT 24 Jun 06 04:52:28 PM PDT 24 5948567392 ps
T968 /workspace/coverage/default/1.chip_sw_uart_tx_rx.2655420157 Jun 06 04:16:52 PM PDT 24 Jun 06 04:25:32 PM PDT 24 4727215436 ps
T969 /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.366256587 Jun 06 04:19:30 PM PDT 24 Jun 06 05:19:41 PM PDT 24 14425781738 ps
T970 /workspace/coverage/default/2.rom_e2e_asm_init_rma.3808558324 Jun 06 04:42:16 PM PDT 24 Jun 06 05:28:59 PM PDT 24 14907882183 ps
T971 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.2257302634 Jun 06 04:18:48 PM PDT 24 Jun 06 05:09:16 PM PDT 24 10554443464 ps
T972 /workspace/coverage/default/1.chip_sw_edn_kat.4062819319 Jun 06 04:21:29 PM PDT 24 Jun 06 04:32:35 PM PDT 24 3472971200 ps
T973 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1310244201 Jun 06 04:33:20 PM PDT 24 Jun 06 04:44:44 PM PDT 24 4361320442 ps
T737 /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.3392958869 Jun 06 04:46:09 PM PDT 24 Jun 06 04:52:05 PM PDT 24 4356493188 ps
T785 /workspace/coverage/default/14.chip_sw_all_escalation_resets.285700802 Jun 06 04:42:30 PM PDT 24 Jun 06 04:54:30 PM PDT 24 6067459526 ps
T974 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.3072420806 Jun 06 04:15:12 PM PDT 24 Jun 06 05:15:40 PM PDT 24 16157005196 ps
T85 /workspace/coverage/default/0.chip_jtag_mem_access.1719873042 Jun 06 04:04:00 PM PDT 24 Jun 06 04:29:43 PM PDT 24 13805436119 ps
T341 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.3569257730 Jun 06 04:16:36 PM PDT 24 Jun 06 04:28:47 PM PDT 24 4386721240 ps
T717 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.267197466 Jun 06 04:28:26 PM PDT 24 Jun 06 04:30:28 PM PDT 24 2469318823 ps
T37 /workspace/coverage/default/0.chip_sw_usbdev_setuprx.1238498634 Jun 06 04:09:17 PM PDT 24 Jun 06 04:18:25 PM PDT 24 4093899414 ps
T975 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.894103079 Jun 06 04:34:28 PM PDT 24 Jun 06 04:43:08 PM PDT 24 3727665240 ps
T976 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.3218145649 Jun 06 04:11:59 PM PDT 24 Jun 06 04:37:32 PM PDT 24 7411654400 ps
T34 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.3491780763 Jun 06 04:11:00 PM PDT 24 Jun 06 04:45:22 PM PDT 24 24300693942 ps
T15 /workspace/coverage/default/2.chip_sw_sleep_pin_wake.3517817319 Jun 06 04:29:07 PM PDT 24 Jun 06 04:36:55 PM PDT 24 6027681480 ps
T366 /workspace/coverage/default/82.chip_sw_all_escalation_resets.431725891 Jun 06 04:48:18 PM PDT 24 Jun 06 04:58:15 PM PDT 24 4697808250 ps
T66 /workspace/coverage/default/1.chip_sw_alert_test.3689353053 Jun 06 04:20:41 PM PDT 24 Jun 06 04:26:21 PM PDT 24 3017642024 ps
T251 /workspace/coverage/default/71.chip_sw_all_escalation_resets.1767266824 Jun 06 04:44:51 PM PDT 24 Jun 06 04:52:52 PM PDT 24 4864858280 ps
T410 /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.2889611879 Jun 06 04:11:20 PM PDT 24 Jun 06 04:18:08 PM PDT 24 4312549048 ps
T390 /workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.574287361 Jun 06 04:29:28 PM PDT 24 Jun 06 04:33:41 PM PDT 24 2547417580 ps
T411 /workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.236717488 Jun 06 04:40:28 PM PDT 24 Jun 06 06:01:17 PM PDT 24 23391475408 ps
T273 /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.4152822302 Jun 06 04:20:50 PM PDT 24 Jun 06 04:29:30 PM PDT 24 4107856044 ps
T412 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.1810086312 Jun 06 04:11:04 PM PDT 24 Jun 06 05:25:56 PM PDT 24 19459867196 ps
T413 /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.629580622 Jun 06 04:37:00 PM PDT 24 Jun 06 04:44:07 PM PDT 24 3495258530 ps
T176 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.905703671 Jun 06 04:33:22 PM PDT 24 Jun 06 04:45:03 PM PDT 24 6171505572 ps
T778 /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.2628454395 Jun 06 04:41:11 PM PDT 24 Jun 06 04:48:16 PM PDT 24 4084889508 ps
T977 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1229476996 Jun 06 04:30:02 PM PDT 24 Jun 06 04:36:50 PM PDT 24 3058105519 ps
T978 /workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.4194337866 Jun 06 04:12:50 PM PDT 24 Jun 06 04:34:39 PM PDT 24 7899799568 ps
T348 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.45554739 Jun 06 04:11:08 PM PDT 24 Jun 06 04:24:46 PM PDT 24 4170687763 ps
T364 /workspace/coverage/default/2.chip_sival_flash_info_access.1593680218 Jun 06 04:28:28 PM PDT 24 Jun 06 04:33:49 PM PDT 24 3074462172 ps
T760 /workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.836904527 Jun 06 04:19:58 PM PDT 24 Jun 06 05:07:29 PM PDT 24 14217076842 ps
T979 /workspace/coverage/default/1.chip_sw_example_manufacturer.3101746558 Jun 06 04:17:06 PM PDT 24 Jun 06 04:21:03 PM PDT 24 2641257168 ps
T980 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.367014796 Jun 06 04:25:37 PM PDT 24 Jun 06 04:35:38 PM PDT 24 4463975004 ps
T981 /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.2103379593 Jun 06 04:40:20 PM PDT 24 Jun 06 05:17:26 PM PDT 24 13551472496 ps
T982 /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.72021664 Jun 06 04:41:03 PM PDT 24 Jun 06 04:48:03 PM PDT 24 4113908432 ps
T71 /workspace/coverage/default/2.chip_tap_straps_testunlock0.3330833156 Jun 06 04:34:07 PM PDT 24 Jun 06 04:40:51 PM PDT 24 4369200077 ps
T8 /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.3190368786 Jun 06 04:25:20 PM PDT 24 Jun 06 04:32:47 PM PDT 24 4345324216 ps
T983 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2865120611 Jun 06 04:38:35 PM PDT 24 Jun 06 04:55:16 PM PDT 24 7930206425 ps
T984 /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.1019482235 Jun 06 04:12:13 PM PDT 24 Jun 06 04:32:13 PM PDT 24 5761206359 ps
T985 /workspace/coverage/default/0.chip_sw_otbn_smoketest.3662202809 Jun 06 04:16:57 PM PDT 24 Jun 06 04:44:35 PM PDT 24 7775451056 ps
T986 /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.1210248334 Jun 06 04:41:51 PM PDT 24 Jun 06 05:17:10 PM PDT 24 13634042320 ps
T987 /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.2059731461 Jun 06 04:21:33 PM PDT 24 Jun 06 04:41:28 PM PDT 24 5736442618 ps
T988 /workspace/coverage/default/0.chip_sival_flash_info_access.2904187945 Jun 06 04:09:54 PM PDT 24 Jun 06 04:14:18 PM PDT 24 2924553000 ps
T989 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.1273400217 Jun 06 04:12:30 PM PDT 24 Jun 06 04:38:56 PM PDT 24 7478883760 ps
T990 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.1067213311 Jun 06 04:18:35 PM PDT 24 Jun 06 05:20:54 PM PDT 24 14555547544 ps
T991 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.4010691576 Jun 06 04:23:18 PM PDT 24 Jun 06 04:35:17 PM PDT 24 4340403470 ps
T827 /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.2127799729 Jun 06 04:43:47 PM PDT 24 Jun 06 04:50:20 PM PDT 24 4016656904 ps
T183 /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.2000524094 Jun 06 04:18:53 PM PDT 24 Jun 06 05:35:47 PM PDT 24 43416837491 ps
T739 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.1147820141 Jun 06 04:29:47 PM PDT 24 Jun 06 04:35:42 PM PDT 24 3163549640 ps
T992 /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.3353123753 Jun 06 04:13:08 PM PDT 24 Jun 06 04:19:44 PM PDT 24 4814336784 ps
T810 /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.2781109960 Jun 06 04:42:57 PM PDT 24 Jun 06 04:49:19 PM PDT 24 4079128070 ps
T177 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.330189355 Jun 06 04:12:55 PM PDT 24 Jun 06 04:23:38 PM PDT 24 5059794893 ps
T769 /workspace/coverage/default/31.chip_sw_all_escalation_resets.3470756415 Jun 06 04:43:07 PM PDT 24 Jun 06 04:54:20 PM PDT 24 4350930508 ps
T274 /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.476459012 Jun 06 04:12:07 PM PDT 24 Jun 06 04:20:55 PM PDT 24 3213485500 ps
T346 /workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.2336970543 Jun 06 04:24:04 PM PDT 24 Jun 06 04:31:52 PM PDT 24 3780947516 ps
T993 /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.2950115396 Jun 06 04:17:02 PM PDT 24 Jun 06 04:37:03 PM PDT 24 7164084706 ps
T840 /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.2587642749 Jun 06 04:41:31 PM PDT 24 Jun 06 04:48:34 PM PDT 24 4117807000 ps
T463 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.1089657918 Jun 06 04:11:12 PM PDT 24 Jun 06 04:31:48 PM PDT 24 6488260660 ps
T994 /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.3007811768 Jun 06 04:37:45 PM PDT 24 Jun 06 04:48:33 PM PDT 24 4878611340 ps
T995 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.2928835360 Jun 06 04:08:41 PM PDT 24 Jun 06 04:18:46 PM PDT 24 8027472408 ps
T996 /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.669292526 Jun 06 04:34:49 PM PDT 24 Jun 06 04:39:52 PM PDT 24 2882533530 ps
T761 /workspace/coverage/default/0.rom_e2e_jtag_debug_rma.1780695171 Jun 06 04:19:58 PM PDT 24 Jun 06 05:00:49 PM PDT 24 13837904909 ps
T783 /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.1444477604 Jun 06 04:39:12 PM PDT 24 Jun 06 04:45:51 PM PDT 24 3370698800 ps
T997 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.1159298411 Jun 06 04:21:13 PM PDT 24 Jun 06 05:26:31 PM PDT 24 14488418350 ps
T820 /workspace/coverage/default/70.chip_sw_all_escalation_resets.3010175334 Jun 06 04:44:22 PM PDT 24 Jun 06 04:54:33 PM PDT 24 5298534100 ps
T998 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2804174124 Jun 06 04:34:55 PM PDT 24 Jun 06 04:47:44 PM PDT 24 5462721365 ps
T999 /workspace/coverage/default/0.rom_keymgr_functest.1943782265 Jun 06 04:15:24 PM PDT 24 Jun 06 04:26:37 PM PDT 24 3954750910 ps
T40 /workspace/coverage/default/1.chip_sw_gpio.164328239 Jun 06 04:20:33 PM PDT 24 Jun 06 04:28:31 PM PDT 24 3952894899 ps
T718 /workspace/coverage/default/0.rom_volatile_raw_unlock.2160606947 Jun 06 04:15:11 PM PDT 24 Jun 06 04:17:06 PM PDT 24 2663721711 ps
T361 /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1300134509 Jun 06 04:32:24 PM PDT 24 Jun 06 04:41:46 PM PDT 24 19234341720 ps
T1000 /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.2481076512 Jun 06 04:46:33 PM PDT 24 Jun 06 04:54:07 PM PDT 24 4126105010 ps
T1001 /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.3397419106 Jun 06 04:17:42 PM PDT 24 Jun 06 04:44:08 PM PDT 24 8395644980 ps
T767 /workspace/coverage/default/91.chip_sw_all_escalation_resets.281048252 Jun 06 04:46:43 PM PDT 24 Jun 06 04:55:11 PM PDT 24 4924303772 ps
T1002 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.3368444844 Jun 06 04:14:34 PM PDT 24 Jun 06 04:24:25 PM PDT 24 4670117840 ps
T824 /workspace/coverage/default/35.chip_sw_all_escalation_resets.2667831063 Jun 06 04:42:04 PM PDT 24 Jun 06 04:54:05 PM PDT 24 4985987080 ps
T287 /workspace/coverage/default/47.chip_sw_all_escalation_resets.3813338716 Jun 06 04:43:01 PM PDT 24 Jun 06 04:51:34 PM PDT 24 5159549000 ps
T832 /workspace/coverage/default/19.chip_sw_all_escalation_resets.755969674 Jun 06 04:43:38 PM PDT 24 Jun 06 04:55:35 PM PDT 24 5139062352 ps
T219 /workspace/coverage/default/0.chip_sw_inject_scramble_seed.1150286916 Jun 06 04:10:31 PM PDT 24 Jun 06 07:26:20 PM PDT 24 63029003353 ps
T1003 /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.2780645779 Jun 06 04:11:49 PM PDT 24 Jun 06 04:20:41 PM PDT 24 4224290364 ps
T818 /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.1442127723 Jun 06 04:42:03 PM PDT 24 Jun 06 04:48:25 PM PDT 24 3594816984 ps
T1004 /workspace/coverage/default/0.chip_sw_aes_enc.1978472904 Jun 06 04:11:35 PM PDT 24 Jun 06 04:14:43 PM PDT 24 2823475236 ps
T1005 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.2886708466 Jun 06 04:31:56 PM PDT 24 Jun 06 05:34:49 PM PDT 24 15912646740 ps
T1006 /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.2596621664 Jun 06 04:12:01 PM PDT 24 Jun 06 04:20:10 PM PDT 24 4531659744 ps
T801 /workspace/coverage/default/26.chip_sw_all_escalation_resets.1187731226 Jun 06 04:43:14 PM PDT 24 Jun 06 04:51:45 PM PDT 24 5887471240 ps
T1007 /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.2121829393 Jun 06 04:36:06 PM PDT 24 Jun 06 04:39:25 PM PDT 24 3506380870 ps
T1008 /workspace/coverage/default/0.chip_sw_example_flash.4199545489 Jun 06 04:10:00 PM PDT 24 Jun 06 04:14:43 PM PDT 24 2816480814 ps
T1009 /workspace/coverage/default/90.chip_sw_all_escalation_resets.1188145543 Jun 06 04:46:06 PM PDT 24 Jun 06 04:53:33 PM PDT 24 4433615816 ps
T316 /workspace/coverage/default/57.chip_sw_all_escalation_resets.2187670290 Jun 06 04:44:03 PM PDT 24 Jun 06 04:53:52 PM PDT 24 5275949608 ps
T771 /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.1828859719 Jun 06 04:42:11 PM PDT 24 Jun 06 04:49:29 PM PDT 24 3575489400 ps
T14 /workspace/coverage/default/1.chip_sw_sleep_pin_retention.614218675 Jun 06 04:16:34 PM PDT 24 Jun 06 04:21:12 PM PDT 24 3821513608 ps
T833 /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.803759873 Jun 06 04:40:56 PM PDT 24 Jun 06 04:46:12 PM PDT 24 4044243008 ps
T228 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.646105382 Jun 06 04:22:06 PM PDT 24 Jun 06 04:57:55 PM PDT 24 10133087800 ps
T384 /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.3350278039 Jun 06 04:31:54 PM PDT 24 Jun 06 04:45:07 PM PDT 24 7010821080 ps
T1010 /workspace/coverage/default/0.chip_sw_kmac_idle.1575427248 Jun 06 04:11:49 PM PDT 24 Jun 06 04:15:32 PM PDT 24 2894005908 ps
T93 /workspace/coverage/default/77.chip_sw_all_escalation_resets.3061884440 Jun 06 04:45:59 PM PDT 24 Jun 06 04:56:59 PM PDT 24 4774967322 ps
T178 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.818293939 Jun 06 04:32:37 PM PDT 24 Jun 06 04:44:44 PM PDT 24 5056018288 ps
T343 /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.1984371793 Jun 06 04:27:12 PM PDT 24 Jun 06 04:37:46 PM PDT 24 4207182612 ps
T765 /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.481707631 Jun 06 04:43:41 PM PDT 24 Jun 06 04:51:14 PM PDT 24 3520387040 ps
T1011 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3726618000 Jun 06 04:33:58 PM PDT 24 Jun 06 04:50:44 PM PDT 24 6907283526 ps
T1012 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.1979812844 Jun 06 04:18:31 PM PDT 24 Jun 06 04:32:27 PM PDT 24 9072367504 ps
T1013 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.977100847 Jun 06 04:33:26 PM PDT 24 Jun 06 04:42:57 PM PDT 24 6189210008 ps
T811 /workspace/coverage/default/55.chip_sw_all_escalation_resets.1220914171 Jun 06 04:46:33 PM PDT 24 Jun 06 04:56:17 PM PDT 24 5416063470 ps
T1014 /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.2203883002 Jun 06 04:17:50 PM PDT 24 Jun 06 04:36:13 PM PDT 24 5867554680 ps
T167 /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.3359664755 Jun 06 04:10:55 PM PDT 24 Jun 06 04:18:12 PM PDT 24 4810466368 ps
T1015 /workspace/coverage/default/1.chip_sw_inject_scramble_seed.3476670573 Jun 06 04:16:41 PM PDT 24 Jun 06 07:27:06 PM PDT 24 63789707677 ps
T1016 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.3600305656 Jun 06 04:18:28 PM PDT 24 Jun 06 05:42:12 PM PDT 24 21786389764 ps
T738 /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.4175959031 Jun 06 04:44:17 PM PDT 24 Jun 06 04:51:33 PM PDT 24 4485329714 ps
T843 /workspace/coverage/default/4.chip_sw_all_escalation_resets.319543974 Jun 06 04:39:19 PM PDT 24 Jun 06 04:51:34 PM PDT 24 5182789296 ps
T841 /workspace/coverage/default/67.chip_sw_all_escalation_resets.4205767432 Jun 06 04:48:28 PM PDT 24 Jun 06 04:58:48 PM PDT 24 6601806516 ps
T1017 /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.313488414 Jun 06 04:25:25 PM PDT 24 Jun 06 04:46:45 PM PDT 24 4978931912 ps
T238 /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.831715099 Jun 06 04:29:23 PM PDT 24 Jun 06 06:02:56 PM PDT 24 47951506088 ps
T369 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.4121588459 Jun 06 04:10:56 PM PDT 24 Jun 06 04:24:17 PM PDT 24 4551836422 ps
T1018 /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.4248226624 Jun 06 04:11:47 PM PDT 24 Jun 06 04:48:15 PM PDT 24 24738864812 ps
T1019 /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.3734030175 Jun 06 04:13:13 PM PDT 24 Jun 06 04:17:19 PM PDT 24 2472629504 ps
T53 /workspace/coverage/default/1.chip_sw_spi_device_tpm.3474868986 Jun 06 04:16:02 PM PDT 24 Jun 06 04:22:28 PM PDT 24 3558807600 ps
T1020 /workspace/coverage/default/0.rom_e2e_asm_init_dev.825576967 Jun 06 04:19:13 PM PDT 24 Jun 06 05:26:15 PM PDT 24 13599698832 ps
T825 /workspace/coverage/default/0.chip_sw_all_escalation_resets.4067482418 Jun 06 04:08:23 PM PDT 24 Jun 06 04:15:23 PM PDT 24 4609929500 ps
T1021 /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.2137089577 Jun 06 04:41:03 PM PDT 24 Jun 06 05:28:16 PM PDT 24 14028752584 ps
T1022 /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.589937027 Jun 06 04:27:18 PM PDT 24 Jun 06 04:32:36 PM PDT 24 2919535552 ps
T1023 /workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.3157761447 Jun 06 04:31:19 PM PDT 24 Jun 06 04:55:09 PM PDT 24 7929928714 ps
T72 /workspace/coverage/default/4.chip_tap_straps_rma.746640996 Jun 06 04:38:44 PM PDT 24 Jun 06 04:47:18 PM PDT 24 5690417500 ps
T1024 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.4230979430 Jun 06 04:22:05 PM PDT 24 Jun 06 04:27:41 PM PDT 24 2561762856 ps
T1025 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.471601767 Jun 06 04:22:59 PM PDT 24 Jun 06 04:34:47 PM PDT 24 8455570150 ps
T1026 /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.2984074689 Jun 06 04:12:15 PM PDT 24 Jun 06 04:30:48 PM PDT 24 5848749398 ps
T795 /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.223963597 Jun 06 04:41:14 PM PDT 24 Jun 06 04:47:05 PM PDT 24 3865894004 ps
T835 /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1044233730 Jun 06 04:45:29 PM PDT 24 Jun 06 04:51:27 PM PDT 24 4269007708 ps
T1027 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.3498427140 Jun 06 04:24:28 PM PDT 24 Jun 06 04:56:10 PM PDT 24 9232752056 ps
T1028 /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.1308146444 Jun 06 04:10:10 PM PDT 24 Jun 06 04:15:32 PM PDT 24 3173349340 ps
T464 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.69987844 Jun 06 04:21:36 PM PDT 24 Jun 06 04:41:20 PM PDT 24 5952717832 ps
T1029 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.1897408566 Jun 06 04:14:24 PM PDT 24 Jun 06 04:29:51 PM PDT 24 8597456980 ps
T1030 /workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.2404437520 Jun 06 04:40:39 PM PDT 24 Jun 06 05:28:22 PM PDT 24 11951456536 ps
T38 /workspace/coverage/default/0.chip_sw_usbdev_config_host.1750067650 Jun 06 04:10:06 PM PDT 24 Jun 06 04:42:26 PM PDT 24 8037409504 ps
T35 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.543003406 Jun 06 04:30:05 PM PDT 24 Jun 06 05:26:55 PM PDT 24 20310536681 ps
T1031 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.3560985246 Jun 06 04:40:11 PM PDT 24 Jun 06 05:34:07 PM PDT 24 15331372386 ps
T1032 /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.1843994311 Jun 06 04:32:02 PM PDT 24 Jun 06 04:39:45 PM PDT 24 3553713284 ps
T164 /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.327683869 Jun 06 04:28:50 PM PDT 24 Jun 06 04:33:42 PM PDT 24 2876963347 ps
T1033 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1516584485 Jun 06 04:17:06 PM PDT 24 Jun 06 05:06:21 PM PDT 24 23398763278 ps
T239 /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.736785350 Jun 06 04:17:20 PM PDT 24 Jun 06 05:48:22 PM PDT 24 48627346160 ps
T153 /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.3351522255 Jun 06 04:11:22 PM PDT 24 Jun 06 07:14:13 PM PDT 24 57911693574 ps
T1034 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.3835704804 Jun 06 04:22:35 PM PDT 24 Jun 06 05:08:47 PM PDT 24 12085305203 ps
T1035 /workspace/coverage/default/1.rom_e2e_asm_init_dev.230448506 Jun 06 04:29:41 PM PDT 24 Jun 06 05:41:43 PM PDT 24 14211306616 ps
T90 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.33666546 Jun 06 04:24:19 PM PDT 24 Jun 06 04:52:11 PM PDT 24 13705209920 ps
T465 /workspace/coverage/default/2.chip_sw_kmac_entropy.2115709224 Jun 06 04:27:22 PM PDT 24 Jun 06 04:31:37 PM PDT 24 3211380108 ps
T1036 /workspace/coverage/default/4.chip_tap_straps_dev.1582591030 Jun 06 04:42:06 PM PDT 24 Jun 06 04:45:19 PM PDT 24 3044934512 ps
T338 /workspace/coverage/default/0.chip_sw_entropy_src_csrng.3808462151 Jun 06 04:10:33 PM PDT 24 Jun 06 04:33:19 PM PDT 24 6131021484 ps
T776 /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.1480118804 Jun 06 04:45:35 PM PDT 24 Jun 06 04:51:51 PM PDT 24 3713603576 ps
T719 /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.553791640 Jun 06 04:15:37 PM PDT 24 Jun 06 04:17:49 PM PDT 24 3036036598 ps
T1037 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.638252803 Jun 06 04:12:56 PM PDT 24 Jun 06 04:18:15 PM PDT 24 2925089519 ps
T1038 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.4198702137 Jun 06 04:19:17 PM PDT 24 Jun 06 05:19:37 PM PDT 24 15076259328 ps
T230 /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.2073984071 Jun 06 04:32:17 PM PDT 24 Jun 06 05:02:25 PM PDT 24 10922759500 ps
T1039 /workspace/coverage/default/1.chip_sw_hmac_enc_idle.345324909 Jun 06 04:20:30 PM PDT 24 Jun 06 04:25:32 PM PDT 24 3391105748 ps
T212 /workspace/coverage/default/2.chip_sw_gpio_smoketest.621233032 Jun 06 04:36:33 PM PDT 24 Jun 06 04:42:10 PM PDT 24 3216662487 ps
T1040 /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.3944998639 Jun 06 04:30:30 PM PDT 24 Jun 06 05:19:37 PM PDT 24 11192566278 ps
T275 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.309387542 Jun 06 04:25:13 PM PDT 24 Jun 06 04:36:26 PM PDT 24 5041374444 ps
T261 /workspace/coverage/default/63.chip_sw_all_escalation_resets.1563697602 Jun 06 04:48:02 PM PDT 24 Jun 06 04:55:40 PM PDT 24 5219084422 ps
T181 /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.2165513092 Jun 06 04:35:10 PM PDT 24 Jun 06 04:41:26 PM PDT 24 2809790960 ps
T1041 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.3261087941 Jun 06 04:20:39 PM PDT 24 Jun 06 05:49:31 PM PDT 24 17661529940 ps
T1042 /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.1088258888 Jun 06 04:13:04 PM PDT 24 Jun 06 04:17:53 PM PDT 24 3446152234 ps
T39 /workspace/coverage/default/0.chip_sw_usbdev_dpi.2943896391 Jun 06 04:09:51 PM PDT 24 Jun 06 05:02:59 PM PDT 24 11813093180 ps
T1043 /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.4220762081 Jun 06 04:09:42 PM PDT 24 Jun 06 04:13:28 PM PDT 24 2255501840 ps
T1044 /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.259287864 Jun 06 04:38:23 PM PDT 24 Jun 06 04:45:19 PM PDT 24 5384901568 ps
T793 /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.2466851204 Jun 06 04:43:24 PM PDT 24 Jun 06 04:48:40 PM PDT 24 4431175940 ps
T1045 /workspace/coverage/default/0.chip_sw_kmac_smoketest.4263702691 Jun 06 04:15:30 PM PDT 24 Jun 06 04:20:39 PM PDT 24 2837393806 ps
T1046 /workspace/coverage/default/2.chip_sw_edn_kat.596061115 Jun 06 04:31:31 PM PDT 24 Jun 06 04:44:43 PM PDT 24 3137409810 ps
T1047 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.1024057526 Jun 06 04:10:10 PM PDT 24 Jun 06 04:18:51 PM PDT 24 4609754088 ps
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