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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.06 95.60 94.23 95.49 95.03 96.47 99.51


Total test records in report: 2881
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T1198 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.3204427090 Jun 06 04:13:54 PM PDT 24 Jun 06 04:35:58 PM PDT 24 7384544490 ps
T1199 /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.1624779210 Jun 06 04:27:50 PM PDT 24 Jun 06 04:49:49 PM PDT 24 10512004061 ps
T1200 /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.2803315089 Jun 06 04:40:32 PM PDT 24 Jun 06 04:47:36 PM PDT 24 5047071430 ps
T815 /workspace/coverage/default/40.chip_sw_all_escalation_resets.2409743596 Jun 06 04:42:37 PM PDT 24 Jun 06 04:55:05 PM PDT 24 6239383580 ps
T355 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.3761084612 Jun 06 04:10:35 PM PDT 24 Jun 06 04:26:19 PM PDT 24 5577364230 ps
T1201 /workspace/coverage/default/0.rom_e2e_asm_init_prod.2124136009 Jun 06 04:25:45 PM PDT 24 Jun 06 05:32:10 PM PDT 24 14320375450 ps
T1202 /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.2476042352 Jun 06 04:09:04 PM PDT 24 Jun 06 04:32:41 PM PDT 24 8406353720 ps
T1203 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.2952711487 Jun 06 04:09:59 PM PDT 24 Jun 06 04:20:22 PM PDT 24 4959075604 ps
T1204 /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.3766772357 Jun 06 04:30:08 PM PDT 24 Jun 06 04:46:59 PM PDT 24 5578510106 ps
T232 /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.4034116561 Jun 06 04:11:48 PM PDT 24 Jun 06 04:50:12 PM PDT 24 11546921732 ps
T471 /workspace/coverage/default/1.chip_sw_edn_boot_mode.2251176207 Jun 06 04:21:12 PM PDT 24 Jun 06 04:32:02 PM PDT 24 2954115408 ps
T1205 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3356971912 Jun 06 04:24:46 PM PDT 24 Jun 06 04:42:34 PM PDT 24 6750891646 ps
T1206 /workspace/coverage/default/2.chip_tap_straps_dev.1563968142 Jun 06 04:35:28 PM PDT 24 Jun 06 04:38:24 PM PDT 24 2687633813 ps
T1207 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1665488305 Jun 06 04:23:28 PM PDT 24 Jun 06 04:33:28 PM PDT 24 3406059250 ps
T1208 /workspace/coverage/default/3.chip_tap_straps_rma.1872747483 Jun 06 04:36:12 PM PDT 24 Jun 06 04:40:53 PM PDT 24 3899144910 ps
T233 /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.633560750 Jun 06 04:32:59 PM PDT 24 Jun 06 05:55:37 PM PDT 24 17271757500 ps
T1209 /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.3201531016 Jun 06 04:24:39 PM PDT 24 Jun 06 04:31:49 PM PDT 24 4122098960 ps
T788 /workspace/coverage/default/84.chip_sw_all_escalation_resets.911904531 Jun 06 04:46:16 PM PDT 24 Jun 06 04:53:49 PM PDT 24 4339128520 ps
T1210 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3294126998 Jun 06 04:18:28 PM PDT 24 Jun 06 04:38:00 PM PDT 24 11337891861 ps
T1211 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.4039301660 Jun 06 04:31:58 PM PDT 24 Jun 06 05:37:43 PM PDT 24 17580942296 ps
T1212 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.2624658228 Jun 06 04:19:57 PM PDT 24 Jun 06 04:43:00 PM PDT 24 9578395420 ps
T1213 /workspace/coverage/default/0.rom_e2e_smoke.289608121 Jun 06 04:20:15 PM PDT 24 Jun 06 05:28:11 PM PDT 24 14861741830 ps
T1214 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.829194768 Jun 06 04:11:15 PM PDT 24 Jun 06 04:22:41 PM PDT 24 3800737232 ps
T847 /workspace/coverage/default/83.chip_sw_all_escalation_resets.862219127 Jun 06 04:45:40 PM PDT 24 Jun 06 04:53:19 PM PDT 24 5614415960 ps
T1215 /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.2184897651 Jun 06 04:27:23 PM PDT 24 Jun 06 04:31:19 PM PDT 24 2674043574 ps
T291 /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.3969316551 Jun 06 04:46:11 PM PDT 24 Jun 06 04:52:39 PM PDT 24 4281697816 ps
T1216 /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3186703586 Jun 06 04:41:43 PM PDT 24 Jun 06 04:52:49 PM PDT 24 4309302712 ps
T1217 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2362940720 Jun 06 04:29:34 PM PDT 24 Jun 06 05:23:07 PM PDT 24 31270191640 ps
T1218 /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.2666264991 Jun 06 04:15:00 PM PDT 24 Jun 06 04:21:40 PM PDT 24 4113876936 ps
T1219 /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.1295798403 Jun 06 04:12:20 PM PDT 24 Jun 06 04:23:56 PM PDT 24 4607645400 ps
T1220 /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.1135885211 Jun 06 04:37:26 PM PDT 24 Jun 06 04:42:09 PM PDT 24 2660557148 ps
T1221 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.772100916 Jun 06 04:19:07 PM PDT 24 Jun 06 05:38:58 PM PDT 24 18032261394 ps
T1222 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.4137564548 Jun 06 04:14:15 PM PDT 24 Jun 06 04:37:57 PM PDT 24 10597057024 ps
T1223 /workspace/coverage/default/2.chip_sw_flash_init.2598004440 Jun 06 04:27:22 PM PDT 24 Jun 06 05:01:31 PM PDT 24 22933736429 ps
T1224 /workspace/coverage/default/2.chip_sw_kmac_idle.539565729 Jun 06 04:32:27 PM PDT 24 Jun 06 04:37:52 PM PDT 24 3481556504 ps
T1225 /workspace/coverage/default/0.chip_sw_hmac_enc.2514884526 Jun 06 04:11:59 PM PDT 24 Jun 06 04:16:31 PM PDT 24 2882207432 ps
T1226 /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.683996707 Jun 06 04:26:51 PM PDT 24 Jun 06 04:32:14 PM PDT 24 3003970316 ps
T1227 /workspace/coverage/default/1.chip_sw_kmac_smoketest.4184503985 Jun 06 04:28:34 PM PDT 24 Jun 06 04:34:13 PM PDT 24 3420159796 ps
T1228 /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.1926805083 Jun 06 04:14:33 PM PDT 24 Jun 06 04:18:50 PM PDT 24 3301935768 ps
T1229 /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.1117293046 Jun 06 04:17:42 PM PDT 24 Jun 06 04:23:48 PM PDT 24 3376095920 ps
T768 /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.1836685472 Jun 06 04:37:58 PM PDT 24 Jun 06 04:45:21 PM PDT 24 3511685928 ps
T1230 /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.695999843 Jun 06 04:12:15 PM PDT 24 Jun 06 04:20:44 PM PDT 24 4743769302 ps
T1231 /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.3424599091 Jun 06 04:33:07 PM PDT 24 Jun 06 04:43:49 PM PDT 24 9577167629 ps
T1232 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.3245964195 Jun 06 04:38:26 PM PDT 24 Jun 06 04:51:53 PM PDT 24 4817201724 ps
T1233 /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.3032847711 Jun 06 04:37:43 PM PDT 24 Jun 06 04:46:17 PM PDT 24 4369372638 ps
T1234 /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.1761744341 Jun 06 04:15:58 PM PDT 24 Jun 06 04:41:23 PM PDT 24 9624701968 ps
T1235 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.637850924 Jun 06 04:13:06 PM PDT 24 Jun 06 04:23:41 PM PDT 24 4418792340 ps
T1236 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.1654329938 Jun 06 04:19:56 PM PDT 24 Jun 06 05:17:39 PM PDT 24 14491384704 ps
T1237 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1175143324 Jun 06 04:28:29 PM PDT 24 Jun 06 04:34:22 PM PDT 24 6212260512 ps
T1238 /workspace/coverage/default/78.chip_sw_all_escalation_resets.3684886582 Jun 06 04:45:28 PM PDT 24 Jun 06 04:55:59 PM PDT 24 5966639000 ps
T184 /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.2462065032 Jun 06 04:27:17 PM PDT 24 Jun 06 06:13:41 PM PDT 24 44234502581 ps
T842 /workspace/coverage/default/85.chip_sw_all_escalation_resets.3390677512 Jun 06 04:45:21 PM PDT 24 Jun 06 04:56:51 PM PDT 24 5270453864 ps
T1239 /workspace/coverage/default/4.chip_tap_straps_testunlock0.3617484219 Jun 06 04:38:02 PM PDT 24 Jun 06 04:51:44 PM PDT 24 8264194663 ps
T1240 /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.978453027 Jun 06 04:15:46 PM PDT 24 Jun 06 04:22:03 PM PDT 24 3614415920 ps
T1241 /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.916391686 Jun 06 04:32:33 PM PDT 24 Jun 06 04:40:23 PM PDT 24 4467277000 ps
T809 /workspace/coverage/default/59.chip_sw_all_escalation_resets.2839832438 Jun 06 04:44:47 PM PDT 24 Jun 06 04:55:05 PM PDT 24 5620901916 ps
T245 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.3976029410 Jun 06 04:17:37 PM PDT 24 Jun 06 05:41:50 PM PDT 24 48977214580 ps
T190 /workspace/coverage/default/1.chip_sw_spi_device_pass_through.902092194 Jun 06 04:18:34 PM PDT 24 Jun 06 04:29:40 PM PDT 24 6232542022 ps
T813 /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.2550880019 Jun 06 04:42:13 PM PDT 24 Jun 06 04:50:23 PM PDT 24 4299497206 ps
T1242 /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.980466819 Jun 06 04:39:52 PM PDT 24 Jun 06 05:18:25 PM PDT 24 10401824704 ps
T1243 /workspace/coverage/default/2.rom_keymgr_functest.3392619572 Jun 06 04:41:03 PM PDT 24 Jun 06 04:48:48 PM PDT 24 4891979460 ps
T725 /workspace/coverage/default/64.chip_sw_all_escalation_resets.1046534783 Jun 06 04:43:46 PM PDT 24 Jun 06 04:52:59 PM PDT 24 5788485004 ps
T1244 /workspace/coverage/default/1.chip_sw_example_concurrency.492504053 Jun 06 04:18:58 PM PDT 24 Jun 06 04:22:58 PM PDT 24 2844115216 ps
T1245 /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.3671589518 Jun 06 04:39:25 PM PDT 24 Jun 06 05:16:04 PM PDT 24 13202860056 ps
T806 /workspace/coverage/default/96.chip_sw_all_escalation_resets.2928433507 Jun 06 04:46:23 PM PDT 24 Jun 06 04:58:09 PM PDT 24 5613294252 ps
T1246 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.4190411558 Jun 06 04:11:01 PM PDT 24 Jun 06 04:40:20 PM PDT 24 7613434632 ps
T1247 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.2535626428 Jun 06 04:28:43 PM PDT 24 Jun 06 04:39:37 PM PDT 24 4485585600 ps
T1248 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.2644493265 Jun 06 04:30:49 PM PDT 24 Jun 06 05:25:07 PM PDT 24 16833027706 ps
T1249 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.4136229228 Jun 06 04:20:42 PM PDT 24 Jun 06 05:53:10 PM PDT 24 21719715269 ps
T327 /workspace/coverage/default/1.chip_plic_all_irqs_0.2444763694 Jun 06 04:22:53 PM PDT 24 Jun 06 04:39:37 PM PDT 24 5985460842 ps
T1250 /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.128525947 Jun 06 04:20:02 PM PDT 24 Jun 06 04:30:26 PM PDT 24 4545022526 ps
T1251 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.1907790495 Jun 06 04:09:09 PM PDT 24 Jun 06 04:21:17 PM PDT 24 4411676304 ps
T1252 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.1853060694 Jun 06 04:20:41 PM PDT 24 Jun 06 05:15:30 PM PDT 24 14071469960 ps
T1253 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.813509319 Jun 06 04:19:51 PM PDT 24 Jun 06 05:46:28 PM PDT 24 22374806460 ps
T1254 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.14000307 Jun 06 04:19:51 PM PDT 24 Jun 06 05:21:48 PM PDT 24 12944615632 ps
T264 /workspace/coverage/default/9.chip_sw_all_escalation_resets.4011954603 Jun 06 04:39:33 PM PDT 24 Jun 06 04:52:12 PM PDT 24 5980420700 ps
T393 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.719116637 Jun 06 04:16:55 PM PDT 24 Jun 06 04:30:51 PM PDT 24 4937812968 ps
T1255 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.455221926 Jun 06 04:28:59 PM PDT 24 Jun 06 04:56:32 PM PDT 24 7417377100 ps
T1256 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.3248724495 Jun 06 04:20:27 PM PDT 24 Jun 06 05:20:06 PM PDT 24 15553062548 ps
T1257 /workspace/coverage/default/2.chip_sw_hmac_oneshot.1067202238 Jun 06 04:31:54 PM PDT 24 Jun 06 04:37:53 PM PDT 24 2366994456 ps
T1258 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3682480192 Jun 06 04:24:49 PM PDT 24 Jun 06 05:13:02 PM PDT 24 32724705627 ps
T1259 /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.4161874329 Jun 06 04:40:36 PM PDT 24 Jun 06 05:18:42 PM PDT 24 13489867944 ps
T243 /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.346525450 Jun 06 04:24:30 PM PDT 24 Jun 06 04:58:14 PM PDT 24 22369075163 ps
T1260 /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.190101668 Jun 06 04:40:23 PM PDT 24 Jun 06 04:51:39 PM PDT 24 10350184960 ps
T1261 /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3097798781 Jun 06 04:30:56 PM PDT 24 Jun 06 08:11:39 PM PDT 24 254064824430 ps
T1262 /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.3010322371 Jun 06 04:48:19 PM PDT 24 Jun 06 04:53:53 PM PDT 24 3392739912 ps
T26 /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.221830919 Jun 06 04:20:39 PM PDT 24 Jun 06 04:25:58 PM PDT 24 3767057243 ps
T1263 /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.2727085063 Jun 06 04:31:05 PM PDT 24 Jun 06 05:23:36 PM PDT 24 13764066740 ps
T1264 /workspace/coverage/default/0.chip_tap_straps_prod.3603694482 Jun 06 04:12:05 PM PDT 24 Jun 06 04:14:31 PM PDT 24 2662008710 ps
T773 /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.3105901865 Jun 06 04:43:25 PM PDT 24 Jun 06 04:48:04 PM PDT 24 4173785456 ps
T1265 /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2731185956 Jun 06 04:44:19 PM PDT 24 Jun 06 04:50:44 PM PDT 24 3506576460 ps
T1266 /workspace/coverage/default/2.chip_sw_aon_timer_irq.3334305063 Jun 06 04:30:10 PM PDT 24 Jun 06 04:38:45 PM PDT 24 4147913504 ps
T1267 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.662342696 Jun 06 04:33:48 PM PDT 24 Jun 06 04:37:40 PM PDT 24 2981919786 ps
T1268 /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.1782234274 Jun 06 04:27:57 PM PDT 24 Jun 06 04:39:55 PM PDT 24 4479325952 ps
T356 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.14782496 Jun 06 04:17:06 PM PDT 24 Jun 06 04:31:42 PM PDT 24 5646504178 ps
T310 /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1567126697 Jun 06 04:34:19 PM PDT 24 Jun 06 04:45:53 PM PDT 24 4881490992 ps
T1269 /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.3351569691 Jun 06 04:18:05 PM PDT 24 Jun 06 04:24:45 PM PDT 24 6032448264 ps
T1270 /workspace/coverage/default/2.chip_sw_clkmgr_jitter.2235521852 Jun 06 04:33:34 PM PDT 24 Jun 06 04:37:45 PM PDT 24 2324114775 ps
T1271 /workspace/coverage/default/87.chip_sw_all_escalation_resets.3258048134 Jun 06 04:46:16 PM PDT 24 Jun 06 04:56:29 PM PDT 24 5903823188 ps
T1272 /workspace/coverage/default/1.chip_sw_hmac_enc.3525524155 Jun 06 04:22:11 PM PDT 24 Jun 06 04:26:10 PM PDT 24 2808787326 ps
T822 /workspace/coverage/default/16.chip_sw_all_escalation_resets.3102943854 Jun 06 04:41:30 PM PDT 24 Jun 06 04:51:29 PM PDT 24 5734008146 ps
T206 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.3233083785 Jun 06 04:29:07 PM PDT 24 Jun 06 04:33:00 PM PDT 24 2738510728 ps
T1273 /workspace/coverage/default/3.chip_sw_data_integrity_escalation.3453607520 Jun 06 04:37:08 PM PDT 24 Jun 06 04:50:27 PM PDT 24 5432199750 ps
T1274 /workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.4170813749 Jun 06 04:26:39 PM PDT 24 Jun 06 04:32:48 PM PDT 24 3526358020 ps
T1275 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.1130075671 Jun 06 04:19:20 PM PDT 24 Jun 06 04:47:41 PM PDT 24 7974857234 ps
T1276 /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.967846561 Jun 06 04:37:43 PM PDT 24 Jun 06 04:42:26 PM PDT 24 3040197480 ps
T821 /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.2009046234 Jun 06 04:40:32 PM PDT 24 Jun 06 04:48:14 PM PDT 24 4284609120 ps
T1277 /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.1995688514 Jun 06 04:18:24 PM PDT 24 Jun 06 04:57:05 PM PDT 24 25178099614 ps
T1278 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1913864484 Jun 06 04:14:24 PM PDT 24 Jun 06 04:26:53 PM PDT 24 4652453984 ps
T1279 /workspace/coverage/default/0.chip_sw_plic_sw_irq.1926136314 Jun 06 04:13:56 PM PDT 24 Jun 06 04:18:03 PM PDT 24 3335377644 ps
T380 /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2872633120 Jun 06 04:15:25 PM PDT 24 Jun 06 04:23:09 PM PDT 24 6099553088 ps
T1280 /workspace/coverage/default/1.chip_sw_uart_smoketest.2710289692 Jun 06 04:28:24 PM PDT 24 Jun 06 04:33:20 PM PDT 24 3361694612 ps
T304 /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.3344039640 Jun 06 04:22:16 PM PDT 24 Jun 06 04:36:16 PM PDT 24 7091421176 ps
T1281 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.3856846358 Jun 06 04:21:09 PM PDT 24 Jun 06 04:32:05 PM PDT 24 4262012312 ps
T18 /workspace/coverage/default/1.chip_sw_sleep_pin_wake.3962278389 Jun 06 04:15:13 PM PDT 24 Jun 06 04:19:31 PM PDT 24 3180540448 ps
T430 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.2572854955 Jun 06 04:28:12 PM PDT 24 Jun 06 04:45:29 PM PDT 24 6032173976 ps
T292 /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.1497575936 Jun 06 04:12:49 PM PDT 24 Jun 06 04:17:07 PM PDT 24 2887990300 ps
T331 /workspace/coverage/default/1.chip_plic_all_irqs_20.3441942882 Jun 06 04:23:58 PM PDT 24 Jun 06 04:37:38 PM PDT 24 4682286910 ps
T116 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.1091510971 Jun 06 04:30:07 PM PDT 24 Jun 06 05:16:04 PM PDT 24 17877678916 ps
T344 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.3033901631 Jun 06 04:16:25 PM PDT 24 Jun 06 04:30:25 PM PDT 24 4724316892 ps
T431 /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.547629045 Jun 06 04:30:41 PM PDT 24 Jun 06 04:48:00 PM PDT 24 5406332792 ps
T432 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2324245496 Jun 06 04:35:12 PM PDT 24 Jun 06 04:44:58 PM PDT 24 6066805884 ps
T433 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.1412626358 Jun 06 04:12:49 PM PDT 24 Jun 06 04:16:39 PM PDT 24 3178163544 ps
T434 /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.1544104205 Jun 06 04:15:46 PM PDT 24 Jun 06 04:23:11 PM PDT 24 6295720840 ps
T1282 /workspace/coverage/default/4.chip_sw_uart_tx_rx.3042991040 Jun 06 04:38:12 PM PDT 24 Jun 06 04:51:34 PM PDT 24 4212580760 ps
T117 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.688861814 Jun 06 04:36:04 PM PDT 24 Jun 06 06:34:57 PM PDT 24 48597753115 ps
T1283 /workspace/coverage/default/0.chip_sw_ast_clk_outputs.3276173355 Jun 06 04:11:29 PM PDT 24 Jun 06 04:30:36 PM PDT 24 8306665500 ps
T49 /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.2939119573 Jun 06 04:10:10 PM PDT 24 Jun 06 04:14:58 PM PDT 24 3116683912 ps
T1284 /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.351919927 Jun 06 04:39:42 PM PDT 24 Jun 06 05:08:43 PM PDT 24 8450345306 ps
T1285 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2119903063 Jun 06 04:31:11 PM PDT 24 Jun 06 05:01:50 PM PDT 24 27652926583 ps
T265 /workspace/coverage/default/86.chip_sw_all_escalation_resets.1330168396 Jun 06 04:45:34 PM PDT 24 Jun 06 04:53:38 PM PDT 24 5671990520 ps
T1286 /workspace/coverage/default/0.chip_sw_kmac_entropy.3167650542 Jun 06 04:10:09 PM PDT 24 Jun 06 04:13:31 PM PDT 24 2634558548 ps
T1287 /workspace/coverage/default/1.chip_sw_aes_enc.4080598905 Jun 06 04:20:30 PM PDT 24 Jun 06 04:25:29 PM PDT 24 3127591632 ps
T1288 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.3927247541 Jun 06 04:30:39 PM PDT 24 Jun 06 04:58:08 PM PDT 24 6577869984 ps
T803 /workspace/coverage/default/68.chip_sw_all_escalation_resets.1401790990 Jun 06 04:49:13 PM PDT 24 Jun 06 04:59:43 PM PDT 24 5573147080 ps
T759 /workspace/coverage/default/2.chip_sw_pattgen_ios.2386729967 Jun 06 04:27:44 PM PDT 24 Jun 06 04:31:22 PM PDT 24 2623103452 ps
T1289 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.464570257 Jun 06 04:10:11 PM PDT 24 Jun 06 04:22:27 PM PDT 24 3980046540 ps
T1290 /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.3830072488 Jun 06 04:42:29 PM PDT 24 Jun 06 04:51:19 PM PDT 24 3782393896 ps
T1291 /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.3068872721 Jun 06 04:32:26 PM PDT 24 Jun 06 04:41:25 PM PDT 24 4103830600 ps
T95 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.573505192 Jun 06 04:31:27 PM PDT 24 Jun 06 04:38:41 PM PDT 24 3600859032 ps
T1292 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2119614697 Jun 06 04:12:55 PM PDT 24 Jun 06 04:24:13 PM PDT 24 4955916552 ps
T1293 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.2888792886 Jun 06 04:28:25 PM PDT 24 Jun 06 04:47:26 PM PDT 24 8160967854 ps
T1294 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.2952726002 Jun 06 04:11:13 PM PDT 24 Jun 06 05:53:52 PM PDT 24 46590711518 ps
T1295 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3721297072 Jun 06 04:13:38 PM PDT 24 Jun 06 04:22:45 PM PDT 24 5521245739 ps
T137 /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.1303076810 Jun 06 04:36:48 PM PDT 24 Jun 06 04:46:23 PM PDT 24 5896672640 ps
T1296 /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.3530828933 Jun 06 04:30:37 PM PDT 24 Jun 06 04:41:17 PM PDT 24 5154144012 ps
T266 /workspace/coverage/default/36.chip_sw_all_escalation_resets.4193123225 Jun 06 04:46:51 PM PDT 24 Jun 06 04:57:32 PM PDT 24 5884364892 ps
T317 /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1566856429 Jun 06 04:48:43 PM PDT 24 Jun 06 04:55:18 PM PDT 24 3390818250 ps
T1297 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.2330938976 Jun 06 04:16:11 PM PDT 24 Jun 06 04:34:54 PM PDT 24 6154842118 ps
T1298 /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.672811741 Jun 06 04:22:48 PM PDT 24 Jun 06 04:36:32 PM PDT 24 6167843360 ps
T1299 /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.1982158779 Jun 06 04:41:33 PM PDT 24 Jun 06 04:49:54 PM PDT 24 3735841554 ps
T1300 /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.4197395201 Jun 06 04:25:22 PM PDT 24 Jun 06 04:32:19 PM PDT 24 4371547386 ps
T1301 /workspace/coverage/default/2.rom_volatile_raw_unlock.2076341816 Jun 06 04:35:53 PM PDT 24 Jun 06 04:37:40 PM PDT 24 2351305614 ps
T12 /workspace/coverage/default/0.chip_jtag_csr_rw.4195996628 Jun 06 04:03:59 PM PDT 24 Jun 06 04:50:47 PM PDT 24 23022845643 ps
T415 /workspace/coverage/default/0.chip_sw_hmac_oneshot.2920235206 Jun 06 04:12:29 PM PDT 24 Jun 06 04:17:27 PM PDT 24 2969466040 ps
T416 /workspace/coverage/default/3.chip_tap_straps_dev.2072296142 Jun 06 04:36:29 PM PDT 24 Jun 06 04:39:01 PM PDT 24 2424117704 ps
T417 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.305071888 Jun 06 04:17:02 PM PDT 24 Jun 06 04:41:59 PM PDT 24 9004811346 ps
T267 /workspace/coverage/default/61.chip_sw_all_escalation_resets.946810966 Jun 06 04:44:14 PM PDT 24 Jun 06 04:52:28 PM PDT 24 4692038220 ps
T418 /workspace/coverage/default/0.chip_sw_example_concurrency.3543355676 Jun 06 04:08:54 PM PDT 24 Jun 06 04:12:45 PM PDT 24 2466036264 ps
T139 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1901003467 Jun 06 04:26:35 PM PDT 24 Jun 06 04:34:07 PM PDT 24 5193189356 ps
T381 /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.344946363 Jun 06 04:33:00 PM PDT 24 Jun 06 04:38:22 PM PDT 24 4455692064 ps
T419 /workspace/coverage/default/2.chip_sw_csrng_smoketest.2754291898 Jun 06 04:35:17 PM PDT 24 Jun 06 04:40:52 PM PDT 24 2783101200 ps
T420 /workspace/coverage/default/0.chip_sw_aon_timer_irq.617413520 Jun 06 04:12:17 PM PDT 24 Jun 06 04:19:56 PM PDT 24 3928541660 ps
T96 /workspace/coverage/default/27.chip_sw_all_escalation_resets.2542758893 Jun 06 04:41:35 PM PDT 24 Jun 06 04:52:08 PM PDT 24 5838852500 ps
T1302 /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.3725742521 Jun 06 04:19:35 PM PDT 24 Jun 06 04:25:34 PM PDT 24 4384364846 ps
T1303 /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.1085326124 Jun 06 04:11:58 PM PDT 24 Jun 06 04:20:20 PM PDT 24 4858018718 ps
T1304 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1729373478 Jun 06 04:10:28 PM PDT 24 Jun 06 05:02:09 PM PDT 24 31569330770 ps
T1305 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2577158975 Jun 06 04:25:31 PM PDT 24 Jun 06 05:24:54 PM PDT 24 25575759805 ps
T837 /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.2647254300 Jun 06 04:40:08 PM PDT 24 Jun 06 04:46:35 PM PDT 24 3536493674 ps
T293 /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.3084409217 Jun 06 04:24:47 PM PDT 24 Jun 06 04:30:27 PM PDT 24 3118590600 ps
T713 /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.2610199199 Jun 06 04:34:30 PM PDT 24 Jun 06 04:42:04 PM PDT 24 4088432864 ps
T1306 /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.780144341 Jun 06 04:23:25 PM PDT 24 Jun 06 04:50:20 PM PDT 24 10884306992 ps
T714 /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.2172686644 Jun 06 04:14:23 PM PDT 24 Jun 06 04:28:25 PM PDT 24 5630639281 ps
T1307 /workspace/coverage/default/0.chip_tap_straps_testunlock0.2365994429 Jun 06 04:11:44 PM PDT 24 Jun 06 04:23:32 PM PDT 24 7475553166 ps
T1308 /workspace/coverage/default/2.chip_sw_uart_tx_rx.2659824828 Jun 06 04:28:01 PM PDT 24 Jun 06 04:43:00 PM PDT 24 4548733176 ps
T1309 /workspace/coverage/default/0.chip_sw_kmac_app_rom.3856215792 Jun 06 04:13:47 PM PDT 24 Jun 06 04:17:13 PM PDT 24 3392772454 ps
T1310 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.2763419605 Jun 06 04:21:03 PM PDT 24 Jun 06 04:48:52 PM PDT 24 7131480824 ps
T1311 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.2123242842 Jun 06 04:33:21 PM PDT 24 Jun 06 04:36:56 PM PDT 24 2719511471 ps
T1312 /workspace/coverage/default/0.chip_sw_hmac_enc_idle.2870048559 Jun 06 04:13:23 PM PDT 24 Jun 06 04:17:43 PM PDT 24 3138555098 ps
T1313 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.119634439 Jun 06 04:21:50 PM PDT 24 Jun 06 05:47:42 PM PDT 24 22681423704 ps
T1314 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.3754445984 Jun 06 04:18:33 PM PDT 24 Jun 06 04:25:43 PM PDT 24 6099539940 ps
T1315 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.1771636330 Jun 06 04:15:13 PM PDT 24 Jun 06 04:35:13 PM PDT 24 5516077417 ps
T67 /workspace/coverage/default/2.chip_sw_alert_test.3224866951 Jun 06 04:31:17 PM PDT 24 Jun 06 04:36:43 PM PDT 24 2640376016 ps
T1316 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3021334166 Jun 06 04:33:56 PM PDT 24 Jun 06 04:51:51 PM PDT 24 8707427253 ps
T138 /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.3075932375 Jun 06 04:25:31 PM PDT 24 Jun 06 04:40:30 PM PDT 24 9494048240 ps
T1317 /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.2822162004 Jun 06 04:14:34 PM PDT 24 Jun 06 04:19:36 PM PDT 24 2603580316 ps
T55 /workspace/coverage/default/0.chip_sw_spi_device_tpm.256172283 Jun 06 04:10:11 PM PDT 24 Jun 06 04:16:44 PM PDT 24 4302323393 ps
T1318 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.2131486794 Jun 06 04:12:43 PM PDT 24 Jun 06 04:18:08 PM PDT 24 3542634217 ps
T1319 /workspace/coverage/default/0.chip_tap_straps_dev.143532661 Jun 06 04:11:17 PM PDT 24 Jun 06 04:13:49 PM PDT 24 2440236659 ps
T1320 /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.3726674849 Jun 06 04:12:30 PM PDT 24 Jun 06 04:19:35 PM PDT 24 4015600400 ps
T1321 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.2234860686 Jun 06 04:14:40 PM PDT 24 Jun 06 04:35:25 PM PDT 24 6386341308 ps
T244 /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.3336562907 Jun 06 04:34:39 PM PDT 24 Jun 06 05:06:10 PM PDT 24 24831276125 ps
T1322 /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.1976073288 Jun 06 04:26:25 PM PDT 24 Jun 06 04:30:24 PM PDT 24 2654300114 ps
T1323 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.2550816928 Jun 06 04:22:08 PM PDT 24 Jun 06 04:42:40 PM PDT 24 6442440110 ps
T1324 /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.3054275564 Jun 06 04:16:29 PM PDT 24 Jun 06 04:21:24 PM PDT 24 2981091752 ps
T234 /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.874632234 Jun 06 04:10:59 PM PDT 24 Jun 06 05:00:45 PM PDT 24 10009789000 ps
T1325 /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.2187972767 Jun 06 04:25:50 PM PDT 24 Jun 06 04:34:58 PM PDT 24 5622265024 ps
T796 /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.2931152622 Jun 06 04:43:08 PM PDT 24 Jun 06 04:52:00 PM PDT 24 3138450190 ps
T1326 /workspace/coverage/default/2.rom_e2e_smoke.250692690 Jun 06 04:40:18 PM PDT 24 Jun 06 05:28:31 PM PDT 24 14832894228 ps
T774 /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3847160162 Jun 06 04:44:10 PM PDT 24 Jun 06 04:51:13 PM PDT 24 4177291588 ps
T328 /workspace/coverage/default/0.chip_plic_all_irqs_0.3790755892 Jun 06 04:12:32 PM PDT 24 Jun 06 04:33:41 PM PDT 24 5823094440 ps
T1327 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.684763995 Jun 06 04:11:07 PM PDT 24 Jun 06 05:09:06 PM PDT 24 16976552956 ps
T1328 /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.2094217240 Jun 06 04:36:45 PM PDT 24 Jun 06 04:43:52 PM PDT 24 3684225912 ps
T337 /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.3604096985 Jun 06 04:30:19 PM PDT 24 Jun 06 04:54:38 PM PDT 24 11713802200 ps
T1329 /workspace/coverage/default/1.chip_sw_power_idle_load.725444005 Jun 06 04:29:46 PM PDT 24 Jun 06 04:42:03 PM PDT 24 4511473526 ps
T1330 /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.1520397751 Jun 06 04:37:05 PM PDT 24 Jun 06 04:43:30 PM PDT 24 2972629672 ps
T52 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1911306063 Jun 06 04:10:21 PM PDT 24 Jun 06 04:18:26 PM PDT 24 6297113470 ps
T1331 /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.825098459 Jun 06 04:40:39 PM PDT 24 Jun 06 04:48:56 PM PDT 24 5305149600 ps
T831 /workspace/coverage/default/15.chip_sw_all_escalation_resets.2357499294 Jun 06 04:41:05 PM PDT 24 Jun 06 04:50:50 PM PDT 24 5013812432 ps
T1332 /workspace/coverage/default/2.chip_sw_inject_scramble_seed.2878018790 Jun 06 04:27:52 PM PDT 24 Jun 06 07:35:54 PM PDT 24 64870771125 ps
T1333 /workspace/coverage/default/1.chip_sw_otbn_randomness.3036745529 Jun 06 04:18:37 PM PDT 24 Jun 06 04:32:37 PM PDT 24 5794136700 ps
T1334 /workspace/coverage/default/0.rom_e2e_shutdown_output.4051111440 Jun 06 04:19:43 PM PDT 24 Jun 06 05:13:48 PM PDT 24 24150593432 ps
T772 /workspace/coverage/default/69.chip_sw_all_escalation_resets.2546937634 Jun 06 04:47:33 PM PDT 24 Jun 06 04:57:29 PM PDT 24 5582681796 ps
T1335 /workspace/coverage/default/1.rom_keymgr_functest.3127127823 Jun 06 04:29:06 PM PDT 24 Jun 06 04:38:05 PM PDT 24 4681639340 ps
T1336 /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.522066963 Jun 06 04:10:39 PM PDT 24 Jun 06 04:29:44 PM PDT 24 11981304378 ps
T1337 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2690311264 Jun 06 04:37:07 PM PDT 24 Jun 06 04:52:46 PM PDT 24 8177754922 ps
T1338 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.2147669878 Jun 06 04:18:38 PM PDT 24 Jun 06 05:02:21 PM PDT 24 10596908276 ps
T1339 /workspace/coverage/default/1.chip_sw_example_rom.1531909713 Jun 06 04:15:25 PM PDT 24 Jun 06 04:17:40 PM PDT 24 2272144778 ps
T1340 /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.3608670417 Jun 06 04:16:16 PM PDT 24 Jun 06 04:20:38 PM PDT 24 3518719732 ps
T294 /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.863342188 Jun 06 04:36:32 PM PDT 24 Jun 06 04:40:54 PM PDT 24 3204448735 ps
T1341 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1415105384 Jun 06 04:31:01 PM PDT 24 Jun 06 04:55:24 PM PDT 24 12829429080 ps
T1342 /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.3337166655 Jun 06 04:45:09 PM PDT 24 Jun 06 04:52:00 PM PDT 24 3779726244 ps
T1343 /workspace/coverage/default/3.chip_tap_straps_prod.2551878929 Jun 06 04:38:03 PM PDT 24 Jun 06 04:54:46 PM PDT 24 10219005413 ps
T1344 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.1974915016 Jun 06 04:22:08 PM PDT 24 Jun 06 04:49:17 PM PDT 24 7717918344 ps
T1345 /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.2330062117 Jun 06 04:17:05 PM PDT 24 Jun 06 04:21:27 PM PDT 24 2961373840 ps
T1346 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.3158238591 Jun 06 04:18:48 PM PDT 24 Jun 06 05:11:29 PM PDT 24 20568483709 ps
T1347 /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.4003707337 Jun 06 04:19:39 PM PDT 24 Jun 06 04:27:29 PM PDT 24 4172838499 ps
T1348 /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.2630168724 Jun 06 04:37:09 PM PDT 24 Jun 06 05:15:48 PM PDT 24 13595708420 ps
T1349 /workspace/coverage/default/2.chip_sw_aes_entropy.2505226782 Jun 06 04:31:31 PM PDT 24 Jun 06 04:37:33 PM PDT 24 3217225844 ps
T1350 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.3791559399 Jun 06 04:11:30 PM PDT 24 Jun 06 04:22:29 PM PDT 24 4740691332 ps
T1351 /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.1935316560 Jun 06 04:43:07 PM PDT 24 Jun 06 04:52:17 PM PDT 24 3358798040 ps
T80 /workspace/coverage/cover_reg_top/92.xbar_random_zero_delays.3914137607 Jun 06 04:00:23 PM PDT 24 Jun 06 04:01:14 PM PDT 24 587605275 ps
T81 /workspace/coverage/cover_reg_top/89.xbar_smoke_zero_delays.2021100867 Jun 06 03:59:44 PM PDT 24 Jun 06 03:59:52 PM PDT 24 42536379 ps
T82 /workspace/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.1939843432 Jun 06 03:55:29 PM PDT 24 Jun 06 03:55:51 PM PDT 24 466440058 ps
T86 /workspace/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.2151491827 Jun 06 03:43:48 PM PDT 24 Jun 06 03:44:30 PM PDT 24 1132850647 ps
T252 /workspace/coverage/cover_reg_top/41.xbar_smoke_large_delays.3897323131 Jun 06 03:50:43 PM PDT 24 Jun 06 03:51:50 PM PDT 24 6262623866 ps
T253 /workspace/coverage/cover_reg_top/48.xbar_error_random.89492867 Jun 06 03:52:14 PM PDT 24 Jun 06 03:52:27 PM PDT 24 107918927 ps
T472 /workspace/coverage/cover_reg_top/75.xbar_random_slow_rsp.2428223765 Jun 06 03:57:13 PM PDT 24 Jun 06 04:14:50 PM PDT 24 51493849663 ps
T559 /workspace/coverage/cover_reg_top/65.xbar_stress_all.515999151 Jun 06 03:55:40 PM PDT 24 Jun 06 03:57:31 PM PDT 24 2675464398 ps
T473 /workspace/coverage/cover_reg_top/4.xbar_random_slow_rsp.1572114399 Jun 06 03:40:29 PM PDT 24 Jun 06 03:46:39 PM PDT 24 21321153047 ps
T561 /workspace/coverage/cover_reg_top/92.xbar_same_source.2840466679 Jun 06 04:00:32 PM PDT 24 Jun 06 04:00:46 PM PDT 24 143559163 ps
T564 /workspace/coverage/cover_reg_top/62.xbar_random_zero_delays.102454089 Jun 06 03:54:58 PM PDT 24 Jun 06 03:55:13 PM PDT 24 97568703 ps
T575 /workspace/coverage/cover_reg_top/26.xbar_smoke_large_delays.2137644499 Jun 06 03:47:03 PM PDT 24 Jun 06 03:48:08 PM PDT 24 5588974360 ps
T562 /workspace/coverage/cover_reg_top/59.xbar_error_random.1053436409 Jun 06 03:54:34 PM PDT 24 Jun 06 03:55:45 PM PDT 24 2417393467 ps
T578 /workspace/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.1360704901 Jun 06 03:59:50 PM PDT 24 Jun 06 04:01:30 PM PDT 24 5696319293 ps
T563 /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_error.983480408 Jun 06 03:50:55 PM PDT 24 Jun 06 03:54:07 PM PDT 24 5100450455 ps
T573 /workspace/coverage/cover_reg_top/75.xbar_same_source.226812210 Jun 06 03:57:15 PM PDT 24 Jun 06 03:57:29 PM PDT 24 133098349 ps
T565 /workspace/coverage/cover_reg_top/43.xbar_random.3393508204 Jun 06 03:51:17 PM PDT 24 Jun 06 03:52:15 PM PDT 24 1574451456 ps
T576 /workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.2470216084 Jun 06 03:43:24 PM PDT 24 Jun 06 03:44:57 PM PDT 24 8435764807 ps
T486 /workspace/coverage/cover_reg_top/99.xbar_same_source.2722038366 Jun 06 04:01:32 PM PDT 24 Jun 06 04:01:55 PM PDT 24 285672057 ps
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