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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.06 95.60 94.23 95.49 95.03 96.47 99.51


Total test records in report: 2881
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T336 /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.1836185593 Jun 06 04:17:05 PM PDT 24 Jun 06 04:50:12 PM PDT 24 13967127478 ps
T240 /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.2916022601 Jun 06 04:29:20 PM PDT 24 Jun 06 05:50:14 PM PDT 24 47469583784 ps
T349 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.2349711137 Jun 06 04:28:41 PM PDT 24 Jun 06 04:43:17 PM PDT 24 4256250934 ps
T1048 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.3513852591 Jun 06 04:23:24 PM PDT 24 Jun 06 05:31:19 PM PDT 24 14474653768 ps
T808 /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.364538236 Jun 06 04:44:53 PM PDT 24 Jun 06 04:51:26 PM PDT 24 3727614032 ps
T288 /workspace/coverage/default/98.chip_sw_all_escalation_resets.2129448688 Jun 06 04:47:56 PM PDT 24 Jun 06 04:58:05 PM PDT 24 5830752440 ps
T1049 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.2564293259 Jun 06 04:19:25 PM PDT 24 Jun 06 05:11:52 PM PDT 24 13850137096 ps
T782 /workspace/coverage/default/79.chip_sw_all_escalation_resets.166471003 Jun 06 04:46:30 PM PDT 24 Jun 06 04:55:50 PM PDT 24 5688555304 ps
T276 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.1999656931 Jun 06 04:32:22 PM PDT 24 Jun 06 04:45:46 PM PDT 24 5783000750 ps
T1050 /workspace/coverage/default/2.chip_sw_hmac_multistream.4123957499 Jun 06 04:31:56 PM PDT 24 Jun 06 04:57:04 PM PDT 24 7425687064 ps
T1051 /workspace/coverage/default/0.chip_sw_flash_crash_alert.3957063261 Jun 06 04:13:28 PM PDT 24 Jun 06 04:23:54 PM PDT 24 4442466216 ps
T347 /workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.3632521144 Jun 06 04:35:21 PM PDT 24 Jun 06 04:43:37 PM PDT 24 4137338800 ps
T1052 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3664293033 Jun 06 04:28:15 PM PDT 24 Jun 06 04:39:11 PM PDT 24 4738583988 ps
T335 /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.4213345011 Jun 06 04:18:12 PM PDT 24 Jun 06 04:50:20 PM PDT 24 10749103630 ps
T1053 /workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.2476132562 Jun 06 04:11:00 PM PDT 24 Jun 06 04:16:16 PM PDT 24 3227434330 ps
T1054 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.3285224491 Jun 06 04:20:39 PM PDT 24 Jun 06 05:13:42 PM PDT 24 10460573498 ps
T830 /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.3418892565 Jun 06 04:47:40 PM PDT 24 Jun 06 04:53:47 PM PDT 24 3354507000 ps
T797 /workspace/coverage/default/18.chip_sw_all_escalation_resets.109649741 Jun 06 04:40:00 PM PDT 24 Jun 06 04:47:31 PM PDT 24 4217147238 ps
T1055 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.444307719 Jun 06 04:30:08 PM PDT 24 Jun 06 04:44:41 PM PDT 24 8517121030 ps
T720 /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.2734310870 Jun 06 04:10:56 PM PDT 24 Jun 06 04:15:14 PM PDT 24 3312991131 ps
T1056 /workspace/coverage/default/2.chip_sw_rv_timer_irq.1835278278 Jun 06 04:30:46 PM PDT 24 Jun 06 04:36:21 PM PDT 24 3509559676 ps
T1057 /workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.2164560852 Jun 06 04:20:03 PM PDT 24 Jun 06 04:46:37 PM PDT 24 8327117728 ps
T790 /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.3434577524 Jun 06 04:43:16 PM PDT 24 Jun 06 04:49:43 PM PDT 24 3615738360 ps
T1058 /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.225112662 Jun 06 04:39:37 PM PDT 24 Jun 06 05:35:46 PM PDT 24 11260216219 ps
T800 /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.733977205 Jun 06 04:41:42 PM PDT 24 Jun 06 04:48:42 PM PDT 24 3187676876 ps
T1059 /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.991995919 Jun 06 04:20:45 PM PDT 24 Jun 06 04:29:04 PM PDT 24 5185317512 ps
T844 /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.2933880783 Jun 06 04:41:31 PM PDT 24 Jun 06 04:50:42 PM PDT 24 4226203784 ps
T1060 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.1268694886 Jun 06 04:41:25 PM PDT 24 Jun 06 05:33:25 PM PDT 24 14338174920 ps
T1061 /workspace/coverage/default/0.chip_sw_aes_entropy.697708953 Jun 06 04:11:11 PM PDT 24 Jun 06 04:15:58 PM PDT 24 2894046936 ps
T1062 /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.429149837 Jun 06 04:24:21 PM PDT 24 Jun 06 04:33:20 PM PDT 24 3121683848 ps
T556 /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.859353464 Jun 06 04:10:56 PM PDT 24 Jun 06 04:26:32 PM PDT 24 4583695170 ps
T289 /workspace/coverage/default/17.chip_sw_all_escalation_resets.590616375 Jun 06 04:40:06 PM PDT 24 Jun 06 04:52:42 PM PDT 24 6607557780 ps
T255 /workspace/coverage/default/2.chip_sw_plic_sw_irq.1995728349 Jun 06 04:32:38 PM PDT 24 Jun 06 04:36:25 PM PDT 24 2795124750 ps
T1063 /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.2049469267 Jun 06 04:40:25 PM PDT 24 Jun 06 05:20:29 PM PDT 24 13489533862 ps
T1064 /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1855750181 Jun 06 04:40:29 PM PDT 24 Jun 06 04:52:18 PM PDT 24 10951136192 ps
T198 /workspace/coverage/default/2.chip_jtag_csr_rw.1671474320 Jun 06 04:25:50 PM PDT 24 Jun 06 04:59:53 PM PDT 24 19149865352 ps
T816 /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.1521484081 Jun 06 04:44:43 PM PDT 24 Jun 06 04:51:58 PM PDT 24 4134777066 ps
T1065 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.621040712 Jun 06 04:31:46 PM PDT 24 Jun 06 04:52:20 PM PDT 24 7787615346 ps
T819 /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.1914647428 Jun 06 04:41:33 PM PDT 24 Jun 06 04:47:23 PM PDT 24 3329940184 ps
T1066 /workspace/coverage/default/1.chip_sw_kmac_entropy.1673981412 Jun 06 04:16:15 PM PDT 24 Jun 06 04:21:46 PM PDT 24 3229778770 ps
T156 /workspace/coverage/default/0.chip_plic_all_irqs_10.1013438172 Jun 06 04:13:02 PM PDT 24 Jun 06 04:23:16 PM PDT 24 4394233362 ps
T1067 /workspace/coverage/default/0.chip_tap_straps_rma.2075813564 Jun 06 04:13:27 PM PDT 24 Jun 06 04:18:48 PM PDT 24 4346952219 ps
T200 /workspace/coverage/default/0.chip_sw_usbdev_vbus.1840907595 Jun 06 04:10:06 PM PDT 24 Jun 06 04:13:15 PM PDT 24 2726555584 ps
T1068 /workspace/coverage/default/1.chip_sw_aes_masking_off.276037577 Jun 06 04:18:51 PM PDT 24 Jun 06 04:23:04 PM PDT 24 2460215046 ps
T1069 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.631062828 Jun 06 04:12:31 PM PDT 24 Jun 06 04:23:16 PM PDT 24 4882096952 ps
T1070 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.1626914559 Jun 06 04:11:59 PM PDT 24 Jun 06 04:20:31 PM PDT 24 3932832152 ps
T165 /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.970974774 Jun 06 04:17:27 PM PDT 24 Jun 06 04:21:49 PM PDT 24 2250900356 ps
T1071 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.970276612 Jun 06 04:33:31 PM PDT 24 Jun 06 04:46:20 PM PDT 24 3833631256 ps
T51 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3015440055 Jun 06 04:22:50 PM PDT 24 Jun 06 04:34:45 PM PDT 24 5945592716 ps
T1072 /workspace/coverage/default/0.chip_sw_example_manufacturer.1036114792 Jun 06 04:09:48 PM PDT 24 Jun 06 04:12:30 PM PDT 24 2288364280 ps
T1073 /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.1690014423 Jun 06 04:10:53 PM PDT 24 Jun 06 04:17:25 PM PDT 24 4212525886 ps
T1074 /workspace/coverage/default/4.chip_tap_straps_prod.4236305563 Jun 06 04:39:13 PM PDT 24 Jun 06 04:41:41 PM PDT 24 2455081157 ps
T453 /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.590697227 Jun 06 04:14:50 PM PDT 24 Jun 06 04:21:11 PM PDT 24 9865617292 ps
T1075 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.142635381 Jun 06 04:13:07 PM PDT 24 Jun 06 04:24:48 PM PDT 24 11109383359 ps
T770 /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.79377542 Jun 06 04:46:08 PM PDT 24 Jun 06 04:52:49 PM PDT 24 3473211104 ps
T330 /workspace/coverage/default/2.chip_plic_all_irqs_20.1101177437 Jun 06 04:32:31 PM PDT 24 Jun 06 04:46:28 PM PDT 24 4929464336 ps
T203 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.1758158070 Jun 06 04:19:16 PM PDT 24 Jun 06 04:30:06 PM PDT 24 5274520779 ps
T1076 /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.2446898630 Jun 06 04:40:37 PM PDT 24 Jun 06 04:54:32 PM PDT 24 10112376303 ps
T1077 /workspace/coverage/default/1.rom_e2e_asm_init_prod.2946761427 Jun 06 04:39:12 PM PDT 24 Jun 06 05:25:48 PM PDT 24 14426703176 ps
T1078 /workspace/coverage/default/2.chip_sw_aes_masking_off.2539432248 Jun 06 04:31:07 PM PDT 24 Jun 06 04:35:19 PM PDT 24 2461809530 ps
T41 /workspace/coverage/default/2.chip_sw_gpio.3534531329 Jun 06 04:28:34 PM PDT 24 Jun 06 04:37:17 PM PDT 24 3651962920 ps
T277 /workspace/coverage/default/5.chip_sw_data_integrity_escalation.3956513808 Jun 06 04:38:29 PM PDT 24 Jun 06 04:51:36 PM PDT 24 5332885142 ps
T1079 /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.1172395835 Jun 06 04:35:41 PM PDT 24 Jun 06 04:39:43 PM PDT 24 2366467500 ps
T79 /workspace/coverage/default/0.chip_sw_usbdev_pincfg.2153108465 Jun 06 04:10:23 PM PDT 24 Jun 06 06:08:31 PM PDT 24 32113201320 ps
T1080 /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.3101585659 Jun 06 04:36:46 PM PDT 24 Jun 06 04:41:29 PM PDT 24 2832034056 ps
T777 /workspace/coverage/default/66.chip_sw_all_escalation_resets.2139070532 Jun 06 04:47:48 PM PDT 24 Jun 06 04:55:09 PM PDT 24 4655752932 ps
T9 /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.3216232646 Jun 06 04:12:52 PM PDT 24 Jun 06 04:17:36 PM PDT 24 3856094344 ps
T1081 /workspace/coverage/default/48.chip_sw_all_escalation_resets.3002239502 Jun 06 04:45:20 PM PDT 24 Jun 06 04:55:54 PM PDT 24 5475199422 ps
T794 /workspace/coverage/default/34.chip_sw_all_escalation_resets.2410203157 Jun 06 04:41:12 PM PDT 24 Jun 06 04:50:34 PM PDT 24 5171308672 ps
T1082 /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.3694465979 Jun 06 04:35:39 PM PDT 24 Jun 06 04:43:08 PM PDT 24 6068157028 ps
T1083 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.2130004880 Jun 06 04:27:51 PM PDT 24 Jun 06 04:41:07 PM PDT 24 4194671982 ps
T1084 /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.1226002116 Jun 06 04:24:48 PM PDT 24 Jun 06 04:34:42 PM PDT 24 4819535288 ps
T1085 /workspace/coverage/default/0.chip_sw_example_rom.3759135879 Jun 06 04:07:58 PM PDT 24 Jun 06 04:10:05 PM PDT 24 2676091512 ps
T1086 /workspace/coverage/default/1.chip_sw_power_sleep_load.2426942154 Jun 06 04:24:54 PM PDT 24 Jun 06 04:39:29 PM PDT 24 10738501416 ps
T1087 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.1192116991 Jun 06 04:22:41 PM PDT 24 Jun 06 04:35:28 PM PDT 24 7412900594 ps
T1088 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.3621874115 Jun 06 04:23:52 PM PDT 24 Jun 06 04:32:05 PM PDT 24 6399183026 ps
T1089 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.3529001312 Jun 06 04:12:30 PM PDT 24 Jun 06 04:49:42 PM PDT 24 9289138014 ps
T1090 /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.3576695549 Jun 06 04:18:53 PM PDT 24 Jun 06 04:23:47 PM PDT 24 3422690946 ps
T350 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.1422532436 Jun 06 04:19:16 PM PDT 24 Jun 06 04:31:36 PM PDT 24 4035312882 ps
T1091 /workspace/coverage/default/2.chip_sw_edn_sw_mode.879215050 Jun 06 04:32:11 PM PDT 24 Jun 06 04:57:13 PM PDT 24 7668222944 ps
T804 /workspace/coverage/default/32.chip_sw_all_escalation_resets.1558509976 Jun 06 04:41:37 PM PDT 24 Jun 06 04:53:09 PM PDT 24 4528499782 ps
T798 /workspace/coverage/default/29.chip_sw_all_escalation_resets.482954237 Jun 06 04:41:43 PM PDT 24 Jun 06 04:50:04 PM PDT 24 4917725576 ps
T1092 /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.653322172 Jun 06 04:32:44 PM PDT 24 Jun 06 04:53:56 PM PDT 24 7553888408 ps
T1093 /workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.1633875962 Jun 06 04:10:11 PM PDT 24 Jun 06 05:38:04 PM PDT 24 27327736386 ps
T1094 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.3069318830 Jun 06 04:32:44 PM PDT 24 Jun 06 05:07:10 PM PDT 24 11912170494 ps
T838 /workspace/coverage/default/62.chip_sw_all_escalation_resets.2889963883 Jun 06 04:44:08 PM PDT 24 Jun 06 04:56:37 PM PDT 24 5015749870 ps
T1095 /workspace/coverage/default/0.chip_sw_csrng_smoketest.178694455 Jun 06 04:16:28 PM PDT 24 Jun 06 04:20:35 PM PDT 24 2689682900 ps
T1096 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.1688397532 Jun 06 04:18:53 PM PDT 24 Jun 06 05:20:13 PM PDT 24 14430498990 ps
T339 /workspace/coverage/default/1.chip_sw_entropy_src_csrng.2732560503 Jun 06 04:24:11 PM PDT 24 Jun 06 04:45:34 PM PDT 24 6473359534 ps
T1097 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.2124709630 Jun 06 04:37:38 PM PDT 24 Jun 06 04:48:00 PM PDT 24 4873051384 ps
T1098 /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.2868494486 Jun 06 04:14:43 PM PDT 24 Jun 06 04:24:47 PM PDT 24 5868200572 ps
T1099 /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.4118600590 Jun 06 04:40:16 PM PDT 24 Jun 06 05:29:03 PM PDT 24 14786217492 ps
T1100 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.863824101 Jun 06 04:31:37 PM PDT 24 Jun 06 05:29:50 PM PDT 24 18559261812 ps
T388 /workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.3050142014 Jun 06 04:34:16 PM PDT 24 Jun 06 04:37:58 PM PDT 24 2833342390 ps
T106 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.538650211 Jun 06 04:33:53 PM PDT 24 Jun 06 04:40:06 PM PDT 24 7110924300 ps
T1101 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.366320378 Jun 06 04:16:29 PM PDT 24 Jun 06 04:18:32 PM PDT 24 2346218638 ps
T1102 /workspace/coverage/default/2.chip_sw_hmac_enc_idle.3212823715 Jun 06 04:31:52 PM PDT 24 Jun 06 04:37:03 PM PDT 24 2508282368 ps
T1103 /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.1058804544 Jun 06 04:35:20 PM PDT 24 Jun 06 04:39:26 PM PDT 24 2386349898 ps
T812 /workspace/coverage/default/58.chip_sw_all_escalation_resets.3423256567 Jun 06 04:44:20 PM PDT 24 Jun 06 04:53:20 PM PDT 24 5809654816 ps
T1104 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2011993744 Jun 06 04:36:54 PM PDT 24 Jun 06 04:50:51 PM PDT 24 4746472916 ps
T36 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.1880768986 Jun 06 04:30:29 PM PDT 24 Jun 06 04:56:10 PM PDT 24 25467766232 ps
T823 /workspace/coverage/default/2.chip_sw_all_escalation_resets.1705830299 Jun 06 04:27:20 PM PDT 24 Jun 06 04:38:18 PM PDT 24 5542389346 ps
T242 /workspace/coverage/default/0.chip_sw_flash_init.3608738163 Jun 06 04:11:28 PM PDT 24 Jun 06 04:47:52 PM PDT 24 23083032940 ps
T1105 /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.612206180 Jun 06 04:38:00 PM PDT 24 Jun 06 04:44:17 PM PDT 24 6249340700 ps
T1106 /workspace/coverage/default/2.chip_sw_edn_auto_mode.3362772948 Jun 06 04:31:25 PM PDT 24 Jun 06 04:47:20 PM PDT 24 4544592076 ps
T357 /workspace/coverage/default/0.chip_sw_pattgen_ios.186526416 Jun 06 04:10:04 PM PDT 24 Jun 06 04:15:32 PM PDT 24 3137228988 ps
T1107 /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.1078841033 Jun 06 04:21:59 PM PDT 24 Jun 06 04:50:14 PM PDT 24 7739280368 ps
T199 /workspace/coverage/default/2.chip_jtag_mem_access.1394151084 Jun 06 04:25:43 PM PDT 24 Jun 06 04:54:15 PM PDT 24 13561265368 ps
T1108 /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.3545661394 Jun 06 04:33:13 PM PDT 24 Jun 06 04:43:11 PM PDT 24 5224482100 ps
T846 /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3643652300 Jun 06 04:47:05 PM PDT 24 Jun 06 04:54:14 PM PDT 24 3795096938 ps
T1109 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.1693782894 Jun 06 04:18:43 PM PDT 24 Jun 06 05:28:04 PM PDT 24 13688532250 ps
T1110 /workspace/coverage/default/1.chip_sw_alert_handler_entropy.2233767072 Jun 06 04:20:15 PM PDT 24 Jun 06 04:25:49 PM PDT 24 3843107198 ps
T1111 /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.3371079157 Jun 06 04:29:15 PM PDT 24 Jun 06 04:39:55 PM PDT 24 5090563658 ps
T54 /workspace/coverage/default/2.chip_sw_spi_device_tpm.4009084079 Jun 06 04:27:23 PM PDT 24 Jun 06 04:34:31 PM PDT 24 3679263836 ps
T1112 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.941585033 Jun 06 04:09:47 PM PDT 24 Jun 06 04:17:07 PM PDT 24 7574842816 ps
T1113 /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.1482586435 Jun 06 04:21:12 PM PDT 24 Jun 06 04:24:58 PM PDT 24 2858644650 ps
T290 /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.1434035615 Jun 06 04:43:45 PM PDT 24 Jun 06 04:49:45 PM PDT 24 3837511990 ps
T1114 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.3467188879 Jun 06 04:17:49 PM PDT 24 Jun 06 04:29:49 PM PDT 24 6954452104 ps
T146 /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.2110868886 Jun 06 04:16:54 PM PDT 24 Jun 06 04:23:22 PM PDT 24 7089432424 ps
T1115 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.566669588 Jun 06 04:14:20 PM PDT 24 Jun 06 04:19:01 PM PDT 24 3424700887 ps
T1116 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2629648544 Jun 06 04:27:09 PM PDT 24 Jun 06 04:53:39 PM PDT 24 12949962552 ps
T1117 /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.2927703372 Jun 06 04:11:20 PM PDT 24 Jun 06 04:20:57 PM PDT 24 5322142000 ps
T1118 /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.388416286 Jun 06 04:45:50 PM PDT 24 Jun 06 04:51:37 PM PDT 24 3895855476 ps
T764 /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.3420721338 Jun 06 04:45:10 PM PDT 24 Jun 06 04:51:43 PM PDT 24 4276232496 ps
T1119 /workspace/coverage/default/1.rom_volatile_raw_unlock.3262604314 Jun 06 04:38:02 PM PDT 24 Jun 06 04:39:50 PM PDT 24 2644619062 ps
T1120 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.1417255980 Jun 06 04:37:38 PM PDT 24 Jun 06 04:48:33 PM PDT 24 4216956224 ps
T182 /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.2313226 Jun 06 04:24:02 PM PDT 24 Jun 06 04:28:17 PM PDT 24 3188480362 ps
T1121 /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1407917904 Jun 06 04:46:46 PM PDT 24 Jun 06 04:52:57 PM PDT 24 3421802350 ps
T1122 /workspace/coverage/default/41.chip_sw_all_escalation_resets.2873696720 Jun 06 04:45:04 PM PDT 24 Jun 06 04:54:32 PM PDT 24 4994858008 ps
T1123 /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.2195464122 Jun 06 04:24:27 PM PDT 24 Jun 06 04:32:39 PM PDT 24 4982339880 ps
T42 /workspace/coverage/default/0.chip_sw_gpio.3664380026 Jun 06 04:11:21 PM PDT 24 Jun 06 04:21:27 PM PDT 24 4123628200 ps
T1124 /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.1943912723 Jun 06 04:45:04 PM PDT 24 Jun 06 04:49:56 PM PDT 24 3756101574 ps
T834 /workspace/coverage/default/73.chip_sw_all_escalation_resets.1459928103 Jun 06 04:45:01 PM PDT 24 Jun 06 04:55:21 PM PDT 24 4354580184 ps
T1125 /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.2421712605 Jun 06 04:15:08 PM PDT 24 Jun 06 04:24:42 PM PDT 24 4559438694 ps
T1126 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.896266734 Jun 06 04:31:52 PM PDT 24 Jun 06 04:48:57 PM PDT 24 9074945770 ps
T466 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.2548949651 Jun 06 04:32:43 PM PDT 24 Jun 06 04:52:15 PM PDT 24 6843874750 ps
T402 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2732350873 Jun 06 04:11:48 PM PDT 24 Jun 06 04:37:11 PM PDT 24 26341752328 ps
T1127 /workspace/coverage/default/1.chip_tap_straps_testunlock0.406402947 Jun 06 04:23:21 PM PDT 24 Jun 06 04:28:01 PM PDT 24 3313380351 ps
T1128 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.691396779 Jun 06 04:24:40 PM PDT 24 Jun 06 04:28:32 PM PDT 24 3238293092 ps
T775 /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.4218852493 Jun 06 04:45:02 PM PDT 24 Jun 06 04:52:36 PM PDT 24 4285356440 ps
T1129 /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.1840022380 Jun 06 04:38:26 PM PDT 24 Jun 06 05:05:18 PM PDT 24 8890758644 ps
T1130 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.2777857219 Jun 06 04:13:25 PM PDT 24 Jun 06 04:21:12 PM PDT 24 3684712000 ps
T1131 /workspace/coverage/default/0.chip_sw_uart_tx_rx.4225252071 Jun 06 04:09:48 PM PDT 24 Jun 06 04:21:47 PM PDT 24 4872894060 ps
T367 /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3752462222 Jun 06 04:10:32 PM PDT 24 Jun 06 04:21:13 PM PDT 24 19985661558 ps
T1132 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.3702913893 Jun 06 04:33:34 PM PDT 24 Jun 06 04:39:45 PM PDT 24 5109686416 ps
T187 /workspace/coverage/default/0.chip_sw_spi_device_pass_through.2612032325 Jun 06 04:10:16 PM PDT 24 Jun 06 04:28:18 PM PDT 24 8622583864 ps
T1133 /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.3334214957 Jun 06 04:28:24 PM PDT 24 Jun 06 04:47:48 PM PDT 24 6624193930 ps
T1134 /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.2947736246 Jun 06 04:43:26 PM PDT 24 Jun 06 04:50:18 PM PDT 24 3846371316 ps
T805 /workspace/coverage/default/65.chip_sw_all_escalation_resets.472848410 Jun 06 04:44:49 PM PDT 24 Jun 06 04:51:36 PM PDT 24 5717849224 ps
T1135 /workspace/coverage/default/2.chip_sw_hmac_smoketest.237823406 Jun 06 04:35:40 PM PDT 24 Jun 06 04:41:39 PM PDT 24 3004828740 ps
T1136 /workspace/coverage/default/2.chip_sw_otbn_smoketest.212415200 Jun 06 04:37:38 PM PDT 24 Jun 06 05:01:50 PM PDT 24 7738905144 ps
T1137 /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.1034934538 Jun 06 04:37:45 PM PDT 24 Jun 06 04:43:43 PM PDT 24 6114166771 ps
T204 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.249057075 Jun 06 04:19:02 PM PDT 24 Jun 06 04:24:35 PM PDT 24 2865193797 ps
T1138 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.1055471106 Jun 06 04:23:25 PM PDT 24 Jun 06 05:25:29 PM PDT 24 14331506786 ps
T1139 /workspace/coverage/default/1.chip_sw_rv_timer_irq.102493765 Jun 06 04:24:45 PM PDT 24 Jun 06 04:30:00 PM PDT 24 3663220744 ps
T1140 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.714846652 Jun 06 04:19:13 PM PDT 24 Jun 06 04:24:58 PM PDT 24 3584186600 ps
T1141 /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.2363226294 Jun 06 04:29:19 PM PDT 24 Jun 06 04:36:52 PM PDT 24 8136663744 ps
T1142 /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.340248379 Jun 06 04:44:27 PM PDT 24 Jun 06 04:50:37 PM PDT 24 3577689576 ps
T1143 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.623609363 Jun 06 04:24:40 PM PDT 24 Jun 06 04:35:44 PM PDT 24 4775490912 ps
T1144 /workspace/coverage/default/1.chip_sw_aon_timer_irq.637932541 Jun 06 04:18:36 PM PDT 24 Jun 06 04:25:46 PM PDT 24 3429020860 ps
T136 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2996143911 Jun 06 04:14:40 PM PDT 24 Jun 06 04:22:01 PM PDT 24 5313830060 ps
T1145 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.904154355 Jun 06 04:18:19 PM PDT 24 Jun 06 04:26:39 PM PDT 24 5509616712 ps
T1146 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3066172032 Jun 06 04:11:41 PM PDT 24 Jun 06 04:42:28 PM PDT 24 16454352052 ps
T1147 /workspace/coverage/default/1.rom_e2e_shutdown_output.3426412162 Jun 06 04:38:04 PM PDT 24 Jun 06 05:19:51 PM PDT 24 22447246968 ps
T1148 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.643119831 Jun 06 04:11:02 PM PDT 24 Jun 06 04:16:21 PM PDT 24 3341131496 ps
T1149 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.3759561932 Jun 06 04:24:20 PM PDT 24 Jun 06 04:29:02 PM PDT 24 2156788371 ps
T1150 /workspace/coverage/default/0.chip_sw_aes_idle.1469039731 Jun 06 04:11:02 PM PDT 24 Jun 06 04:14:55 PM PDT 24 2813174720 ps
T1151 /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.4043256571 Jun 06 04:18:18 PM PDT 24 Jun 06 05:03:01 PM PDT 24 10384618378 ps
T94 /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.2607722734 Jun 06 04:45:24 PM PDT 24 Jun 06 04:50:59 PM PDT 24 3947874396 ps
T262 /workspace/coverage/default/76.chip_sw_all_escalation_resets.2779059250 Jun 06 04:45:21 PM PDT 24 Jun 06 04:55:25 PM PDT 24 5102871436 ps
T817 /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1709017834 Jun 06 04:40:27 PM PDT 24 Jun 06 04:49:40 PM PDT 24 4280233392 ps
T1152 /workspace/coverage/default/0.chip_sw_csrng_kat_test.1738149160 Jun 06 04:11:40 PM PDT 24 Jun 06 04:15:42 PM PDT 24 3156122230 ps
T188 /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.522677369 Jun 06 04:15:16 PM PDT 24 Jun 06 04:25:12 PM PDT 24 4143599445 ps
T748 /workspace/coverage/default/2.chip_sw_power_sleep_load.2084433640 Jun 06 04:34:22 PM PDT 24 Jun 06 04:41:18 PM PDT 24 5061635144 ps
T789 /workspace/coverage/default/44.chip_sw_all_escalation_resets.2580602854 Jun 06 04:43:34 PM PDT 24 Jun 06 04:52:15 PM PDT 24 5169689300 ps
T1153 /workspace/coverage/default/33.chip_sw_all_escalation_resets.595992261 Jun 06 04:46:57 PM PDT 24 Jun 06 04:56:44 PM PDT 24 4910089538 ps
T1154 /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.3024233185 Jun 06 04:38:04 PM PDT 24 Jun 06 05:04:08 PM PDT 24 7936984824 ps
T1155 /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.504043583 Jun 06 04:10:51 PM PDT 24 Jun 06 04:46:19 PM PDT 24 8956055844 ps
T17 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3544378506 Jun 06 04:14:34 PM PDT 24 Jun 06 04:47:53 PM PDT 24 24363630356 ps
T1156 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1215924778 Jun 06 04:19:39 PM PDT 24 Jun 06 04:21:26 PM PDT 24 2477944608 ps
T1157 /workspace/coverage/default/54.chip_sw_all_escalation_resets.2163471990 Jun 06 04:43:57 PM PDT 24 Jun 06 04:56:06 PM PDT 24 5967019172 ps
T1158 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.3542002826 Jun 06 04:33:25 PM PDT 24 Jun 06 04:56:14 PM PDT 24 6501079729 ps
T231 /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.444259986 Jun 06 04:25:27 PM PDT 24 Jun 06 04:45:09 PM PDT 24 5824845254 ps
T1159 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.207118898 Jun 06 04:12:30 PM PDT 24 Jun 06 04:22:12 PM PDT 24 7475385088 ps
T791 /workspace/coverage/default/53.chip_sw_all_escalation_resets.2639962247 Jun 06 04:43:46 PM PDT 24 Jun 06 04:52:02 PM PDT 24 5075725744 ps
T1160 /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.2219467340 Jun 06 04:34:16 PM PDT 24 Jun 06 04:43:12 PM PDT 24 4117666140 ps
T724 /workspace/coverage/default/46.chip_sw_all_escalation_resets.1966121799 Jun 06 04:43:20 PM PDT 24 Jun 06 04:53:11 PM PDT 24 4693263728 ps
T1161 /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.3387173610 Jun 06 04:23:34 PM PDT 24 Jun 06 04:27:41 PM PDT 24 2522957252 ps
T1162 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3097397981 Jun 06 04:34:49 PM PDT 24 Jun 06 04:47:17 PM PDT 24 4049816536 ps
T802 /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.2173917928 Jun 06 04:44:03 PM PDT 24 Jun 06 04:50:38 PM PDT 24 3972840566 ps
T332 /workspace/coverage/default/2.chip_plic_all_irqs_0.1202017170 Jun 06 04:33:11 PM PDT 24 Jun 06 04:50:19 PM PDT 24 5967177192 ps
T1163 /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.81991659 Jun 06 04:31:14 PM PDT 24 Jun 06 04:34:12 PM PDT 24 2352863669 ps
T201 /workspace/coverage/default/0.chip_sw_usbdev_stream.2881554911 Jun 06 04:11:22 PM PDT 24 Jun 06 05:27:55 PM PDT 24 18692148140 ps
T1164 /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.3730710050 Jun 06 04:26:29 PM PDT 24 Jun 06 05:11:05 PM PDT 24 26659897200 ps
T766 /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.152815451 Jun 06 04:45:39 PM PDT 24 Jun 06 04:51:14 PM PDT 24 4144977424 ps
T1165 /workspace/coverage/default/2.chip_sw_otbn_randomness.1722823696 Jun 06 04:30:22 PM PDT 24 Jun 06 04:48:18 PM PDT 24 5323620632 ps
T303 /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.3098190958 Jun 06 04:33:12 PM PDT 24 Jun 06 04:46:03 PM PDT 24 7860650984 ps
T839 /workspace/coverage/default/7.chip_sw_all_escalation_resets.3621308888 Jun 06 04:38:14 PM PDT 24 Jun 06 04:48:02 PM PDT 24 4441434184 ps
T157 /workspace/coverage/default/1.chip_plic_all_irqs_10.1074256593 Jun 06 04:22:41 PM PDT 24 Jun 06 04:31:39 PM PDT 24 3730877290 ps
T792 /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.1641665038 Jun 06 04:39:22 PM PDT 24 Jun 06 04:45:19 PM PDT 24 3204670702 ps
T278 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.364019870 Jun 06 04:22:37 PM PDT 24 Jun 06 04:33:13 PM PDT 24 4583944234 ps
T205 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.2308673240 Jun 06 04:22:39 PM PDT 24 Jun 06 04:53:53 PM PDT 24 23748881982 ps
T1166 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.555519554 Jun 06 04:20:10 PM PDT 24 Jun 06 04:28:29 PM PDT 24 4214172704 ps
T1167 /workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.2858911124 Jun 06 04:38:07 PM PDT 24 Jun 06 05:54:42 PM PDT 24 19965974020 ps
T221 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.2231409372 Jun 06 04:19:44 PM PDT 24 Jun 06 05:15:48 PM PDT 24 20545502448 ps
T1168 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.2728252379 Jun 06 04:19:20 PM PDT 24 Jun 06 04:32:47 PM PDT 24 9905265775 ps
T1169 /workspace/coverage/default/1.chip_sw_hmac_multistream.957725876 Jun 06 04:22:12 PM PDT 24 Jun 06 04:42:58 PM PDT 24 6685665144 ps
T1170 /workspace/coverage/default/2.chip_sw_alert_handler_escalation.1041350359 Jun 06 04:30:14 PM PDT 24 Jun 06 04:39:52 PM PDT 24 4291751420 ps
T560 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.1053992073 Jun 06 04:13:20 PM PDT 24 Jun 06 04:23:44 PM PDT 24 3899063988 ps
T1171 /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.1715283527 Jun 06 04:11:31 PM PDT 24 Jun 06 05:35:11 PM PDT 24 46147326760 ps
T25 /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1376786155 Jun 06 04:09:10 PM PDT 24 Jun 06 04:15:57 PM PDT 24 2525133833 ps
T1172 /workspace/coverage/default/0.chip_sw_data_integrity_escalation.3813643471 Jun 06 04:09:12 PM PDT 24 Jun 06 04:19:40 PM PDT 24 6026481250 ps
T1173 /workspace/coverage/default/1.chip_sw_ast_clk_outputs.1624061801 Jun 06 04:23:53 PM PDT 24 Jun 06 04:43:05 PM PDT 24 6919573032 ps
T340 /workspace/coverage/default/2.chip_sw_entropy_src_csrng.2313588910 Jun 06 04:31:19 PM PDT 24 Jun 06 04:55:48 PM PDT 24 7711575730 ps
T557 /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.558433898 Jun 06 04:19:53 PM PDT 24 Jun 06 04:36:43 PM PDT 24 4852888800 ps
T1174 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.3584728356 Jun 06 04:32:21 PM PDT 24 Jun 06 04:36:53 PM PDT 24 2793804212 ps
T1175 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.319941686 Jun 06 04:39:07 PM PDT 24 Jun 06 05:02:42 PM PDT 24 8101099789 ps
T1176 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.3369114797 Jun 06 04:20:16 PM PDT 24 Jun 06 04:32:19 PM PDT 24 8759489450 ps
T836 /workspace/coverage/default/92.chip_sw_all_escalation_resets.2732773266 Jun 06 04:46:29 PM PDT 24 Jun 06 04:55:22 PM PDT 24 4895802640 ps
T1177 /workspace/coverage/default/60.chip_sw_all_escalation_resets.2766865939 Jun 06 04:44:26 PM PDT 24 Jun 06 04:54:10 PM PDT 24 6052996560 ps
T467 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.4143202480 Jun 06 04:34:48 PM PDT 24 Jun 06 05:32:08 PM PDT 24 24501660746 ps
T1178 /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.3673819987 Jun 06 04:41:18 PM PDT 24 Jun 06 04:48:52 PM PDT 24 4427096532 ps
T1179 /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.298918509 Jun 06 04:40:45 PM PDT 24 Jun 06 04:53:41 PM PDT 24 13136447791 ps
T241 /workspace/coverage/default/1.chip_sw_flash_init.1676500588 Jun 06 04:18:47 PM PDT 24 Jun 06 04:50:36 PM PDT 24 20541278633 ps
T115 /workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.4046855398 Jun 06 04:39:42 PM PDT 24 Jun 06 05:09:28 PM PDT 24 16439026021 ps
T334 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.1406645889 Jun 06 04:27:27 PM PDT 24 Jun 06 04:43:06 PM PDT 24 5097602960 ps
T1180 /workspace/coverage/default/5.chip_sw_all_escalation_resets.3693284915 Jun 06 04:38:24 PM PDT 24 Jun 06 04:48:47 PM PDT 24 5742718256 ps
T1181 /workspace/coverage/default/1.chip_sw_flash_ctrl_access.3168538786 Jun 06 04:17:30 PM PDT 24 Jun 06 04:35:38 PM PDT 24 6510691250 ps
T362 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.988514271 Jun 06 04:24:00 PM PDT 24 Jun 06 04:38:13 PM PDT 24 5191731132 ps
T1182 /workspace/coverage/default/56.chip_sw_all_escalation_resets.3975664459 Jun 06 04:45:48 PM PDT 24 Jun 06 04:56:06 PM PDT 24 4944168264 ps
T189 /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.2355188943 Jun 06 04:17:11 PM PDT 24 Jun 06 04:25:18 PM PDT 24 4614740211 ps
T1183 /workspace/coverage/default/1.chip_sw_hmac_smoketest.3476753864 Jun 06 04:34:25 PM PDT 24 Jun 06 04:40:48 PM PDT 24 2918250236 ps
T1184 /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.2407200051 Jun 06 04:41:49 PM PDT 24 Jun 06 04:49:07 PM PDT 24 4018858776 ps
T1185 /workspace/coverage/default/1.chip_sw_kmac_idle.2035926293 Jun 06 04:24:06 PM PDT 24 Jun 06 04:27:22 PM PDT 24 2557370016 ps
T1186 /workspace/coverage/default/0.chip_sw_alert_handler_entropy.223530539 Jun 06 04:13:38 PM PDT 24 Jun 06 04:18:42 PM PDT 24 3380815679 ps
T1187 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.2321426784 Jun 06 04:30:09 PM PDT 24 Jun 06 04:48:00 PM PDT 24 11026790640 ps
T1188 /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.3379476687 Jun 06 04:44:30 PM PDT 24 Jun 06 04:50:30 PM PDT 24 3838829144 ps
T1189 /workspace/coverage/default/0.chip_sw_gpio_smoketest.653705370 Jun 06 04:15:52 PM PDT 24 Jun 06 04:20:40 PM PDT 24 3260534035 ps
T1190 /workspace/coverage/default/1.chip_sw_csrng_kat_test.514384349 Jun 06 04:21:21 PM PDT 24 Jun 06 04:26:51 PM PDT 24 3742716790 ps
T758 /workspace/coverage/default/1.chip_sw_pattgen_ios.2817548565 Jun 06 04:15:51 PM PDT 24 Jun 06 04:21:11 PM PDT 24 3334794588 ps
T1191 /workspace/coverage/default/2.chip_sw_example_flash.11269389 Jun 06 04:28:45 PM PDT 24 Jun 06 04:34:32 PM PDT 24 2865171732 ps
T828 /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.4038233055 Jun 06 04:47:55 PM PDT 24 Jun 06 04:54:08 PM PDT 24 3802109316 ps
T263 /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.2552236125 Jun 06 04:29:49 PM PDT 24 Jun 06 04:40:21 PM PDT 24 6445804024 ps
T1192 /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.2426162852 Jun 06 04:14:51 PM PDT 24 Jun 06 04:19:10 PM PDT 24 3034381940 ps
T1193 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.276809712 Jun 06 04:13:42 PM PDT 24 Jun 06 04:20:32 PM PDT 24 7020576724 ps
T1194 /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.1158261135 Jun 06 04:12:00 PM PDT 24 Jun 06 04:21:15 PM PDT 24 5227639760 ps
T1195 /workspace/coverage/default/0.chip_sw_flash_ctrl_access.2571348571 Jun 06 04:09:05 PM PDT 24 Jun 06 04:25:46 PM PDT 24 5531381292 ps
T1196 /workspace/coverage/default/0.chip_sw_hmac_multistream.2906381358 Jun 06 04:12:42 PM PDT 24 Jun 06 04:37:05 PM PDT 24 6713259328 ps
T379 /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2886517137 Jun 06 04:23:06 PM PDT 24 Jun 06 04:29:11 PM PDT 24 6536327304 ps
T1197 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.718330389 Jun 06 04:13:19 PM PDT 24 Jun 06 04:18:15 PM PDT 24 3700529519 ps
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