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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.99 95.52 94.01 95.51 94.89 96.47 99.55


Total test records in report: 2887
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T904 /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.1864798855 Jun 07 10:10:39 PM PDT 24 Jun 07 10:16:45 PM PDT 24 4054740744 ps
T1019 /workspace/coverage/default/1.chip_sw_flash_ctrl_access.3926170741 Jun 07 09:43:02 PM PDT 24 Jun 07 09:58:29 PM PDT 24 5066389432 ps
T12 /workspace/coverage/default/1.chip_sw_sleep_pin_retention.3158195405 Jun 07 09:42:38 PM PDT 24 Jun 07 09:47:36 PM PDT 24 4349893144 ps
T859 /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.2978138708 Jun 07 10:10:17 PM PDT 24 Jun 07 10:16:28 PM PDT 24 4221772320 ps
T216 /workspace/coverage/default/2.chip_sw_power_idle_load.270416399 Jun 07 10:00:52 PM PDT 24 Jun 07 10:13:11 PM PDT 24 4816702684 ps
T1020 /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.3622470536 Jun 07 10:08:16 PM PDT 24 Jun 07 10:15:06 PM PDT 24 6818717413 ps
T898 /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.3050075616 Jun 07 10:08:46 PM PDT 24 Jun 07 10:14:12 PM PDT 24 4190785948 ps
T755 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2000376845 Jun 07 09:37:57 PM PDT 24 Jun 07 10:50:37 PM PDT 24 24162746199 ps
T880 /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.2430279951 Jun 07 10:09:06 PM PDT 24 Jun 07 10:16:22 PM PDT 24 3879834136 ps
T1021 /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.176119700 Jun 07 10:08:43 PM PDT 24 Jun 07 10:38:01 PM PDT 24 8567050566 ps
T282 /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.755601305 Jun 07 09:42:01 PM PDT 24 Jun 07 09:44:08 PM PDT 24 2869185747 ps
T1022 /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.3721216365 Jun 07 10:02:08 PM PDT 24 Jun 07 10:05:41 PM PDT 24 2269545822 ps
T1023 /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.4219943218 Jun 07 09:48:10 PM PDT 24 Jun 07 09:55:58 PM PDT 24 4444668312 ps
T34 /workspace/coverage/default/0.chip_sw_usbdev_config_host.1335782094 Jun 07 09:37:17 PM PDT 24 Jun 07 10:15:42 PM PDT 24 7766385836 ps
T445 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.1220911119 Jun 07 09:36:25 PM PDT 24 Jun 07 09:52:28 PM PDT 24 6446030700 ps
T215 /workspace/coverage/default/0.chip_sw_pattgen_ios.885190841 Jun 07 09:35:37 PM PDT 24 Jun 07 09:41:22 PM PDT 24 2842440444 ps
T1024 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.3369418755 Jun 07 09:56:46 PM PDT 24 Jun 07 10:53:15 PM PDT 24 14666811900 ps
T761 /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.369326074 Jun 07 10:01:05 PM PDT 24 Jun 07 10:10:42 PM PDT 24 5708089764 ps
T1025 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2365174890 Jun 07 09:50:52 PM PDT 24 Jun 07 10:09:46 PM PDT 24 7474359329 ps
T283 /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.778643438 Jun 07 09:38:26 PM PDT 24 Jun 07 09:47:07 PM PDT 24 9409489244 ps
T1026 /workspace/coverage/default/1.rom_keymgr_functest.3340652396 Jun 07 09:52:30 PM PDT 24 Jun 07 10:01:47 PM PDT 24 5159418972 ps
T1027 /workspace/coverage/default/1.chip_sw_kmac_smoketest.3567726342 Jun 07 09:54:00 PM PDT 24 Jun 07 09:59:56 PM PDT 24 3013967100 ps
T1028 /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.567516891 Jun 07 09:42:09 PM PDT 24 Jun 07 09:47:53 PM PDT 24 5059597478 ps
T1029 /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.2636751483 Jun 07 10:03:49 PM PDT 24 Jun 07 10:07:12 PM PDT 24 2558127728 ps
T805 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.797078662 Jun 07 09:46:11 PM PDT 24 Jun 07 11:19:30 PM PDT 24 22399161859 ps
T11 /workspace/coverage/default/1.chip_sw_sleep_pin_wake.3907821650 Jun 07 09:42:52 PM PDT 24 Jun 07 09:47:16 PM PDT 24 3474816516 ps
T429 /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.3574657596 Jun 07 10:14:19 PM PDT 24 Jun 07 10:21:26 PM PDT 24 4032031226 ps
T201 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.2953230415 Jun 07 09:37:52 PM PDT 24 Jun 07 09:49:53 PM PDT 24 4942988386 ps
T430 /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.151484265 Jun 07 10:10:11 PM PDT 24 Jun 07 10:18:12 PM PDT 24 3110735000 ps
T123 /workspace/coverage/default/1.chip_sw_entropy_src_csrng.3258489041 Jun 07 09:45:42 PM PDT 24 Jun 07 10:15:53 PM PDT 24 8317489512 ps
T346 /workspace/coverage/default/1.chip_plic_all_irqs_20.2123857129 Jun 07 09:48:07 PM PDT 24 Jun 07 10:04:53 PM PDT 24 4427805440 ps
T59 /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.3377259079 Jun 07 09:53:39 PM PDT 24 Jun 07 10:03:06 PM PDT 24 5754398320 ps
T259 /workspace/coverage/default/4.chip_sw_all_escalation_resets.2903115852 Jun 07 10:05:13 PM PDT 24 Jun 07 10:16:00 PM PDT 24 4861739312 ps
T309 /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.1019681021 Jun 07 09:36:11 PM PDT 24 Jun 07 10:01:50 PM PDT 24 9519024729 ps
T310 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.2433989263 Jun 07 09:47:16 PM PDT 24 Jun 07 09:51:46 PM PDT 24 2715174706 ps
T275 /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.530762968 Jun 07 10:07:32 PM PDT 24 Jun 07 11:18:04 PM PDT 24 20113596952 ps
T231 /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.2392322841 Jun 07 09:59:39 PM PDT 24 Jun 07 10:28:25 PM PDT 24 9100758996 ps
T311 /workspace/coverage/default/2.chip_sw_edn_kat.571968713 Jun 07 10:01:03 PM PDT 24 Jun 07 10:12:56 PM PDT 24 2815062104 ps
T312 /workspace/coverage/default/62.chip_sw_all_escalation_resets.3557363283 Jun 07 10:11:58 PM PDT 24 Jun 07 10:24:02 PM PDT 24 4830639072 ps
T313 /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.729623211 Jun 07 10:09:51 PM PDT 24 Jun 07 10:17:40 PM PDT 24 4234700360 ps
T314 /workspace/coverage/default/26.chip_sw_all_escalation_resets.2623742886 Jun 07 10:09:11 PM PDT 24 Jun 07 10:21:39 PM PDT 24 5824190498 ps
T167 /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.2667163260 Jun 07 09:38:52 PM PDT 24 Jun 07 09:51:36 PM PDT 24 6093497668 ps
T383 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.3227251456 Jun 07 09:36:10 PM PDT 24 Jun 07 09:49:33 PM PDT 24 5163744008 ps
T384 /workspace/coverage/default/3.chip_sw_all_escalation_resets.1663263680 Jun 07 10:06:42 PM PDT 24 Jun 07 10:17:32 PM PDT 24 4747105540 ps
T63 /workspace/coverage/default/2.chip_tap_straps_rma.2405317934 Jun 07 10:03:40 PM PDT 24 Jun 07 10:13:12 PM PDT 24 5350358353 ps
T326 /workspace/coverage/default/83.chip_sw_all_escalation_resets.1658551342 Jun 07 10:15:53 PM PDT 24 Jun 07 10:26:39 PM PDT 24 5565150380 ps
T332 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.729615773 Jun 07 10:00:37 PM PDT 24 Jun 07 10:15:55 PM PDT 24 9955562525 ps
T333 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.2891572602 Jun 07 09:45:28 PM PDT 24 Jun 07 09:57:24 PM PDT 24 5906582296 ps
T128 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.736625303 Jun 07 09:37:33 PM PDT 24 Jun 07 09:45:55 PM PDT 24 5371404924 ps
T334 /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.3475214891 Jun 07 09:41:04 PM PDT 24 Jun 07 10:04:27 PM PDT 24 5266734040 ps
T335 /workspace/coverage/default/4.chip_tap_straps_prod.4158169677 Jun 07 10:05:11 PM PDT 24 Jun 07 10:08:01 PM PDT 24 2479498459 ps
T336 /workspace/coverage/default/3.chip_sw_uart_tx_rx.3276226114 Jun 07 10:04:05 PM PDT 24 Jun 07 10:18:01 PM PDT 24 4947503400 ps
T337 /workspace/coverage/default/0.chip_sw_hmac_oneshot.1861479761 Jun 07 09:39:04 PM PDT 24 Jun 07 09:44:27 PM PDT 24 2787363620 ps
T338 /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.3423097666 Jun 07 10:07:33 PM PDT 24 Jun 07 10:14:01 PM PDT 24 3127928304 ps
T339 /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.2135087540 Jun 07 10:15:37 PM PDT 24 Jun 07 10:21:49 PM PDT 24 4007948288 ps
T891 /workspace/coverage/default/21.chip_sw_all_escalation_resets.3503981869 Jun 07 10:07:57 PM PDT 24 Jun 07 10:21:22 PM PDT 24 5519446210 ps
T1030 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2127535426 Jun 07 09:45:50 PM PDT 24 Jun 07 10:12:03 PM PDT 24 11846168957 ps
T253 /workspace/coverage/default/3.chip_sw_data_integrity_escalation.3502111158 Jun 07 10:04:17 PM PDT 24 Jun 07 10:15:28 PM PDT 24 5679786680 ps
T1031 /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.278938609 Jun 07 10:11:08 PM PDT 24 Jun 07 10:18:16 PM PDT 24 4036795996 ps
T15 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.444441716 Jun 07 10:01:41 PM PDT 24 Jun 07 10:23:03 PM PDT 24 23509232058 ps
T1032 /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.2448511363 Jun 07 10:06:32 PM PDT 24 Jun 07 10:14:42 PM PDT 24 6422195455 ps
T1033 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.1220750656 Jun 07 09:44:10 PM PDT 24 Jun 07 10:40:54 PM PDT 24 18797685009 ps
T1034 /workspace/coverage/default/2.chip_sw_flash_ctrl_access.4273350213 Jun 07 09:56:54 PM PDT 24 Jun 07 10:13:31 PM PDT 24 6027994264 ps
T847 /workspace/coverage/default/66.chip_sw_all_escalation_resets.1796207025 Jun 07 10:13:51 PM PDT 24 Jun 07 10:25:40 PM PDT 24 5417829208 ps
T1035 /workspace/coverage/default/1.chip_sw_alert_handler_escalation.2748509712 Jun 07 09:44:39 PM PDT 24 Jun 07 09:52:34 PM PDT 24 4405218532 ps
T349 /workspace/coverage/default/0.chip_sw_entropy_src_csrng.561274763 Jun 07 09:37:25 PM PDT 24 Jun 07 10:07:17 PM PDT 24 7687730334 ps
T232 /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.1740093428 Jun 07 10:10:13 PM PDT 24 Jun 07 10:16:02 PM PDT 24 3797017896 ps
T183 /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.2373115497 Jun 07 09:57:44 PM PDT 24 Jun 07 10:10:52 PM PDT 24 6402693580 ps
T781 /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.3407649696 Jun 07 10:02:02 PM PDT 24 Jun 07 10:06:50 PM PDT 24 3605035810 ps
T8 /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.1086287180 Jun 07 09:41:27 PM PDT 24 Jun 07 09:46:57 PM PDT 24 3634334232 ps
T806 /workspace/coverage/default/0.chip_sw_aon_timer_irq.1043019233 Jun 07 09:38:04 PM PDT 24 Jun 07 09:45:55 PM PDT 24 3984170866 ps
T76 /workspace/coverage/default/2.chip_jtag_csr_rw.2648652005 Jun 07 09:53:44 PM PDT 24 Jun 07 10:14:31 PM PDT 24 10705356366 ps
T807 /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.420306478 Jun 07 10:15:09 PM PDT 24 Jun 07 10:20:40 PM PDT 24 3698662104 ps
T239 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.154934506 Jun 07 09:54:22 PM PDT 24 Jun 07 10:15:58 PM PDT 24 8651957786 ps
T808 /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.3323767809 Jun 07 09:37:05 PM PDT 24 Jun 07 09:46:30 PM PDT 24 4988035540 ps
T443 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.2905607566 Jun 07 09:37:52 PM PDT 24 Jun 07 10:10:37 PM PDT 24 7881645320 ps
T763 /workspace/coverage/default/1.rom_volatile_raw_unlock.1479045872 Jun 07 09:52:59 PM PDT 24 Jun 07 09:55:02 PM PDT 24 2910664090 ps
T809 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.3941152816 Jun 07 09:57:52 PM PDT 24 Jun 07 10:22:23 PM PDT 24 8851843688 ps
T810 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.3495126064 Jun 07 09:45:42 PM PDT 24 Jun 07 10:42:52 PM PDT 24 14661689648 ps
T46 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.477944111 Jun 07 09:43:59 PM PDT 24 Jun 07 09:52:26 PM PDT 24 6200068592 ps
T376 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.4189131096 Jun 07 09:50:21 PM PDT 24 Jun 07 09:57:40 PM PDT 24 6128074524 ps
T172 /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.1131590196 Jun 07 09:42:01 PM PDT 24 Jun 07 10:20:52 PM PDT 24 26805400312 ps
T1036 /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.1394001541 Jun 07 09:40:40 PM PDT 24 Jun 07 09:46:50 PM PDT 24 5449296472 ps
T1037 /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.3090073282 Jun 07 09:57:42 PM PDT 24 Jun 07 10:01:07 PM PDT 24 2531137208 ps
T345 /workspace/coverage/default/0.chip_plic_all_irqs_20.4033586042 Jun 07 09:40:12 PM PDT 24 Jun 07 09:55:13 PM PDT 24 4675182588 ps
T284 /workspace/coverage/default/1.chip_sw_data_integrity_escalation.1182767568 Jun 07 09:40:19 PM PDT 24 Jun 07 09:51:35 PM PDT 24 4787661500 ps
T850 /workspace/coverage/default/68.chip_sw_all_escalation_resets.1251908137 Jun 07 10:13:06 PM PDT 24 Jun 07 10:23:23 PM PDT 24 4718532666 ps
T1038 /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.2416771036 Jun 07 10:12:30 PM PDT 24 Jun 07 10:34:17 PM PDT 24 8502021168 ps
T1039 /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.2023621208 Jun 07 09:44:44 PM PDT 24 Jun 07 10:38:15 PM PDT 24 11012327086 ps
T99 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.811864903 Jun 07 09:37:29 PM PDT 24 Jun 07 10:05:34 PM PDT 24 22368723012 ps
T1040 /workspace/coverage/default/2.chip_tap_straps_dev.1433759592 Jun 07 10:00:39 PM PDT 24 Jun 07 10:31:26 PM PDT 24 16258794324 ps
T1041 /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.1341461379 Jun 07 10:09:03 PM PDT 24 Jun 07 10:53:26 PM PDT 24 12347233210 ps
T764 /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.2271371794 Jun 07 09:36:06 PM PDT 24 Jun 07 09:38:19 PM PDT 24 3207270849 ps
T174 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2179825236 Jun 07 09:52:31 PM PDT 24 Jun 07 10:01:41 PM PDT 24 4182299070 ps
T150 /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.52110350 Jun 07 09:41:44 PM PDT 24 Jun 08 12:45:21 AM PDT 24 59078299269 ps
T854 /workspace/coverage/default/46.chip_sw_all_escalation_resets.3413367285 Jun 07 10:12:32 PM PDT 24 Jun 07 10:21:34 PM PDT 24 5521415896 ps
T1042 /workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.2592602607 Jun 07 10:07:19 PM PDT 24 Jun 07 10:59:20 PM PDT 24 14334346500 ps
T1043 /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.1898874254 Jun 07 09:44:30 PM PDT 24 Jun 07 10:05:47 PM PDT 24 8185502717 ps
T163 /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.4032572530 Jun 07 09:38:18 PM PDT 24 Jun 07 09:42:56 PM PDT 24 2603321540 ps
T175 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.1080210491 Jun 07 09:37:31 PM PDT 24 Jun 07 09:46:44 PM PDT 24 6713234392 ps
T788 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.4107313041 Jun 07 09:37:34 PM PDT 24 Jun 07 09:42:55 PM PDT 24 3369639928 ps
T358 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.1318029459 Jun 07 09:36:08 PM PDT 24 Jun 07 09:46:02 PM PDT 24 4636483166 ps
T1044 /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.1289446009 Jun 07 09:53:59 PM PDT 24 Jun 07 09:58:30 PM PDT 24 2965741000 ps
T1045 /workspace/coverage/default/99.chip_sw_all_escalation_resets.596545242 Jun 07 10:14:50 PM PDT 24 Jun 07 10:22:11 PM PDT 24 5117931994 ps
T905 /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.2592893164 Jun 07 10:10:02 PM PDT 24 Jun 07 10:16:03 PM PDT 24 3446121640 ps
T1046 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.702879265 Jun 07 09:58:51 PM PDT 24 Jun 07 10:09:39 PM PDT 24 8748052460 ps
T80 /workspace/coverage/default/0.chip_sw_alert_handler_entropy.2982281535 Jun 07 09:40:05 PM PDT 24 Jun 07 09:45:58 PM PDT 24 3908138619 ps
T837 /workspace/coverage/default/63.chip_sw_all_escalation_resets.2254877554 Jun 07 10:12:47 PM PDT 24 Jun 07 10:25:17 PM PDT 24 5481175892 ps
T1047 /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.4083838368 Jun 07 10:02:57 PM PDT 24 Jun 07 10:21:07 PM PDT 24 5475473100 ps
T1048 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2011836786 Jun 07 09:48:24 PM PDT 24 Jun 07 09:59:19 PM PDT 24 4153111832 ps
T36 /workspace/coverage/default/1.chip_sw_gpio.2224555870 Jun 07 09:41:34 PM PDT 24 Jun 07 09:49:52 PM PDT 24 3562865480 ps
T403 /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.414294958 Jun 07 09:39:05 PM PDT 24 Jun 07 10:04:47 PM PDT 24 9384858724 ps
T362 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2860594772 Jun 07 09:50:27 PM PDT 24 Jun 07 10:01:56 PM PDT 24 4695547887 ps
T186 /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.1864436594 Jun 07 09:35:23 PM PDT 24 Jun 07 09:42:35 PM PDT 24 4787608907 ps
T1049 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2047212108 Jun 07 09:38:35 PM PDT 24 Jun 07 09:50:25 PM PDT 24 3786678230 ps
T835 /workspace/coverage/default/2.chip_sw_otbn_smoketest.458655464 Jun 07 10:02:55 PM PDT 24 Jun 07 10:20:21 PM PDT 24 4850944832 ps
T855 /workspace/coverage/default/84.chip_sw_all_escalation_resets.2555483184 Jun 07 10:15:12 PM PDT 24 Jun 07 10:28:03 PM PDT 24 4653697110 ps
T845 /workspace/coverage/default/8.chip_sw_all_escalation_resets.3279686528 Jun 07 10:06:43 PM PDT 24 Jun 07 10:16:43 PM PDT 24 4689234120 ps
T168 /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.4275428303 Jun 07 09:38:47 PM PDT 24 Jun 07 09:51:41 PM PDT 24 5627900724 ps
T1050 /workspace/coverage/default/2.chip_sw_aes_smoketest.2263499114 Jun 07 10:06:09 PM PDT 24 Jun 07 10:11:16 PM PDT 24 2975521420 ps
T1051 /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.2943843126 Jun 07 10:00:26 PM PDT 24 Jun 07 10:10:55 PM PDT 24 4766751062 ps
T1052 /workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.4218750271 Jun 07 09:38:18 PM PDT 24 Jun 07 09:59:06 PM PDT 24 8147033332 ps
T140 /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.955777749 Jun 07 09:55:53 PM PDT 24 Jun 07 10:03:51 PM PDT 24 9601355880 ps
T1053 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.2513238672 Jun 07 09:39:22 PM PDT 24 Jun 07 09:44:02 PM PDT 24 3288569981 ps
T1054 /workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.3234803154 Jun 07 10:06:17 PM PDT 24 Jun 07 11:02:32 PM PDT 24 16550763456 ps
T81 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.2996251524 Jun 07 09:57:18 PM PDT 24 Jun 07 10:13:43 PM PDT 24 11234964648 ps
T1055 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.364620167 Jun 07 09:42:48 PM PDT 24 Jun 07 10:27:32 PM PDT 24 10420732750 ps
T1056 /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2025907589 Jun 07 10:06:17 PM PDT 24 Jun 07 10:14:52 PM PDT 24 7303520480 ps
T545 /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.3117474909 Jun 07 09:43:36 PM PDT 24 Jun 07 10:00:16 PM PDT 24 4082577940 ps
T882 /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3136246546 Jun 07 10:13:14 PM PDT 24 Jun 07 10:22:21 PM PDT 24 3641354976 ps
T407 /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.3178252727 Jun 07 09:49:35 PM PDT 24 Jun 07 09:56:09 PM PDT 24 2875216696 ps
T1057 /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.2953120321 Jun 07 09:55:34 PM PDT 24 Jun 07 10:11:27 PM PDT 24 5830974170 ps
T1058 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.820420083 Jun 07 09:35:55 PM PDT 24 Jun 07 09:46:45 PM PDT 24 4305096800 ps
T812 /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.2605325722 Jun 07 09:58:22 PM PDT 24 Jun 07 10:11:45 PM PDT 24 4988084920 ps
T342 /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.3654586120 Jun 07 09:55:43 PM PDT 24 Jun 07 11:17:42 PM PDT 24 44547405982 ps
T1059 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.1877241908 Jun 07 09:37:27 PM PDT 24 Jun 07 10:43:44 PM PDT 24 17118451440 ps
T381 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.1935393764 Jun 07 09:44:58 PM PDT 24 Jun 07 10:08:37 PM PDT 24 11230295972 ps
T260 /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.3247955919 Jun 07 10:12:46 PM PDT 24 Jun 07 10:18:25 PM PDT 24 3574272740 ps
T1060 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.1011892355 Jun 07 09:58:58 PM PDT 24 Jun 07 10:24:45 PM PDT 24 7898852000 ps
T1061 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.2135795613 Jun 07 09:36:21 PM PDT 24 Jun 07 09:57:17 PM PDT 24 8203429478 ps
T1062 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.3005217378 Jun 07 09:49:55 PM PDT 24 Jun 07 09:58:42 PM PDT 24 5164170605 ps
T43 /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.3213066446 Jun 07 09:40:34 PM PDT 24 Jun 07 09:45:36 PM PDT 24 2834435600 ps
T860 /workspace/coverage/default/2.chip_sw_all_escalation_resets.333193332 Jun 07 09:55:46 PM PDT 24 Jun 07 10:07:11 PM PDT 24 4870587120 ps
T327 /workspace/coverage/default/38.chip_sw_all_escalation_resets.559899505 Jun 07 10:11:08 PM PDT 24 Jun 07 10:22:49 PM PDT 24 5421793396 ps
T69 /workspace/coverage/default/0.chip_tap_straps_testunlock0.1350314152 Jun 07 09:38:47 PM PDT 24 Jun 07 09:54:31 PM PDT 24 9277858483 ps
T883 /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1718048243 Jun 07 10:14:33 PM PDT 24 Jun 07 10:21:18 PM PDT 24 4038198734 ps
T343 /workspace/coverage/default/2.chip_plic_all_irqs_0.2829586214 Jun 07 10:02:12 PM PDT 24 Jun 07 10:24:02 PM PDT 24 6112972360 ps
T247 /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.4097802576 Jun 07 09:42:18 PM PDT 24 Jun 07 09:51:34 PM PDT 24 5116798420 ps
T907 /workspace/coverage/default/97.chip_sw_all_escalation_resets.1760778879 Jun 07 10:17:53 PM PDT 24 Jun 07 10:25:53 PM PDT 24 5582211000 ps
T263 /workspace/coverage/default/1.chip_sw_plic_sw_irq.1535605549 Jun 07 09:48:16 PM PDT 24 Jun 07 09:53:36 PM PDT 24 3281905880 ps
T871 /workspace/coverage/default/6.chip_sw_all_escalation_resets.3958571530 Jun 07 10:07:20 PM PDT 24 Jun 07 10:16:38 PM PDT 24 4843963250 ps
T218 /workspace/coverage/default/0.chip_sw_inject_scramble_seed.2212052024 Jun 07 09:36:34 PM PDT 24 Jun 08 01:13:28 AM PDT 24 64340884492 ps
T378 /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2013313400 Jun 07 09:50:58 PM PDT 24 Jun 07 10:01:34 PM PDT 24 5720341044 ps
T1063 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.3443737515 Jun 07 09:59:12 PM PDT 24 Jun 07 10:03:56 PM PDT 24 2730360742 ps
T1064 /workspace/coverage/default/1.rom_e2e_asm_init_prod.1463404863 Jun 07 09:57:34 PM PDT 24 Jun 07 10:49:48 PM PDT 24 14433960610 ps
T841 /workspace/coverage/default/91.chip_sw_all_escalation_resets.2265502606 Jun 07 10:15:23 PM PDT 24 Jun 07 10:26:26 PM PDT 24 5111802536 ps
T1065 /workspace/coverage/default/2.chip_sw_aes_masking_off.3589980845 Jun 07 09:56:30 PM PDT 24 Jun 07 10:00:51 PM PDT 24 2606837422 ps
T1066 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.2044465226 Jun 07 09:43:04 PM PDT 24 Jun 07 10:42:23 PM PDT 24 13649862088 ps
T371 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.1231446015 Jun 07 09:46:23 PM PDT 24 Jun 07 09:51:56 PM PDT 24 2379112314 ps
T1067 /workspace/coverage/default/2.chip_sw_aes_enc.624260400 Jun 07 09:57:52 PM PDT 24 Jun 07 10:01:52 PM PDT 24 2834253756 ps
T1068 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.929962901 Jun 07 09:57:57 PM PDT 24 Jun 07 11:08:17 PM PDT 24 17813112284 ps
T100 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.920505838 Jun 07 09:49:58 PM PDT 24 Jun 07 09:57:13 PM PDT 24 6774380214 ps
T1069 /workspace/coverage/default/2.chip_tap_straps_prod.3915723913 Jun 07 10:00:16 PM PDT 24 Jun 07 10:28:18 PM PDT 24 15392275162 ps
T1070 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.754099396 Jun 07 09:44:15 PM PDT 24 Jun 07 10:49:12 PM PDT 24 17504495384 ps
T861 /workspace/coverage/default/57.chip_sw_all_escalation_resets.3988143626 Jun 07 10:13:01 PM PDT 24 Jun 07 10:23:53 PM PDT 24 6681161032 ps
T1071 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.2362850816 Jun 07 09:56:45 PM PDT 24 Jun 07 10:19:28 PM PDT 24 6959355978 ps
T359 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.583903853 Jun 07 09:41:49 PM PDT 24 Jun 07 09:53:30 PM PDT 24 4071419144 ps
T823 /workspace/coverage/default/89.chip_sw_all_escalation_resets.2184114097 Jun 07 10:14:48 PM PDT 24 Jun 07 10:23:19 PM PDT 24 4707624520 ps
T84 /workspace/coverage/default/56.chip_sw_all_escalation_resets.2973370373 Jun 07 10:13:31 PM PDT 24 Jun 07 10:22:43 PM PDT 24 4239126046 ps
T90 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.4272717174 Jun 07 09:56:32 PM PDT 24 Jun 07 10:05:19 PM PDT 24 5464994374 ps
T91 /workspace/coverage/default/0.chip_sw_alert_handler_escalation.1610097533 Jun 07 09:39:41 PM PDT 24 Jun 07 09:50:25 PM PDT 24 4790962384 ps
T92 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.1202539691 Jun 07 09:48:16 PM PDT 24 Jun 07 10:57:10 PM PDT 24 17161823064 ps
T93 /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.2032397549 Jun 07 10:07:27 PM PDT 24 Jun 07 10:14:09 PM PDT 24 3490415544 ps
T94 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3159178076 Jun 07 10:00:52 PM PDT 24 Jun 07 10:13:08 PM PDT 24 4301693096 ps
T95 /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.779769930 Jun 07 09:57:25 PM PDT 24 Jun 07 10:04:36 PM PDT 24 4062508060 ps
T96 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.2062985863 Jun 07 09:40:27 PM PDT 24 Jun 07 09:46:31 PM PDT 24 3402327042 ps
T97 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3198829941 Jun 07 09:39:15 PM PDT 24 Jun 07 09:44:54 PM PDT 24 7351469220 ps
T98 /workspace/coverage/default/1.chip_plic_all_irqs_10.1799854801 Jun 07 09:51:01 PM PDT 24 Jun 07 09:58:21 PM PDT 24 4198227148 ps
T1072 /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.2574526246 Jun 07 09:39:10 PM PDT 24 Jun 07 09:43:06 PM PDT 24 2876667400 ps
T1073 /workspace/coverage/default/1.chip_sw_kmac_idle.3165256605 Jun 07 09:47:50 PM PDT 24 Jun 07 09:51:26 PM PDT 24 3002476536 ps
T1074 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.2322723541 Jun 07 09:35:27 PM PDT 24 Jun 07 09:48:32 PM PDT 24 9762489636 ps
T178 /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.1778048258 Jun 07 09:40:08 PM PDT 24 Jun 07 10:00:26 PM PDT 24 7339442684 ps
T295 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.2175575860 Jun 07 09:39:29 PM PDT 24 Jun 07 09:47:55 PM PDT 24 3913834356 ps
T1075 /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.2256517577 Jun 07 09:43:24 PM PDT 24 Jun 07 09:47:45 PM PDT 24 2775499808 ps
T85 /workspace/coverage/default/10.chip_sw_all_escalation_resets.1617964211 Jun 07 10:11:30 PM PDT 24 Jun 07 10:22:46 PM PDT 24 5341256488 ps
T399 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.2065868922 Jun 07 09:37:09 PM PDT 24 Jun 07 09:50:39 PM PDT 24 4665701912 ps
T1076 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.4103207098 Jun 07 09:45:12 PM PDT 24 Jun 07 10:32:22 PM PDT 24 11535376170 ps
T1077 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2769396087 Jun 07 09:47:37 PM PDT 24 Jun 07 10:51:35 PM PDT 24 32508159210 ps
T1078 /workspace/coverage/default/2.rom_e2e_static_critical.3196201416 Jun 07 10:08:14 PM PDT 24 Jun 07 11:01:24 PM PDT 24 15984532280 ps
T379 /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.525058711 Jun 07 10:01:07 PM PDT 24 Jun 07 10:07:19 PM PDT 24 4702886108 ps
T756 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.3141445180 Jun 07 09:40:41 PM PDT 24 Jun 07 11:17:45 PM PDT 24 26817294360 ps
T1079 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3318825656 Jun 07 10:00:47 PM PDT 24 Jun 07 10:09:57 PM PDT 24 5066992760 ps
T1080 /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.2474475216 Jun 07 09:46:23 PM PDT 24 Jun 07 09:50:40 PM PDT 24 3315014622 ps
T803 /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.2653907897 Jun 07 09:44:00 PM PDT 24 Jun 07 10:08:11 PM PDT 24 8662941960 ps
T1081 /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.1097903604 Jun 07 09:53:45 PM PDT 24 Jun 07 10:03:23 PM PDT 24 4195340880 ps
T889 /workspace/coverage/default/93.chip_sw_all_escalation_resets.1245735141 Jun 07 10:15:27 PM PDT 24 Jun 07 10:23:52 PM PDT 24 6342107020 ps
T1082 /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.4252158381 Jun 07 10:08:45 PM PDT 24 Jun 07 10:16:05 PM PDT 24 4736111180 ps
T1083 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.1838704758 Jun 07 09:43:34 PM PDT 24 Jun 07 09:48:59 PM PDT 24 5856606780 ps
T389 /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.3827278389 Jun 07 09:46:14 PM PDT 24 Jun 07 09:58:47 PM PDT 24 6975075960 ps
T899 /workspace/coverage/default/19.chip_sw_all_escalation_resets.905730576 Jun 07 10:08:42 PM PDT 24 Jun 07 10:18:58 PM PDT 24 5000740360 ps
T1084 /workspace/coverage/default/1.chip_sw_hmac_smoketest.1000965111 Jun 07 09:55:31 PM PDT 24 Jun 07 10:01:37 PM PDT 24 3498680372 ps
T900 /workspace/coverage/default/29.chip_sw_all_escalation_resets.1959095544 Jun 07 10:09:36 PM PDT 24 Jun 07 10:21:53 PM PDT 24 4794600824 ps
T1085 /workspace/coverage/default/2.chip_sw_hmac_smoketest.2068702232 Jun 07 10:03:30 PM PDT 24 Jun 07 10:10:21 PM PDT 24 2931096248 ps
T1086 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.87143242 Jun 07 09:44:07 PM PDT 24 Jun 07 10:02:31 PM PDT 24 7398230800 ps
T1087 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1646219056 Jun 07 09:43:20 PM PDT 24 Jun 07 09:55:00 PM PDT 24 4580520990 ps
T77 /workspace/coverage/default/2.chip_jtag_mem_access.1141260531 Jun 07 09:53:10 PM PDT 24 Jun 07 10:22:00 PM PDT 24 13964880500 ps
T824 /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.3090392792 Jun 07 10:07:51 PM PDT 24 Jun 07 10:14:35 PM PDT 24 3944899226 ps
T842 /workspace/coverage/default/78.chip_sw_all_escalation_resets.2856409283 Jun 07 10:13:33 PM PDT 24 Jun 07 10:23:11 PM PDT 24 5869507420 ps
T408 /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.1832490360 Jun 07 09:50:39 PM PDT 24 Jun 07 09:55:54 PM PDT 24 4180923304 ps
T86 /workspace/coverage/default/23.chip_sw_all_escalation_resets.4121042533 Jun 07 10:08:14 PM PDT 24 Jun 07 10:20:41 PM PDT 24 5191300990 ps
T214 /workspace/coverage/default/1.chip_sw_pattgen_ios.2485621927 Jun 07 09:44:09 PM PDT 24 Jun 07 09:48:16 PM PDT 24 2865755248 ps
T1088 /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.1108488671 Jun 07 10:05:31 PM PDT 24 Jun 07 10:34:48 PM PDT 24 8858931070 ps
T1089 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.919709176 Jun 07 10:01:01 PM PDT 24 Jun 07 10:10:39 PM PDT 24 4744675800 ps
T1090 /workspace/coverage/default/1.chip_sw_aon_timer_irq.2325838630 Jun 07 09:45:05 PM PDT 24 Jun 07 09:52:27 PM PDT 24 3666495352 ps
T1091 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2408677403 Jun 07 09:43:18 PM PDT 24 Jun 07 10:10:28 PM PDT 24 16414108314 ps
T1092 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3493031226 Jun 07 10:01:47 PM PDT 24 Jun 07 10:06:54 PM PDT 24 2833950838 ps
T1093 /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.3806388633 Jun 07 09:57:28 PM PDT 24 Jun 07 11:01:09 PM PDT 24 10892679954 ps
T1094 /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.1893795808 Jun 07 10:05:44 PM PDT 24 Jun 07 10:16:30 PM PDT 24 4767825888 ps
T1095 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3271356100 Jun 07 09:47:49 PM PDT 24 Jun 07 09:58:31 PM PDT 24 4588342090 ps
T1096 /workspace/coverage/default/3.chip_tap_straps_dev.2774038076 Jun 07 10:03:43 PM PDT 24 Jun 07 10:06:48 PM PDT 24 2786345523 ps
T1097 /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.1797316283 Jun 07 10:08:17 PM PDT 24 Jun 07 10:19:34 PM PDT 24 5755920561 ps
T1098 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.3114065794 Jun 07 09:59:32 PM PDT 24 Jun 07 10:09:13 PM PDT 24 7500202798 ps
T1099 /workspace/coverage/default/2.chip_sw_kmac_smoketest.558712914 Jun 07 10:03:19 PM PDT 24 Jun 07 10:08:32 PM PDT 24 3097682272 ps
T1100 /workspace/coverage/default/0.rom_e2e_asm_init_prod.1616915360 Jun 07 09:47:32 PM PDT 24 Jun 07 11:04:44 PM PDT 24 14225358978 ps
T1101 /workspace/coverage/default/2.chip_sw_csrng_kat_test.917302731 Jun 07 09:57:32 PM PDT 24 Jun 07 10:01:42 PM PDT 24 2849082854 ps
T1102 /workspace/coverage/default/0.chip_sw_edn_sw_mode.2938621012 Jun 07 09:37:43 PM PDT 24 Jun 07 10:06:42 PM PDT 24 7526711048 ps
T1103 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.804121377 Jun 07 09:46:08 PM PDT 24 Jun 07 10:44:58 PM PDT 24 14674567480 ps
T1104 /workspace/coverage/default/0.chip_sw_edn_auto_mode.569922342 Jun 07 09:36:54 PM PDT 24 Jun 07 10:13:10 PM PDT 24 7014714846 ps
T1105 /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.2692932824 Jun 07 09:52:03 PM PDT 24 Jun 07 10:01:34 PM PDT 24 6203450192 ps
T1106 /workspace/coverage/default/2.chip_sw_aon_timer_irq.940278921 Jun 07 09:56:51 PM PDT 24 Jun 07 10:04:07 PM PDT 24 4156059874 ps
T49 /workspace/coverage/default/2.chip_sw_spi_device_tpm.2396278923 Jun 07 09:54:28 PM PDT 24 Jun 07 10:00:23 PM PDT 24 3028490611 ps
T1107 /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.1066827908 Jun 07 09:48:50 PM PDT 24 Jun 07 09:57:14 PM PDT 24 3994347330 ps
T1108 /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.2294095714 Jun 07 09:56:36 PM PDT 24 Jun 07 10:07:05 PM PDT 24 5465031654 ps
T1109 /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.3499126822 Jun 07 10:08:39 PM PDT 24 Jun 07 10:16:38 PM PDT 24 3119514660 ps
T1110 /workspace/coverage/default/1.rom_e2e_smoke.1004229483 Jun 07 09:56:49 PM PDT 24 Jun 07 10:54:19 PM PDT 24 14199031928 ps
T1111 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.3123942422 Jun 07 09:58:26 PM PDT 24 Jun 07 10:10:27 PM PDT 24 9156385152 ps
T1112 /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.2749705259 Jun 07 10:01:29 PM PDT 24 Jun 07 10:12:17 PM PDT 24 4430243760 ps
T296 /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.967250600 Jun 07 09:46:15 PM PDT 24 Jun 07 09:53:15 PM PDT 24 3221799812 ps
T1113 /workspace/coverage/default/2.rom_e2e_asm_init_dev.3653443044 Jun 07 10:07:25 PM PDT 24 Jun 07 11:05:52 PM PDT 24 14966201482 ps
T153 /workspace/coverage/default/2.chip_plic_all_irqs_10.4091919301 Jun 07 09:59:19 PM PDT 24 Jun 07 10:09:33 PM PDT 24 4931399944 ps
T822 /workspace/coverage/default/98.chip_sw_all_escalation_resets.1606288878 Jun 07 10:16:16 PM PDT 24 Jun 07 10:25:54 PM PDT 24 6156704310 ps
T875 /workspace/coverage/default/85.chip_sw_all_escalation_resets.1489394132 Jun 07 10:15:34 PM PDT 24 Jun 07 10:25:39 PM PDT 24 4223833088 ps
T297 /workspace/coverage/default/0.chip_sw_data_integrity_escalation.3713496245 Jun 07 09:35:59 PM PDT 24 Jun 07 09:48:00 PM PDT 24 5761142408 ps
T1114 /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.891616052 Jun 07 09:43:31 PM PDT 24 Jun 07 10:05:35 PM PDT 24 6244307358 ps
T264 /workspace/coverage/default/1.chip_sw_power_sleep_load.3910945910 Jun 07 09:52:41 PM PDT 24 Jun 07 09:59:02 PM PDT 24 3631341328 ps
T1115 /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2934797325 Jun 07 10:03:59 PM PDT 24 Jun 07 10:10:53 PM PDT 24 7185368136 ps
T848 /workspace/coverage/default/18.chip_sw_all_escalation_resets.3808306033 Jun 07 10:10:15 PM PDT 24 Jun 07 10:21:19 PM PDT 24 4569567570 ps
T30 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.1331622271 Jun 07 09:44:22 PM PDT 24 Jun 07 10:42:24 PM PDT 24 20064253861 ps
T1116 /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.3571165753 Jun 07 09:55:34 PM PDT 24 Jun 07 10:05:03 PM PDT 24 3547153320 ps
T1117 /workspace/coverage/default/0.chip_sw_hmac_smoketest.208623218 Jun 07 09:42:00 PM PDT 24 Jun 07 09:49:52 PM PDT 24 3428995176 ps
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