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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.99 95.52 94.01 95.51 94.89 96.47 99.55


Total test records in report: 2887
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T1118 /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.25889200 Jun 07 09:40:26 PM PDT 24 Jun 07 09:47:25 PM PDT 24 6288690328 ps
T179 /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.670135637 Jun 07 10:01:15 PM PDT 24 Jun 07 10:06:16 PM PDT 24 3594339219 ps
T187 /workspace/coverage/default/0.chip_sw_spi_device_pass_through.829966600 Jun 07 09:36:40 PM PDT 24 Jun 07 09:51:04 PM PDT 24 7002044468 ps
T328 /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.751677869 Jun 07 10:15:35 PM PDT 24 Jun 07 10:21:53 PM PDT 24 3954630000 ps
T1119 /workspace/coverage/default/1.chip_tap_straps_dev.1447202058 Jun 07 09:53:05 PM PDT 24 Jun 07 09:57:04 PM PDT 24 4081970288 ps
T438 /workspace/coverage/default/1.chip_sw_kmac_app_rom.2220531649 Jun 07 09:50:58 PM PDT 24 Jun 07 09:54:14 PM PDT 24 2869139360 ps
T1120 /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.1976902460 Jun 07 09:41:28 PM PDT 24 Jun 07 09:51:07 PM PDT 24 3221979862 ps
T1121 /workspace/coverage/default/0.chip_sw_csrng_kat_test.1714066721 Jun 07 09:38:51 PM PDT 24 Jun 07 09:43:44 PM PDT 24 2880850880 ps
T162 /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.2644083328 Jun 07 09:56:22 PM PDT 24 Jun 07 10:00:06 PM PDT 24 2394594934 ps
T1122 /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.3531655705 Jun 07 09:46:28 PM PDT 24 Jun 07 09:51:31 PM PDT 24 3180935768 ps
T1123 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.739146495 Jun 07 09:46:19 PM PDT 24 Jun 07 10:26:27 PM PDT 24 10398352136 ps
T1124 /workspace/coverage/default/0.rom_e2e_asm_init_rma.263554131 Jun 07 09:44:33 PM PDT 24 Jun 07 10:42:35 PM PDT 24 14634014172 ps
T248 /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.307182956 Jun 07 09:43:03 PM PDT 24 Jun 07 11:12:50 PM PDT 24 49665182360 ps
T851 /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.1551695762 Jun 07 10:07:04 PM PDT 24 Jun 07 10:13:23 PM PDT 24 4053429416 ps
T242 /workspace/coverage/default/2.chip_sw_flash_init.1573919722 Jun 07 09:55:44 PM PDT 24 Jun 07 10:24:15 PM PDT 24 18749920896 ps
T369 /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3734241920 Jun 07 09:56:54 PM PDT 24 Jun 07 10:08:11 PM PDT 24 19887821424 ps
T1125 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.295800794 Jun 07 09:59:58 PM PDT 24 Jun 07 10:11:42 PM PDT 24 4968251530 ps
T1126 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.17604407 Jun 07 09:52:54 PM PDT 24 Jun 07 10:03:31 PM PDT 24 4177770600 ps
T1127 /workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.19076807 Jun 07 09:59:03 PM PDT 24 Jun 07 10:20:57 PM PDT 24 7674767040 ps
T1128 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.2068926065 Jun 07 09:44:26 PM PDT 24 Jun 07 10:29:08 PM PDT 24 11270110964 ps
T1129 /workspace/coverage/default/2.chip_sw_power_sleep_load.2077044508 Jun 07 10:02:27 PM PDT 24 Jun 07 10:10:36 PM PDT 24 9673401240 ps
T765 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.317532121 Jun 07 09:54:52 PM PDT 24 Jun 07 09:56:28 PM PDT 24 2317072591 ps
T1130 /workspace/coverage/default/0.rom_keymgr_functest.3298906744 Jun 07 09:43:27 PM PDT 24 Jun 07 09:52:47 PM PDT 24 4941538488 ps
T1131 /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.2293086370 Jun 07 09:43:40 PM PDT 24 Jun 07 09:53:37 PM PDT 24 4923672000 ps
T1132 /workspace/coverage/default/0.chip_sw_aes_masking_off.3550544228 Jun 07 09:38:43 PM PDT 24 Jun 07 09:44:29 PM PDT 24 3169172058 ps
T298 /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.1464943088 Jun 07 09:58:36 PM PDT 24 Jun 07 10:07:21 PM PDT 24 3278820140 ps
T299 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.3885530875 Jun 07 09:59:15 PM PDT 24 Jun 07 10:09:07 PM PDT 24 4261899010 ps
T246 /workspace/coverage/default/0.chip_sw_flash_init.737653429 Jun 07 09:35:55 PM PDT 24 Jun 07 10:18:13 PM PDT 24 18209081200 ps
T1133 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.4040230339 Jun 07 09:42:59 PM PDT 24 Jun 07 09:53:42 PM PDT 24 4526950400 ps
T1134 /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.3682567602 Jun 07 10:04:46 PM PDT 24 Jun 07 10:14:04 PM PDT 24 6520737784 ps
T1135 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3073161208 Jun 07 09:42:31 PM PDT 24 Jun 07 09:53:42 PM PDT 24 4671645100 ps
T1136 /workspace/coverage/default/0.chip_sw_kmac_idle.2449584504 Jun 07 09:38:36 PM PDT 24 Jun 07 09:43:55 PM PDT 24 2979039108 ps
T1137 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.463932754 Jun 07 10:02:01 PM PDT 24 Jun 07 10:06:16 PM PDT 24 3100679582 ps
T1138 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.2525017201 Jun 07 09:56:06 PM PDT 24 Jun 07 10:07:51 PM PDT 24 4004856864 ps
T1139 /workspace/coverage/default/1.chip_sw_otbn_randomness.3886449503 Jun 07 09:43:49 PM PDT 24 Jun 07 10:00:38 PM PDT 24 6202174800 ps
T813 /workspace/coverage/default/2.chip_sw_pattgen_ios.3587791549 Jun 07 09:53:57 PM PDT 24 Jun 07 09:59:42 PM PDT 24 2947892096 ps
T1140 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.2046740579 Jun 07 09:51:49 PM PDT 24 Jun 07 10:04:19 PM PDT 24 7139375688 ps
T766 /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.3853851201 Jun 07 09:37:12 PM PDT 24 Jun 07 09:42:16 PM PDT 24 2989038490 ps
T1141 /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.3759599990 Jun 07 09:55:39 PM PDT 24 Jun 07 10:02:34 PM PDT 24 3798119886 ps
T1142 /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.1384068281 Jun 07 09:42:52 PM PDT 24 Jun 07 09:47:18 PM PDT 24 3268368288 ps
T838 /workspace/coverage/default/22.chip_sw_all_escalation_resets.2036124490 Jun 07 10:08:57 PM PDT 24 Jun 07 10:19:58 PM PDT 24 5219531584 ps
T1143 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3691378859 Jun 07 10:02:52 PM PDT 24 Jun 07 10:21:35 PM PDT 24 7115966133 ps
T869 /workspace/coverage/default/41.chip_sw_all_escalation_resets.1994801414 Jun 07 10:10:26 PM PDT 24 Jun 07 10:18:37 PM PDT 24 4716395240 ps
T1144 /workspace/coverage/default/0.chip_sw_uart_smoketest.23733104 Jun 07 09:41:28 PM PDT 24 Jun 07 09:45:32 PM PDT 24 3321780548 ps
T908 /workspace/coverage/default/43.chip_sw_all_escalation_resets.1502619560 Jun 07 10:10:19 PM PDT 24 Jun 07 10:20:22 PM PDT 24 5317814150 ps
T397 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.2362761872 Jun 07 09:42:29 PM PDT 24 Jun 07 09:56:48 PM PDT 24 5134505400 ps
T1145 /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.293176331 Jun 07 09:39:19 PM PDT 24 Jun 07 09:49:24 PM PDT 24 4265651310 ps
T1146 /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.3410131783 Jun 07 10:08:25 PM PDT 24 Jun 07 10:21:06 PM PDT 24 9774082097 ps
T31 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.1640233801 Jun 07 09:43:42 PM PDT 24 Jun 07 10:13:00 PM PDT 24 24501754960 ps
T1147 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.3730887202 Jun 07 09:51:29 PM PDT 24 Jun 07 09:57:10 PM PDT 24 3030256402 ps
T219 /workspace/coverage/default/2.chip_sw_inject_scramble_seed.2010039095 Jun 07 09:55:59 PM PDT 24 Jun 08 01:29:30 AM PDT 24 65425226354 ps
T154 /workspace/coverage/default/0.chip_plic_all_irqs_10.4055430973 Jun 07 09:38:57 PM PDT 24 Jun 07 09:48:43 PM PDT 24 4168849472 ps
T1148 /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.1900991228 Jun 07 09:43:21 PM PDT 24 Jun 07 09:48:59 PM PDT 24 6722065340 ps
T896 /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.34444850 Jun 07 10:14:06 PM PDT 24 Jun 07 10:20:15 PM PDT 24 3291526040 ps
T1149 /workspace/coverage/default/1.chip_sw_inject_scramble_seed.2893173392 Jun 07 09:40:04 PM PDT 24 Jun 08 12:55:39 AM PDT 24 64524855185 ps
T1150 /workspace/coverage/default/2.chip_sw_example_flash.544049358 Jun 07 09:52:58 PM PDT 24 Jun 07 09:56:36 PM PDT 24 3343288474 ps
T1151 /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3181669926 Jun 07 10:14:33 PM PDT 24 Jun 07 10:21:52 PM PDT 24 3697877980 ps
T1152 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.597567284 Jun 07 09:46:46 PM PDT 24 Jun 07 10:21:35 PM PDT 24 10727018769 ps
T906 /workspace/coverage/default/69.chip_sw_all_escalation_resets.1252009549 Jun 07 10:13:42 PM PDT 24 Jun 07 10:23:06 PM PDT 24 5109519910 ps
T14 /workspace/coverage/default/2.chip_sw_sleep_pin_wake.1741724445 Jun 07 09:54:25 PM PDT 24 Jun 07 10:01:38 PM PDT 24 5512944152 ps
T1153 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.1995830077 Jun 07 09:55:48 PM PDT 24 Jun 07 10:18:05 PM PDT 24 7941942440 ps
T1154 /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.3355338517 Jun 07 09:55:05 PM PDT 24 Jun 07 10:01:47 PM PDT 24 3304522846 ps
T1155 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.3737315255 Jun 07 09:43:28 PM PDT 24 Jun 07 09:52:40 PM PDT 24 8828584960 ps
T1156 /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.2824645972 Jun 07 10:06:30 PM PDT 24 Jun 07 10:19:56 PM PDT 24 10057943683 ps
T1157 /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.179325604 Jun 07 10:06:20 PM PDT 24 Jun 07 10:11:33 PM PDT 24 2873043812 ps
T1158 /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.4141777302 Jun 07 10:06:17 PM PDT 24 Jun 07 10:11:48 PM PDT 24 3108900888 ps
T1159 /workspace/coverage/default/0.chip_sw_clkmgr_jitter.3286618824 Jun 07 09:40:33 PM PDT 24 Jun 07 09:43:45 PM PDT 24 2495399812 ps
T757 /workspace/coverage/default/1.chip_sw_edn_boot_mode.3855203858 Jun 07 09:45:47 PM PDT 24 Jun 07 09:55:43 PM PDT 24 2768028088 ps
T64 /workspace/coverage/default/0.chip_tap_straps_rma.2824247633 Jun 07 09:38:54 PM PDT 24 Jun 07 09:42:22 PM PDT 24 3149520175 ps
T1160 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.3151746865 Jun 07 09:37:19 PM PDT 24 Jun 07 09:42:06 PM PDT 24 2914961774 ps
T1161 /workspace/coverage/default/0.chip_sw_usbdev_stream.362484218 Jun 07 09:35:03 PM PDT 24 Jun 07 10:47:42 PM PDT 24 19982237764 ps
T300 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.3756054535 Jun 07 09:48:11 PM PDT 24 Jun 07 09:57:54 PM PDT 24 3250088256 ps
T1162 /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.2889665221 Jun 07 09:57:57 PM PDT 24 Jun 07 10:29:34 PM PDT 24 8576320232 ps
T1163 /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.589615412 Jun 07 10:08:16 PM PDT 24 Jun 07 10:15:45 PM PDT 24 3992072568 ps
T1164 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.4200463648 Jun 07 09:41:20 PM PDT 24 Jun 07 09:45:06 PM PDT 24 3264051573 ps
T1165 /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.3215742068 Jun 07 10:06:36 PM PDT 24 Jun 07 10:14:17 PM PDT 24 5400461949 ps
T1166 /workspace/coverage/default/1.rom_e2e_asm_init_rma.2444477828 Jun 07 09:57:55 PM PDT 24 Jun 07 10:57:26 PM PDT 24 13858331344 ps
T884 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.1402020442 Jun 07 09:47:32 PM PDT 24 Jun 07 09:53:58 PM PDT 24 4227792552 ps
T71 /workspace/coverage/default/0.chip_sw_usbdev_pincfg.1177703228 Jun 07 09:37:25 PM PDT 24 Jun 07 11:30:21 PM PDT 24 31403936910 ps
T1167 /workspace/coverage/default/0.chip_sw_rv_timer_irq.1715589987 Jun 07 09:37:04 PM PDT 24 Jun 07 09:42:17 PM PDT 24 3315225804 ps
T32 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.1476877184 Jun 07 09:38:04 PM PDT 24 Jun 07 10:07:16 PM PDT 24 20970928816 ps
T1168 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.441481090 Jun 07 09:42:29 PM PDT 24 Jun 07 09:51:23 PM PDT 24 3712496889 ps
T271 /workspace/coverage/default/0.rom_e2e_jtag_debug_rma.2930250538 Jun 07 09:41:23 PM PDT 24 Jun 07 10:27:00 PM PDT 24 12775891720 ps
T1169 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.333580584 Jun 07 09:54:28 PM PDT 24 Jun 07 10:12:46 PM PDT 24 5503372491 ps
T1170 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.796342957 Jun 07 10:00:59 PM PDT 24 Jun 07 10:08:53 PM PDT 24 3756164660 ps
T864 /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.2456004805 Jun 07 10:13:07 PM PDT 24 Jun 07 10:18:45 PM PDT 24 3558476600 ps
T1171 /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.3897021333 Jun 07 09:43:10 PM PDT 24 Jun 07 09:49:44 PM PDT 24 4243520310 ps
T1172 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.4030954584 Jun 07 10:00:22 PM PDT 24 Jun 07 10:13:15 PM PDT 24 4372750758 ps
T329 /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.1750136026 Jun 07 10:11:48 PM PDT 24 Jun 07 10:17:58 PM PDT 24 4254515000 ps
T1173 /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.576253027 Jun 07 09:43:18 PM PDT 24 Jun 07 09:46:53 PM PDT 24 2065781096 ps
T1174 /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2208568872 Jun 07 10:14:43 PM PDT 24 Jun 07 10:21:23 PM PDT 24 3579626418 ps
T1175 /workspace/coverage/default/2.chip_sw_aes_idle.4127078388 Jun 07 09:58:05 PM PDT 24 Jun 07 10:02:07 PM PDT 24 3312847408 ps
T1176 /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.2736247229 Jun 07 09:56:23 PM PDT 24 Jun 07 10:14:54 PM PDT 24 10956647503 ps
T1177 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.1965527477 Jun 07 09:46:06 PM PDT 24 Jun 07 10:01:53 PM PDT 24 4662323046 ps
T1178 /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.1663024109 Jun 07 09:38:55 PM PDT 24 Jun 07 09:45:13 PM PDT 24 2903833176 ps
T1179 /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.540304200 Jun 07 09:53:05 PM PDT 24 Jun 07 10:18:04 PM PDT 24 8693617600 ps
T1180 /workspace/coverage/default/0.chip_sw_example_manufacturer.4129769824 Jun 07 09:35:56 PM PDT 24 Jun 07 09:39:16 PM PDT 24 2413201644 ps
T1181 /workspace/coverage/default/0.chip_sw_example_rom.4060783379 Jun 07 09:34:47 PM PDT 24 Jun 07 09:37:08 PM PDT 24 2312285080 ps
T1182 /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.612736056 Jun 07 09:39:25 PM PDT 24 Jun 07 10:12:28 PM PDT 24 28664586614 ps
T1183 /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.637583788 Jun 07 09:57:06 PM PDT 24 Jun 07 10:01:07 PM PDT 24 2665596008 ps
T1184 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.3251685990 Jun 07 10:05:58 PM PDT 24 Jun 07 10:59:43 PM PDT 24 14494012608 ps
T1185 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.1481165139 Jun 07 09:59:43 PM PDT 24 Jun 07 10:27:28 PM PDT 24 8519528856 ps
T1186 /workspace/coverage/default/2.rom_e2e_shutdown_output.4145649925 Jun 07 10:07:35 PM PDT 24 Jun 07 10:58:41 PM PDT 24 28972173608 ps
T1187 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.2955131964 Jun 07 09:54:42 PM PDT 24 Jun 07 10:07:37 PM PDT 24 4503192632 ps
T1188 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.1735326590 Jun 07 09:45:39 PM PDT 24 Jun 07 10:46:26 PM PDT 24 14058451805 ps
T1189 /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.2116635764 Jun 07 09:54:17 PM PDT 24 Jun 07 09:59:54 PM PDT 24 2370520582 ps
T1190 /workspace/coverage/default/2.chip_sw_flash_crash_alert.3325076869 Jun 07 10:01:39 PM PDT 24 Jun 07 10:11:55 PM PDT 24 5313036300 ps
T1191 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.2377807951 Jun 07 09:46:11 PM PDT 24 Jun 07 09:50:35 PM PDT 24 2906635925 ps
T892 /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.792024191 Jun 07 10:06:35 PM PDT 24 Jun 07 10:13:10 PM PDT 24 3253640164 ps
T221 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.4256186597 Jun 07 09:45:20 PM PDT 24 Jun 07 10:46:17 PM PDT 24 19962386822 ps
T1192 /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.2847585032 Jun 07 09:37:45 PM PDT 24 Jun 07 09:42:47 PM PDT 24 3341975510 ps
T301 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.1552831376 Jun 07 09:47:28 PM PDT 24 Jun 07 09:58:53 PM PDT 24 5595407844 ps
T1193 /workspace/coverage/default/1.rom_e2e_shutdown_output.311002352 Jun 07 09:57:51 PM PDT 24 Jun 07 10:34:02 PM PDT 24 20181576324 ps
T58 /workspace/coverage/default/2.chip_sw_alert_test.3726400253 Jun 07 09:58:13 PM PDT 24 Jun 07 10:04:50 PM PDT 24 3722182764 ps
T895 /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.1486735542 Jun 07 10:10:17 PM PDT 24 Jun 07 10:16:47 PM PDT 24 3707724902 ps
T37 /workspace/coverage/default/0.chip_sw_gpio.725347714 Jun 07 09:37:03 PM PDT 24 Jun 07 09:46:13 PM PDT 24 3425303380 ps
T852 /workspace/coverage/default/9.chip_sw_all_escalation_resets.334933546 Jun 07 10:08:34 PM PDT 24 Jun 07 10:20:42 PM PDT 24 6298493564 ps
T1194 /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.2023763576 Jun 07 09:45:22 PM PDT 24 Jun 07 09:49:09 PM PDT 24 2470692620 ps
T767 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.4248282247 Jun 07 09:44:00 PM PDT 24 Jun 07 09:45:58 PM PDT 24 2594905194 ps
T372 /workspace/coverage/default/2.chip_sw_hmac_enc.1405093567 Jun 07 09:58:32 PM PDT 24 Jun 07 10:03:30 PM PDT 24 3081963640 ps
T1195 /workspace/coverage/default/2.chip_sw_alert_handler_entropy.210901703 Jun 07 09:57:24 PM PDT 24 Jun 07 10:03:57 PM PDT 24 3268932762 ps
T1196 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3207843184 Jun 07 09:49:49 PM PDT 24 Jun 07 10:00:55 PM PDT 24 3795087808 ps
T1197 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.342593373 Jun 07 09:55:37 PM PDT 24 Jun 07 10:12:16 PM PDT 24 9077061032 ps
T1198 /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.4194290675 Jun 07 09:58:53 PM PDT 24 Jun 07 10:02:22 PM PDT 24 2379707196 ps
T1199 /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.147827366 Jun 07 10:14:23 PM PDT 24 Jun 07 10:19:20 PM PDT 24 3799659576 ps
T1200 /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.3025471784 Jun 07 10:05:53 PM PDT 24 Jun 07 11:02:31 PM PDT 24 14421868788 ps
T901 /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2495027371 Jun 07 10:15:05 PM PDT 24 Jun 07 10:21:31 PM PDT 24 3560616024 ps
T1201 /workspace/coverage/default/4.chip_tap_straps_testunlock0.1672678361 Jun 07 10:04:12 PM PDT 24 Jun 07 10:13:30 PM PDT 24 6027595820 ps
T151 /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.747458174 Jun 07 09:36:54 PM PDT 24 Jun 08 12:23:04 AM PDT 24 59431099835 ps
T1202 /workspace/coverage/default/0.chip_sw_usbdev_vbus.3559427482 Jun 07 09:36:31 PM PDT 24 Jun 07 09:40:46 PM PDT 24 3467861030 ps
T272 /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3992911952 Jun 07 09:39:47 PM PDT 24 Jun 07 09:46:38 PM PDT 24 3929091512 ps
T1203 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.1341082802 Jun 07 10:08:34 PM PDT 24 Jun 07 10:31:32 PM PDT 24 8502541057 ps
T887 /workspace/coverage/default/92.chip_sw_all_escalation_resets.486555341 Jun 07 10:15:09 PM PDT 24 Jun 07 10:25:12 PM PDT 24 5986782692 ps
T202 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.2469462014 Jun 07 09:37:10 PM PDT 24 Jun 07 09:43:19 PM PDT 24 3696937405 ps
T1204 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1499328171 Jun 07 09:37:46 PM PDT 24 Jun 07 09:39:39 PM PDT 24 2508825365 ps
T1205 /workspace/coverage/default/2.rom_volatile_raw_unlock.4255736230 Jun 07 10:04:16 PM PDT 24 Jun 07 10:06:05 PM PDT 24 2222184828 ps
T277 /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.1871970863 Jun 07 09:43:17 PM PDT 24 Jun 07 09:55:59 PM PDT 24 7320959702 ps
T1206 /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.3846602723 Jun 07 09:58:24 PM PDT 24 Jun 07 10:14:58 PM PDT 24 6020857830 ps
T902 /workspace/coverage/default/48.chip_sw_all_escalation_resets.1349312755 Jun 07 10:11:16 PM PDT 24 Jun 07 10:22:10 PM PDT 24 6378531440 ps
T1207 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.3672041737 Jun 07 09:36:18 PM PDT 24 Jun 07 09:38:01 PM PDT 24 2846303514 ps
T876 /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.30037830 Jun 07 10:12:32 PM PDT 24 Jun 07 10:18:39 PM PDT 24 3830830628 ps
T1208 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.1591157528 Jun 07 09:45:09 PM PDT 24 Jun 07 11:21:26 PM PDT 24 21670992688 ps
T243 /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.1187981746 Jun 07 09:54:40 PM PDT 24 Jun 07 10:07:06 PM PDT 24 4964805416 ps
T1209 /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.857624192 Jun 07 10:08:07 PM PDT 24 Jun 07 10:14:25 PM PDT 24 4361808468 ps
T1210 /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.1557160275 Jun 07 09:54:28 PM PDT 24 Jun 07 10:35:21 PM PDT 24 29696340031 ps
T1211 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.3066791996 Jun 07 09:46:20 PM PDT 24 Jun 07 10:46:19 PM PDT 24 14730486140 ps
T893 /workspace/coverage/default/34.chip_sw_all_escalation_resets.804719713 Jun 07 10:09:53 PM PDT 24 Jun 07 10:21:40 PM PDT 24 5341951720 ps
T1212 /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.1613013183 Jun 07 09:44:12 PM PDT 24 Jun 07 09:47:24 PM PDT 24 2275518792 ps
T1213 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.3748976211 Jun 07 09:58:09 PM PDT 24 Jun 07 10:19:47 PM PDT 24 7162463756 ps
T1214 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.4146741975 Jun 07 09:44:38 PM PDT 24 Jun 07 09:53:39 PM PDT 24 7235901452 ps
T244 /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.742780942 Jun 07 09:42:40 PM PDT 24 Jun 07 11:13:56 PM PDT 24 47823393204 ps
T758 /workspace/coverage/default/0.chip_sw_edn_boot_mode.181260829 Jun 07 09:38:41 PM PDT 24 Jun 07 09:48:22 PM PDT 24 3461755184 ps
T1215 /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.1646300955 Jun 07 10:08:30 PM PDT 24 Jun 07 10:16:55 PM PDT 24 5307405371 ps
T1216 /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.3157472270 Jun 07 10:04:02 PM PDT 24 Jun 07 10:08:11 PM PDT 24 3476681164 ps
T888 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.3281094979 Jun 07 09:38:07 PM PDT 24 Jun 07 09:44:25 PM PDT 24 3802239220 ps
T87 /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.1729540562 Jun 07 10:11:13 PM PDT 24 Jun 07 10:18:35 PM PDT 24 4193214820 ps
T50 /workspace/coverage/default/1.chip_sw_spi_device_tpm.3441817640 Jun 07 09:41:43 PM PDT 24 Jun 07 09:48:02 PM PDT 24 4093029828 ps
T273 /workspace/coverage/default/0.rom_e2e_jtag_debug_dev.3404090011 Jun 07 09:39:48 PM PDT 24 Jun 07 10:21:26 PM PDT 24 13705016546 ps
T1217 /workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.2056630646 Jun 07 10:08:56 PM PDT 24 Jun 07 11:07:42 PM PDT 24 17545721016 ps
T1218 /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.3228634505 Jun 07 10:04:23 PM PDT 24 Jun 07 10:09:40 PM PDT 24 2497564192 ps
T1219 /workspace/coverage/default/1.chip_sw_example_rom.1423243932 Jun 07 09:44:50 PM PDT 24 Jun 07 09:47:01 PM PDT 24 1743299960 ps
T1220 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2875793877 Jun 07 09:56:41 PM PDT 24 Jun 07 10:10:30 PM PDT 24 4924728270 ps
T1221 /workspace/coverage/default/52.chip_sw_all_escalation_resets.1156553754 Jun 07 10:12:54 PM PDT 24 Jun 07 10:21:32 PM PDT 24 5354777036 ps
T1222 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.3105161374 Jun 07 09:46:23 PM PDT 24 Jun 07 10:02:00 PM PDT 24 6816273523 ps
T1223 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.2709912265 Jun 07 09:38:04 PM PDT 24 Jun 07 09:53:18 PM PDT 24 5440712488 ps
T261 /workspace/coverage/default/72.chip_sw_all_escalation_resets.1626840150 Jun 07 10:13:21 PM PDT 24 Jun 07 10:19:44 PM PDT 24 4688165336 ps
T1224 /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.2918929708 Jun 07 09:37:24 PM PDT 24 Jun 07 09:40:33 PM PDT 24 2884196268 ps
T1225 /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.1199895854 Jun 07 09:37:51 PM PDT 24 Jun 07 09:47:45 PM PDT 24 5085433392 ps
T1226 /workspace/coverage/default/1.chip_sw_otbn_smoketest.4120571777 Jun 07 09:53:18 PM PDT 24 Jun 07 10:23:16 PM PDT 24 8465146416 ps
T1227 /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.3454018710 Jun 07 10:08:48 PM PDT 24 Jun 07 10:14:43 PM PDT 24 3510967044 ps
T241 /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.4205193599 Jun 07 09:40:58 PM PDT 24 Jun 07 10:19:30 PM PDT 24 26343189965 ps
T1228 /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.976544390 Jun 07 09:40:34 PM PDT 24 Jun 08 12:54:31 AM PDT 24 255345619588 ps
T1229 /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.1519355263 Jun 07 10:02:21 PM PDT 24 Jun 07 10:24:50 PM PDT 24 11000747480 ps
T180 /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.553102009 Jun 07 09:36:33 PM PDT 24 Jun 07 11:06:36 PM PDT 24 43469100932 ps
T409 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1574371494 Jun 07 10:01:07 PM PDT 24 Jun 07 10:08:26 PM PDT 24 7338479304 ps
T141 /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.54614142 Jun 07 09:37:07 PM PDT 24 Jun 07 09:45:22 PM PDT 24 6866207588 ps
T203 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.3706070877 Jun 07 09:56:48 PM PDT 24 Jun 07 10:27:49 PM PDT 24 23973432428 ps
T759 /workspace/coverage/default/2.chip_sw_edn_boot_mode.281050754 Jun 07 09:58:22 PM PDT 24 Jun 07 10:08:15 PM PDT 24 3008379512 ps
T1230 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.2229382343 Jun 07 09:47:25 PM PDT 24 Jun 07 11:02:09 PM PDT 24 14216682450 ps
T1231 /workspace/coverage/default/0.chip_sw_kmac_app_rom.4134550317 Jun 07 09:40:38 PM PDT 24 Jun 07 09:45:43 PM PDT 24 2990284456 ps
T1232 /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.490088636 Jun 07 10:08:38 PM PDT 24 Jun 07 10:23:31 PM PDT 24 9785146254 ps
T886 /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.2329740835 Jun 07 10:15:23 PM PDT 24 Jun 07 10:22:07 PM PDT 24 4050998784 ps
T1233 /workspace/coverage/default/0.chip_sw_flash_ctrl_access.2462652870 Jun 07 09:37:34 PM PDT 24 Jun 07 09:56:17 PM PDT 24 5608150904 ps
T1234 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2955025180 Jun 07 09:56:33 PM PDT 24 Jun 07 10:06:05 PM PDT 24 7133637584 ps
T789 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.4095209763 Jun 07 09:57:54 PM PDT 24 Jun 07 10:02:08 PM PDT 24 2848013284 ps
T20 /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.701229475 Jun 07 09:57:07 PM PDT 24 Jun 07 10:03:02 PM PDT 24 3557499238 ps
T1235 /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.450647747 Jun 07 10:13:17 PM PDT 24 Jun 07 10:21:18 PM PDT 24 4038254612 ps
T1236 /workspace/coverage/default/3.chip_tap_straps_prod.4250214267 Jun 07 10:04:26 PM PDT 24 Jun 07 10:31:58 PM PDT 24 15559635388 ps
T1237 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2044789968 Jun 07 09:52:26 PM PDT 24 Jun 07 09:58:36 PM PDT 24 3362717216 ps
T1238 /workspace/coverage/default/1.chip_sw_gpio_smoketest.4082678239 Jun 07 09:54:07 PM PDT 24 Jun 07 09:58:27 PM PDT 24 2957716791 ps
T204 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.3440013065 Jun 07 09:43:32 PM PDT 24 Jun 07 09:49:18 PM PDT 24 3375999666 ps
T1239 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.3782163614 Jun 07 09:46:27 PM PDT 24 Jun 07 11:36:09 PM PDT 24 22127607138 ps
T72 /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.1238575739 Jun 07 09:37:10 PM PDT 24 Jun 07 09:44:29 PM PDT 24 4000023658 ps
T1240 /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.3466677846 Jun 07 09:45:24 PM PDT 24 Jun 07 09:53:31 PM PDT 24 9545004306 ps
T1241 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.3347222903 Jun 07 10:08:40 PM PDT 24 Jun 07 10:40:33 PM PDT 24 8758807529 ps
T1242 /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.672689285 Jun 07 10:07:05 PM PDT 24 Jun 07 10:19:04 PM PDT 24 4559350496 ps
T1243 /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.2032942444 Jun 07 10:08:17 PM PDT 24 Jun 07 10:21:47 PM PDT 24 9124750581 ps
T1244 /workspace/coverage/default/1.rom_e2e_asm_init_dev.3471329782 Jun 07 09:55:42 PM PDT 24 Jun 07 11:01:05 PM PDT 24 14844038023 ps
T1245 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.2537352430 Jun 07 09:38:59 PM PDT 24 Jun 07 10:02:32 PM PDT 24 12863261984 ps
T856 /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.1737506660 Jun 07 10:10:35 PM PDT 24 Jun 07 10:17:52 PM PDT 24 3666258072 ps
T857 /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.1805309177 Jun 07 10:11:21 PM PDT 24 Jun 07 10:17:45 PM PDT 24 4089871874 ps
T1246 /workspace/coverage/default/1.chip_sw_aes_entropy.2844512471 Jun 07 09:47:13 PM PDT 24 Jun 07 09:52:42 PM PDT 24 3668664620 ps
T1247 /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.329845511 Jun 07 09:53:28 PM PDT 24 Jun 07 09:59:39 PM PDT 24 3399952510 ps
T245 /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.3492426630 Jun 07 09:54:56 PM PDT 24 Jun 07 11:16:26 PM PDT 24 47830788980 ps
T1248 /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.3067711702 Jun 07 09:42:44 PM PDT 24 Jun 07 10:21:33 PM PDT 24 27619672712 ps
T1249 /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.1349680128 Jun 07 09:59:52 PM PDT 24 Jun 07 10:32:54 PM PDT 24 28299549198 ps
T353 /workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.2143904909 Jun 07 09:59:56 PM PDT 24 Jun 07 10:09:19 PM PDT 24 4067848396 ps
T853 /workspace/coverage/default/33.chip_sw_all_escalation_resets.1950095972 Jun 07 10:10:44 PM PDT 24 Jun 07 10:26:05 PM PDT 24 5669433416 ps
T826 /workspace/coverage/default/32.chip_sw_all_escalation_resets.3225022046 Jun 07 10:10:02 PM PDT 24 Jun 07 10:20:19 PM PDT 24 4522778700 ps
T819 /workspace/coverage/default/79.chip_sw_all_escalation_resets.1257983273 Jun 07 10:13:54 PM PDT 24 Jun 07 10:23:05 PM PDT 24 4991769060 ps
T265 /workspace/coverage/default/0.chip_sw_power_sleep_load.637758690 Jun 07 09:37:56 PM PDT 24 Jun 07 09:46:19 PM PDT 24 4891254752 ps
T373 /workspace/coverage/default/0.chip_sw_hmac_enc.1735530049 Jun 07 09:49:12 PM PDT 24 Jun 07 09:54:19 PM PDT 24 3090679088 ps
T1250 /workspace/coverage/default/2.rom_e2e_smoke.1648031433 Jun 07 10:10:16 PM PDT 24 Jun 07 11:02:54 PM PDT 24 14003626132 ps
T188 /workspace/coverage/default/2.chip_sw_spi_device_pass_through.3569162431 Jun 07 09:56:02 PM PDT 24 Jun 07 10:07:22 PM PDT 24 5541313834 ps
T1251 /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.4087287950 Jun 07 09:44:24 PM PDT 24 Jun 07 10:13:43 PM PDT 24 10040016043 ps
T1252 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.3329123241 Jun 07 09:43:31 PM PDT 24 Jun 07 10:40:51 PM PDT 24 13717559560 ps
T392 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.625257720 Jun 07 09:48:18 PM PDT 24 Jun 07 11:20:04 PM PDT 24 22520327412 ps
T1253 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.1712381728 Jun 07 10:01:29 PM PDT 24 Jun 07 10:27:18 PM PDT 24 6848582458 ps
T393 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.2364688614 Jun 07 09:45:48 PM PDT 24 Jun 07 11:24:58 PM PDT 24 22851625800 ps
T1254 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1181984757 Jun 07 09:39:49 PM PDT 24 Jun 07 10:21:54 PM PDT 24 23966222228 ps
T1255 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.1705251218 Jun 07 10:04:50 PM PDT 24 Jun 07 10:15:17 PM PDT 24 4096005568 ps
T249 /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.2761415726 Jun 07 09:36:16 PM PDT 24 Jun 07 11:05:17 PM PDT 24 47390864730 ps
T1256 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1751832637 Jun 07 09:39:18 PM PDT 24 Jun 07 10:04:12 PM PDT 24 9268317623 ps
T315 /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.196347483 Jun 07 09:40:02 PM PDT 24 Jun 07 09:46:00 PM PDT 24 3350581050 ps
T1257 /workspace/coverage/default/1.chip_sw_aes_enc.2948196475 Jun 07 09:46:18 PM PDT 24 Jun 07 09:52:16 PM PDT 24 2727652240 ps
T285 /workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.2154201411 Jun 07 09:50:50 PM PDT 24 Jun 07 09:55:46 PM PDT 24 2434069750 ps
T1258 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2579130228 Jun 07 09:56:58 PM PDT 24 Jun 07 10:54:49 PM PDT 24 43250114539 ps
T233 /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.837301332 Jun 07 09:48:21 PM PDT 24 Jun 07 10:18:09 PM PDT 24 8769222850 ps
T1259 /workspace/coverage/default/4.chip_sw_data_integrity_escalation.3910291965 Jun 07 10:04:55 PM PDT 24 Jun 07 10:20:14 PM PDT 24 6527084168 ps
T1260 /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.3435805845 Jun 07 09:39:27 PM PDT 24 Jun 07 09:43:46 PM PDT 24 2282198076 ps
T1261 /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.782055308 Jun 07 09:41:21 PM PDT 24 Jun 07 09:51:51 PM PDT 24 18531200968 ps
T1262 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.2333571242 Jun 07 09:47:51 PM PDT 24 Jun 07 09:58:21 PM PDT 24 6080716680 ps
T903 /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.2134570775 Jun 07 10:15:43 PM PDT 24 Jun 07 10:23:08 PM PDT 24 3538954202 ps
T1263 /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.1107584811 Jun 07 10:06:06 PM PDT 24 Jun 07 11:00:06 PM PDT 24 11505837472 ps
T1264 /workspace/coverage/default/1.chip_sw_hmac_enc_idle.2376778133 Jun 07 09:47:49 PM PDT 24 Jun 07 09:52:29 PM PDT 24 3549925550 ps
T1265 /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.4052440254 Jun 07 09:59:32 PM PDT 24 Jun 07 10:09:31 PM PDT 24 4741956144 ps
T1266 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3341346148 Jun 07 10:02:34 PM PDT 24 Jun 07 10:11:04 PM PDT 24 4663696980 ps
T1267 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.1309983831 Jun 07 09:46:04 PM PDT 24 Jun 07 10:51:04 PM PDT 24 17353418360 ps
T1268 /workspace/coverage/default/1.chip_sw_flash_init.2682002658 Jun 07 09:43:49 PM PDT 24 Jun 07 10:11:59 PM PDT 24 16910937920 ps
T222 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.345301583 Jun 07 09:56:26 PM PDT 24 Jun 07 10:51:09 PM PDT 24 20829711904 ps
T1269 /workspace/coverage/default/0.rom_e2e_smoke.250201385 Jun 07 09:42:24 PM PDT 24 Jun 07 10:41:39 PM PDT 24 14390252968 ps
T1270 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.3816881636 Jun 07 09:38:30 PM PDT 24 Jun 07 09:46:01 PM PDT 24 3511657458 ps
T1271 /workspace/coverage/default/0.chip_sw_hmac_multistream.2532969913 Jun 07 09:39:23 PM PDT 24 Jun 07 10:03:59 PM PDT 24 6212528920 ps
T1272 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.4240717221 Jun 07 10:06:52 PM PDT 24 Jun 07 11:11:59 PM PDT 24 15942125940 ps
T1273 /workspace/coverage/default/47.chip_sw_all_escalation_resets.4268888137 Jun 07 10:10:24 PM PDT 24 Jun 07 10:22:19 PM PDT 24 4773327316 ps
T1274 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.3246884662 Jun 07 09:44:43 PM PDT 24 Jun 07 10:41:11 PM PDT 24 14257396074 ps
T1275 /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.2999805031 Jun 07 09:48:18 PM PDT 24 Jun 07 09:54:53 PM PDT 24 3657436850 ps
T236 /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.157762243 Jun 07 09:50:47 PM PDT 24 Jun 07 11:18:28 PM PDT 24 16047480120 ps
T88 /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.1334577008 Jun 07 10:11:10 PM PDT 24 Jun 07 10:20:36 PM PDT 24 4316504200 ps
T1276 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.1276082679 Jun 07 09:49:38 PM PDT 24 Jun 07 09:59:18 PM PDT 24 5009091965 ps
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