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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.99 95.52 94.01 95.51 94.89 96.47 99.55


Total test records in report: 2887
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T1277 /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.3726172186 Jun 07 10:05:20 PM PDT 24 Jun 07 10:14:00 PM PDT 24 5956483427 ps
T1278 /workspace/coverage/default/1.chip_sw_hmac_enc.4148834193 Jun 07 09:47:09 PM PDT 24 Jun 07 09:52:10 PM PDT 24 2634332248 ps
T237 /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.244900176 Jun 07 10:00:31 PM PDT 24 Jun 07 11:00:43 PM PDT 24 16870683624 ps
T1279 /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.927880982 Jun 07 10:08:17 PM PDT 24 Jun 07 10:13:42 PM PDT 24 4025619128 ps
T894 /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.75577760 Jun 07 10:11:15 PM PDT 24 Jun 07 10:19:16 PM PDT 24 3644901800 ps
T1280 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.1833631616 Jun 07 09:43:10 PM PDT 24 Jun 07 09:52:47 PM PDT 24 7297726549 ps
T1281 /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.2280619292 Jun 07 09:52:03 PM PDT 24 Jun 07 10:14:31 PM PDT 24 5210571100 ps
T1282 /workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.3696308267 Jun 07 10:05:19 PM PDT 24 Jun 07 11:52:03 PM PDT 24 26443667600 ps
T1283 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.3027038596 Jun 07 09:36:50 PM PDT 24 Jun 07 09:45:51 PM PDT 24 5164285816 ps
T1284 /workspace/coverage/default/0.chip_sw_kmac_entropy.3015576193 Jun 07 09:35:10 PM PDT 24 Jun 07 09:38:57 PM PDT 24 3240277480 ps
T1285 /workspace/coverage/default/0.chip_sw_aes_idle.3048253769 Jun 07 09:36:52 PM PDT 24 Jun 07 09:40:17 PM PDT 24 3343009262 ps
T1286 /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.868111026 Jun 07 10:06:08 PM PDT 24 Jun 07 10:13:41 PM PDT 24 3528091124 ps
T16 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.1361226108 Jun 07 09:49:55 PM PDT 24 Jun 07 10:16:06 PM PDT 24 23990287160 ps
T1287 /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.3525525780 Jun 07 09:42:09 PM PDT 24 Jun 07 09:45:19 PM PDT 24 2644235544 ps
T1288 /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.3094605632 Jun 07 10:12:09 PM PDT 24 Jun 07 10:19:23 PM PDT 24 3543836404 ps
T1289 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.2314188169 Jun 07 09:46:11 PM PDT 24 Jun 07 10:42:59 PM PDT 24 13508124436 ps
T1290 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2660798486 Jun 07 09:45:28 PM PDT 24 Jun 07 10:27:24 PM PDT 24 22805201797 ps
T1291 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1414486539 Jun 07 09:44:16 PM PDT 24 Jun 07 10:54:41 PM PDT 24 14331367879 ps
T866 /workspace/coverage/default/74.chip_sw_all_escalation_resets.3724021128 Jun 07 10:14:11 PM PDT 24 Jun 07 10:22:05 PM PDT 24 4605687340 ps
T65 /workspace/coverage/default/4.chip_tap_straps_rma.3986370043 Jun 07 10:05:13 PM PDT 24 Jun 07 10:15:05 PM PDT 24 6109720437 ps
T1292 /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.706683670 Jun 07 10:06:11 PM PDT 24 Jun 07 10:33:38 PM PDT 24 8292949488 ps
T1293 /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.787128346 Jun 07 09:40:37 PM PDT 24 Jun 07 10:09:06 PM PDT 24 8781468984 ps
T380 /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.149883435 Jun 07 09:37:03 PM PDT 24 Jun 07 09:43:13 PM PDT 24 5584732840 ps
T1294 /workspace/coverage/default/1.rom_e2e_static_critical.2346396297 Jun 07 09:57:57 PM PDT 24 Jun 07 11:05:08 PM PDT 24 15985850110 ps
T762 /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.2975384539 Jun 07 09:38:39 PM PDT 24 Jun 07 09:45:43 PM PDT 24 4436311149 ps
T1295 /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.617971969 Jun 07 09:36:39 PM PDT 24 Jun 07 09:55:27 PM PDT 24 6316057351 ps
T1296 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.2495426212 Jun 07 09:40:54 PM PDT 24 Jun 07 09:54:30 PM PDT 24 9937733800 ps
T879 /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.1624881625 Jun 07 10:15:42 PM PDT 24 Jun 07 10:21:24 PM PDT 24 3742347920 ps
T354 /workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.3375405390 Jun 07 09:49:11 PM PDT 24 Jun 07 09:55:17 PM PDT 24 3445045086 ps
T44 /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.439324019 Jun 07 09:54:07 PM PDT 24 Jun 07 10:00:18 PM PDT 24 2913225220 ps
T1297 /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.2810122461 Jun 07 09:58:00 PM PDT 24 Jun 07 10:04:54 PM PDT 24 7776161680 ps
T1298 /workspace/coverage/default/2.chip_sw_hmac_multistream.1345885504 Jun 07 09:58:36 PM PDT 24 Jun 07 10:21:34 PM PDT 24 6983556000 ps
T791 /workspace/coverage/default/0.chip_sw_plic_sw_irq.2372472316 Jun 07 09:40:14 PM PDT 24 Jun 07 09:45:00 PM PDT 24 3458403996 ps
T1299 /workspace/coverage/default/2.chip_sw_ast_clk_outputs.2216836712 Jun 07 09:59:55 PM PDT 24 Jun 07 10:18:56 PM PDT 24 7445734718 ps
T1300 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.761257042 Jun 07 10:05:13 PM PDT 24 Jun 07 10:15:10 PM PDT 24 4748699572 ps
T1301 /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.3501252896 Jun 07 10:08:47 PM PDT 24 Jun 07 10:18:07 PM PDT 24 4047231686 ps
T820 /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.241190075 Jun 07 10:11:10 PM PDT 24 Jun 07 10:18:24 PM PDT 24 3402628724 ps
T1302 /workspace/coverage/default/0.rom_e2e_shutdown_output.1718712079 Jun 07 09:43:11 PM PDT 24 Jun 07 10:37:06 PM PDT 24 19872268312 ps
T1303 /workspace/coverage/default/1.chip_sw_hmac_multistream.2509960212 Jun 07 09:46:54 PM PDT 24 Jun 07 10:08:40 PM PDT 24 6479567660 ps
T849 /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.3378779620 Jun 07 10:12:40 PM PDT 24 Jun 07 10:19:17 PM PDT 24 4543668760 ps
T858 /workspace/coverage/default/64.chip_sw_all_escalation_resets.1153247643 Jun 07 10:12:29 PM PDT 24 Jun 07 10:20:18 PM PDT 24 4424114670 ps
T1304 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.3814975972 Jun 07 09:45:02 PM PDT 24 Jun 07 10:48:05 PM PDT 24 14093111597 ps
T1305 /workspace/coverage/default/0.chip_sw_hmac_enc_idle.360850851 Jun 07 09:48:16 PM PDT 24 Jun 07 09:52:24 PM PDT 24 2897616208 ps
T1306 /workspace/coverage/default/1.chip_sw_aes_idle.1480801893 Jun 07 09:45:10 PM PDT 24 Jun 07 09:48:46 PM PDT 24 2509912280 ps
T1307 /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.131791277 Jun 07 09:38:54 PM PDT 24 Jun 07 09:48:49 PM PDT 24 4336869900 ps
T1308 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.4156931324 Jun 07 09:53:01 PM PDT 24 Jun 07 09:57:29 PM PDT 24 3366995013 ps
T1309 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.2519713968 Jun 07 09:45:49 PM PDT 24 Jun 07 11:31:32 PM PDT 24 22844449604 ps
T1310 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.1899050077 Jun 07 09:38:58 PM PDT 24 Jun 07 10:00:01 PM PDT 24 14243143213 ps
T198 /workspace/coverage/default/1.chip_jtag_mem_access.2498204074 Jun 07 09:42:09 PM PDT 24 Jun 07 10:08:35 PM PDT 24 13868916511 ps
T205 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.3372565046 Jun 07 09:56:49 PM PDT 24 Jun 07 10:07:13 PM PDT 24 4982476018 ps
T47 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2837328311 Jun 07 09:38:12 PM PDT 24 Jun 07 09:46:07 PM PDT 24 5228020520 ps
T1311 /workspace/coverage/default/0.chip_sw_otbn_smoketest.1946378059 Jun 07 09:41:16 PM PDT 24 Jun 07 10:14:25 PM PDT 24 9308748824 ps
T1312 /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.2335494201 Jun 07 10:14:45 PM PDT 24 Jun 07 10:19:11 PM PDT 24 3139931876 ps
T1313 /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.4125089392 Jun 07 09:36:58 PM PDT 24 Jun 07 10:03:22 PM PDT 24 8022642500 ps
T351 /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.216784963 Jun 07 09:37:19 PM PDT 24 Jun 07 09:46:56 PM PDT 24 4384052310 ps
T1314 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.961732376 Jun 07 09:37:32 PM PDT 24 Jun 07 09:50:52 PM PDT 24 4824984342 ps
T1315 /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.2639233978 Jun 07 09:53:09 PM PDT 24 Jun 07 09:56:17 PM PDT 24 2632260280 ps
T1316 /workspace/coverage/default/0.chip_sw_csrng_smoketest.922637748 Jun 07 09:39:38 PM PDT 24 Jun 07 09:42:59 PM PDT 24 2411940208 ps
T1317 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.2831864300 Jun 07 09:48:06 PM PDT 24 Jun 07 10:34:52 PM PDT 24 13000399554 ps
T1318 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.2913875639 Jun 07 09:43:39 PM PDT 24 Jun 07 10:35:01 PM PDT 24 14456738172 ps
T350 /workspace/coverage/default/2.chip_sw_entropy_src_csrng.2918747434 Jun 07 09:57:35 PM PDT 24 Jun 07 10:20:19 PM PDT 24 7753892624 ps
T250 /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.389811392 Jun 07 09:52:00 PM PDT 24 Jun 07 10:20:28 PM PDT 24 23507825351 ps
T1319 /workspace/coverage/default/2.chip_sw_example_concurrency.3454295051 Jun 07 09:54:36 PM PDT 24 Jun 07 09:59:12 PM PDT 24 2269194166 ps
T1320 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.1975712892 Jun 07 10:01:27 PM PDT 24 Jun 07 10:06:01 PM PDT 24 3624587850 ps
T1321 /workspace/coverage/default/0.chip_sw_otbn_randomness.2720177639 Jun 07 09:36:47 PM PDT 24 Jun 07 09:52:47 PM PDT 24 6014697764 ps
T374 /workspace/coverage/default/37.chip_sw_all_escalation_resets.3606941910 Jun 07 10:10:31 PM PDT 24 Jun 07 10:21:07 PM PDT 24 5021577108 ps
T1322 /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.3147499146 Jun 07 09:46:29 PM PDT 24 Jun 07 09:50:45 PM PDT 24 2175040354 ps
T1323 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.531573160 Jun 07 09:47:22 PM PDT 24 Jun 07 10:06:51 PM PDT 24 10517936348 ps
T1324 /workspace/coverage/default/0.rom_e2e_static_critical.4266126310 Jun 07 09:46:12 PM PDT 24 Jun 07 10:52:47 PM PDT 24 15838720560 ps
T1325 /workspace/coverage/default/0.rom_e2e_asm_init_dev.4042650045 Jun 07 09:45:49 PM PDT 24 Jun 07 10:41:40 PM PDT 24 14107866475 ps
T189 /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.4088390540 Jun 07 09:51:25 PM PDT 24 Jun 07 10:00:50 PM PDT 24 4363340008 ps
T1326 /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.1878356441 Jun 07 09:49:07 PM PDT 24 Jun 07 09:58:27 PM PDT 24 4153533980 ps
T1327 /workspace/coverage/default/71.chip_sw_all_escalation_resets.2746597529 Jun 07 10:14:16 PM PDT 24 Jun 07 10:25:02 PM PDT 24 6112011226 ps
T1328 /workspace/coverage/default/0.chip_sw_ast_clk_outputs.1841411728 Jun 07 09:39:05 PM PDT 24 Jun 07 09:58:25 PM PDT 24 8195164046 ps
T306 /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.3074291835 Jun 07 10:11:08 PM PDT 24 Jun 07 10:17:37 PM PDT 24 4257851054 ps
T1329 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3131098675 Jun 07 09:35:22 PM PDT 24 Jun 07 10:09:56 PM PDT 24 14047261482 ps
T867 /workspace/coverage/default/16.chip_sw_all_escalation_resets.2785946514 Jun 07 10:08:05 PM PDT 24 Jun 07 10:15:38 PM PDT 24 6104652938 ps
T1330 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.1962565438 Jun 07 09:51:09 PM PDT 24 Jun 07 09:53:47 PM PDT 24 3198517643 ps
T872 /workspace/coverage/default/88.chip_sw_all_escalation_resets.586746659 Jun 07 10:16:10 PM PDT 24 Jun 07 10:25:26 PM PDT 24 4641915106 ps
T286 /workspace/coverage/default/5.chip_sw_data_integrity_escalation.3191604308 Jun 07 10:05:13 PM PDT 24 Jun 07 10:17:13 PM PDT 24 5719605944 ps
T1331 /workspace/coverage/default/2.rom_e2e_asm_init_prod.1759870875 Jun 07 10:07:46 PM PDT 24 Jun 07 10:59:15 PM PDT 24 14467322207 ps
T1332 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3291912271 Jun 07 09:48:45 PM PDT 24 Jun 07 10:03:12 PM PDT 24 4769822720 ps
T1333 /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.1185891837 Jun 07 09:38:22 PM PDT 24 Jun 07 09:43:57 PM PDT 24 3472595884 ps
T330 /workspace/coverage/default/15.chip_sw_all_escalation_resets.111611735 Jun 07 10:07:40 PM PDT 24 Jun 07 10:17:22 PM PDT 24 5143118420 ps
T130 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3524777332 Jun 07 09:59:41 PM PDT 24 Jun 07 10:07:34 PM PDT 24 4781072744 ps
T873 /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3721989269 Jun 07 10:16:22 PM PDT 24 Jun 07 10:22:52 PM PDT 24 4518410430 ps
T1334 /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.1806579533 Jun 07 09:38:48 PM PDT 24 Jun 07 09:48:38 PM PDT 24 4628361780 ps
T1335 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.2988528330 Jun 07 09:46:07 PM PDT 24 Jun 07 10:00:09 PM PDT 24 6186285280 ps
T1336 /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.3027836025 Jun 07 09:43:50 PM PDT 24 Jun 07 10:51:19 PM PDT 24 14201627427 ps
T1337 /workspace/coverage/default/1.chip_sw_aes_masking_off.1575801373 Jun 07 09:44:00 PM PDT 24 Jun 07 09:48:16 PM PDT 24 2402497874 ps
T134 /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.453973676 Jun 07 09:59:55 PM PDT 24 Jun 07 10:09:44 PM PDT 24 4808892968 ps
T1338 /workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.231803127 Jun 07 09:37:19 PM PDT 24 Jun 07 09:43:21 PM PDT 24 3187860147 ps
T1339 /workspace/coverage/default/1.chip_sw_uart_tx_rx.3691038120 Jun 07 09:40:22 PM PDT 24 Jun 07 09:50:31 PM PDT 24 4370782250 ps
T1340 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.269039458 Jun 07 09:43:34 PM PDT 24 Jun 07 10:39:09 PM PDT 24 14015621752 ps
T1341 /workspace/coverage/default/3.chip_tap_straps_rma.61734274 Jun 07 10:03:32 PM PDT 24 Jun 07 10:08:14 PM PDT 24 4038286843 ps
T1342 /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.3409826946 Jun 07 10:12:30 PM PDT 24 Jun 07 10:17:39 PM PDT 24 3423953820 ps
T138 /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.133472765 Jun 07 10:04:15 PM PDT 24 Jun 07 10:16:06 PM PDT 24 7129745288 ps
T1343 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.1863668966 Jun 07 09:37:28 PM PDT 24 Jun 07 09:56:09 PM PDT 24 7419058560 ps
T1344 /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.2294617156 Jun 07 09:52:03 PM PDT 24 Jun 07 09:57:35 PM PDT 24 2839644976 ps
T1345 /workspace/coverage/default/73.chip_sw_all_escalation_resets.1886439679 Jun 07 10:14:37 PM PDT 24 Jun 07 10:24:08 PM PDT 24 5461859272 ps
T1346 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.1493601137 Jun 07 09:37:14 PM PDT 24 Jun 07 09:53:00 PM PDT 24 5606251084 ps
T1347 /workspace/coverage/default/0.chip_sw_coremark.3605468361 Jun 07 09:37:42 PM PDT 24 Jun 08 01:25:17 AM PDT 24 71364161372 ps
T909 /workspace/coverage/default/1.chip_sw_all_escalation_resets.2723602794 Jun 07 09:42:32 PM PDT 24 Jun 07 09:53:07 PM PDT 24 5172339000 ps
T865 /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.1028206805 Jun 07 10:15:07 PM PDT 24 Jun 07 10:22:59 PM PDT 24 3296081288 ps
T21 /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3482488088 Jun 07 09:42:52 PM PDT 24 Jun 07 09:50:17 PM PDT 24 3532377651 ps
T307 /workspace/coverage/default/96.chip_sw_all_escalation_resets.654456581 Jun 07 10:15:29 PM PDT 24 Jun 07 10:24:51 PM PDT 24 5630377538 ps
T1348 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.2588665910 Jun 07 09:47:52 PM PDT 24 Jun 07 10:50:45 PM PDT 24 10662543924 ps
T324 /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.606716848 Jun 07 09:49:16 PM PDT 24 Jun 07 10:05:47 PM PDT 24 7033848584 ps
T22 /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3134651772 Jun 07 09:37:06 PM PDT 24 Jun 07 09:42:34 PM PDT 24 3275078460 ps
T897 /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.1030343359 Jun 07 10:13:18 PM PDT 24 Jun 07 10:19:13 PM PDT 24 3642916840 ps
T355 /workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.372804412 Jun 07 09:40:38 PM PDT 24 Jun 07 09:47:20 PM PDT 24 3616404384 ps
T398 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.3115137764 Jun 07 09:54:35 PM PDT 24 Jun 07 10:11:55 PM PDT 24 6538659496 ps
T1349 /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.3799730840 Jun 07 09:36:17 PM PDT 24 Jun 07 09:41:27 PM PDT 24 3753634392 ps
T1350 /workspace/coverage/default/2.chip_sw_kmac_app_rom.4027665686 Jun 07 09:59:01 PM PDT 24 Jun 07 10:02:38 PM PDT 24 2357650120 ps
T792 /workspace/coverage/default/2.chip_sw_plic_sw_irq.3490664362 Jun 07 10:01:18 PM PDT 24 Jun 07 10:05:57 PM PDT 24 2385019184 ps
T238 /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.3233510294 Jun 07 09:38:35 PM PDT 24 Jun 07 10:47:47 PM PDT 24 16009828134 ps
T1351 /workspace/coverage/default/0.chip_sw_power_idle_load.806667006 Jun 07 09:40:43 PM PDT 24 Jun 07 09:52:35 PM PDT 24 4392330664 ps
T1352 /workspace/coverage/default/75.chip_sw_all_escalation_resets.4226728617 Jun 07 10:14:01 PM PDT 24 Jun 07 10:22:38 PM PDT 24 4687138296 ps
T142 /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.3395634615 Jun 07 10:00:51 PM PDT 24 Jun 07 10:05:29 PM PDT 24 2331942744 ps
T863 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.134976035 Jun 07 10:00:02 PM PDT 24 Jun 07 10:06:38 PM PDT 24 3678252824 ps
T827 /workspace/coverage/default/61.chip_sw_all_escalation_resets.3493066493 Jun 07 10:12:53 PM PDT 24 Jun 07 10:23:11 PM PDT 24 5885817114 ps
T308 /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.2051447827 Jun 07 10:14:58 PM PDT 24 Jun 07 10:23:11 PM PDT 24 3957956878 ps
T1353 /workspace/coverage/default/1.chip_tap_straps_testunlock0.3934624244 Jun 07 09:50:18 PM PDT 24 Jun 07 09:53:02 PM PDT 24 2634772201 ps
T1354 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.2467290227 Jun 07 09:57:34 PM PDT 24 Jun 07 10:05:00 PM PDT 24 4512774464 ps
T1355 /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.966024946 Jun 07 10:10:30 PM PDT 24 Jun 07 10:17:46 PM PDT 24 3405862096 ps
T375 /workspace/coverage/default/54.chip_sw_all_escalation_resets.478989835 Jun 07 10:12:57 PM PDT 24 Jun 07 10:26:17 PM PDT 24 4606399940 ps
T1356 /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.3654048561 Jun 07 09:45:55 PM PDT 24 Jun 07 10:42:02 PM PDT 24 13588403961 ps
T1357 /workspace/coverage/default/2.chip_sw_gpio_smoketest.2034402172 Jun 07 10:02:48 PM PDT 24 Jun 07 10:07:25 PM PDT 24 3250079761 ps
T1358 /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.1865243446 Jun 07 10:07:15 PM PDT 24 Jun 07 10:14:43 PM PDT 24 4203472360 ps
T325 /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.15030133 Jun 07 09:59:27 PM PDT 24 Jun 07 10:16:27 PM PDT 24 7576266065 ps
T1359 /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.3401800618 Jun 07 09:48:46 PM PDT 24 Jun 07 09:52:53 PM PDT 24 2739917614 ps
T1360 /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.2450682449 Jun 07 10:06:39 PM PDT 24 Jun 07 11:26:02 PM PDT 24 23103006552 ps
T1361 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.138232737 Jun 07 09:37:54 PM PDT 24 Jun 07 10:02:50 PM PDT 24 7387386610 ps
T1362 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3531983162 Jun 07 09:56:21 PM PDT 24 Jun 07 10:17:58 PM PDT 24 14560745231 ps
T1363 /workspace/coverage/default/0.chip_sw_example_concurrency.4088421843 Jun 07 09:36:20 PM PDT 24 Jun 07 09:40:00 PM PDT 24 3085591660 ps
T1364 /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.1270083237 Jun 07 09:45:08 PM PDT 24 Jun 07 09:52:54 PM PDT 24 3476367372 ps
T874 /workspace/coverage/default/35.chip_sw_all_escalation_resets.1816901155 Jun 07 10:10:16 PM PDT 24 Jun 07 10:22:04 PM PDT 24 4364235270 ps
T1365 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.2028206750 Jun 07 09:38:53 PM PDT 24 Jun 07 09:46:15 PM PDT 24 6365056678 ps
T1366 /workspace/coverage/default/0.chip_tap_straps_prod.2566480267 Jun 07 09:35:58 PM PDT 24 Jun 07 09:38:17 PM PDT 24 2317426251 ps
T400 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.82564372 Jun 07 09:55:54 PM PDT 24 Jun 07 10:09:44 PM PDT 24 5392940618 ps
T9 /workspace/coverage/default/0.chip_jtag_csr_rw.1748904635 Jun 07 09:29:46 PM PDT 24 Jun 07 10:17:04 PM PDT 24 20597959416 ps
T417 /workspace/coverage/default/28.chip_sw_all_escalation_resets.1717397973 Jun 07 10:10:44 PM PDT 24 Jun 07 10:21:45 PM PDT 24 5486414664 ps
T418 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.980457370 Jun 07 09:56:16 PM PDT 24 Jun 07 10:05:20 PM PDT 24 3715826651 ps
T419 /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2876022696 Jun 07 10:06:29 PM PDT 24 Jun 07 10:30:44 PM PDT 24 7686044256 ps
T89 /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.2862260836 Jun 07 10:14:32 PM PDT 24 Jun 07 10:21:48 PM PDT 24 4155262900 ps
T420 /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.2934908732 Jun 07 10:07:16 PM PDT 24 Jun 07 10:30:16 PM PDT 24 9001677184 ps
T421 /workspace/coverage/default/1.chip_sw_csrng_kat_test.2089203990 Jun 07 09:48:38 PM PDT 24 Jun 07 09:53:54 PM PDT 24 3452697400 ps
T422 /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.3871955744 Jun 07 10:13:27 PM PDT 24 Jun 07 10:18:37 PM PDT 24 4242334856 ps
T316 /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.1426950029 Jun 07 10:01:16 PM PDT 24 Jun 07 10:06:42 PM PDT 24 2836917640 ps
T423 /workspace/coverage/default/77.chip_sw_all_escalation_resets.3128367108 Jun 07 10:13:47 PM PDT 24 Jun 07 10:23:26 PM PDT 24 5370584520 ps
T1367 /workspace/coverage/default/1.chip_sw_csrng_smoketest.4040261355 Jun 07 09:55:34 PM PDT 24 Jun 07 09:59:42 PM PDT 24 3337569120 ps
T1368 /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.1248114338 Jun 07 09:55:13 PM PDT 24 Jun 07 10:05:25 PM PDT 24 4020256034 ps
T1369 /workspace/coverage/default/0.chip_sw_aes_entropy.467148579 Jun 07 09:39:57 PM PDT 24 Jun 07 09:44:52 PM PDT 24 3414169318 ps
T1370 /workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.2031032539 Jun 07 09:50:46 PM PDT 24 Jun 07 09:55:46 PM PDT 24 2833725580 ps
T234 /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.3995849522 Jun 07 09:38:03 PM PDT 24 Jun 07 10:09:15 PM PDT 24 9749751976 ps
T1371 /workspace/coverage/default/12.chip_sw_all_escalation_resets.3151650005 Jun 07 10:06:19 PM PDT 24 Jun 07 10:15:52 PM PDT 24 5347704636 ps
T1372 /workspace/coverage/default/2.chip_sw_edn_auto_mode.1857010648 Jun 07 09:56:50 PM PDT 24 Jun 07 10:15:10 PM PDT 24 4645414402 ps
T370 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1028178733 Jun 07 09:38:37 PM PDT 24 Jun 07 09:49:20 PM PDT 24 4478931196 ps
T1373 /workspace/coverage/default/0.chip_sw_uart_tx_rx.1756170255 Jun 07 09:35:40 PM PDT 24 Jun 07 09:46:09 PM PDT 24 4372402352 ps
T152 /workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.1474735272 Jun 07 09:55:54 PM PDT 24 Jun 08 12:56:51 AM PDT 24 58999702240 ps
T1374 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.1321874529 Jun 07 09:43:46 PM PDT 24 Jun 07 10:02:56 PM PDT 24 5853935701 ps
T890 /workspace/coverage/default/86.chip_sw_all_escalation_resets.3682577758 Jun 07 10:16:38 PM PDT 24 Jun 07 10:28:26 PM PDT 24 6317746720 ps
T317 /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.1869490514 Jun 07 09:51:09 PM PDT 24 Jun 07 09:54:37 PM PDT 24 2885965232 ps
T1375 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.8548662 Jun 07 09:41:02 PM PDT 24 Jun 07 10:13:32 PM PDT 24 13537992471 ps
T1376 /workspace/coverage/default/1.chip_sw_ast_clk_outputs.4140254638 Jun 07 09:48:44 PM PDT 24 Jun 07 10:10:11 PM PDT 24 8492056736 ps
T331 /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.3197416347 Jun 07 10:08:38 PM PDT 24 Jun 07 10:16:43 PM PDT 24 4419267364 ps
T840 /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.2879110342 Jun 07 10:16:23 PM PDT 24 Jun 07 10:23:58 PM PDT 24 3937277804 ps
T1377 /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.2297116280 Jun 07 10:00:52 PM PDT 24 Jun 07 10:32:13 PM PDT 24 20081184522 ps
T1378 /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.3168837080 Jun 07 10:12:57 PM PDT 24 Jun 07 10:19:45 PM PDT 24 4166775888 ps
T1379 /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.2968721812 Jun 07 09:52:34 PM PDT 24 Jun 07 09:57:19 PM PDT 24 2769276424 ps
T135 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1491963223 Jun 07 09:48:42 PM PDT 24 Jun 07 09:56:03 PM PDT 24 5401670276 ps
T1380 /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.1061544944 Jun 07 09:59:45 PM PDT 24 Jun 07 10:08:42 PM PDT 24 4920561800 ps
T1381 /workspace/coverage/default/1.chip_sw_uart_smoketest.3588960362 Jun 07 09:55:38 PM PDT 24 Jun 07 10:00:27 PM PDT 24 3425063376 ps
T1382 /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.549915461 Jun 07 09:55:42 PM PDT 24 Jun 07 10:16:10 PM PDT 24 5517299301 ps
T1383 /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.2473708788 Jun 07 09:55:42 PM PDT 24 Jun 07 10:01:37 PM PDT 24 3092005198 ps
T1384 /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.906824394 Jun 07 10:11:38 PM PDT 24 Jun 07 10:17:12 PM PDT 24 4404917144 ps
T1385 /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.1624456707 Jun 07 09:49:02 PM PDT 24 Jun 07 10:10:00 PM PDT 24 11914527962 ps
T1386 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.839902330 Jun 07 09:58:17 PM PDT 24 Jun 07 10:49:46 PM PDT 24 16773686120 ps
T862 /workspace/coverage/default/25.chip_sw_all_escalation_resets.1759557773 Jun 07 10:14:18 PM PDT 24 Jun 07 10:22:48 PM PDT 24 6033812568 ps
T1387 /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.4138187726 Jun 07 09:35:38 PM PDT 24 Jun 07 09:59:06 PM PDT 24 8956290168 ps
T1388 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.167927647 Jun 07 09:43:17 PM PDT 24 Jun 07 10:05:57 PM PDT 24 11819179712 ps
T340 /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2906608112 Jun 07 10:02:34 PM PDT 24 Jun 07 10:10:20 PM PDT 24 4357340220 ps
T38 /workspace/coverage/default/2.chip_sw_gpio.3141298987 Jun 07 09:56:15 PM PDT 24 Jun 07 10:04:33 PM PDT 24 4817747590 ps
T1389 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.1877540999 Jun 07 09:44:16 PM PDT 24 Jun 07 11:28:21 PM PDT 24 50020800894 ps
T1390 /workspace/coverage/default/2.rom_e2e_asm_init_rma.4129994192 Jun 07 10:07:48 PM PDT 24 Jun 07 11:00:29 PM PDT 24 14010656600 ps
T1391 /workspace/coverage/default/2.chip_sw_hmac_oneshot.354892129 Jun 07 10:00:23 PM PDT 24 Jun 07 10:05:43 PM PDT 24 3044151276 ps
T1392 /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.2594138048 Jun 07 09:58:13 PM PDT 24 Jun 07 10:01:13 PM PDT 24 2652051402 ps
T199 /workspace/coverage/default/0.chip_jtag_mem_access.3545592870 Jun 07 09:29:47 PM PDT 24 Jun 07 09:56:48 PM PDT 24 13863254508 ps
T396 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.645116704 Jun 07 09:45:28 PM PDT 24 Jun 07 09:57:28 PM PDT 24 4274143096 ps
T839 /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.2342276476 Jun 07 10:05:48 PM PDT 24 Jun 07 10:13:10 PM PDT 24 3336764600 ps
T1393 /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.3116481207 Jun 07 09:38:07 PM PDT 24 Jun 07 09:41:31 PM PDT 24 3327659139 ps
T846 /workspace/coverage/default/44.chip_sw_all_escalation_resets.4224588875 Jun 07 10:11:23 PM PDT 24 Jun 07 10:21:16 PM PDT 24 4303135990 ps
T1394 /workspace/coverage/default/36.chip_sw_all_escalation_resets.733908270 Jun 07 10:12:40 PM PDT 24 Jun 07 10:22:21 PM PDT 24 4950077416 ps
T251 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.3866642799 Jun 07 09:55:17 PM PDT 24 Jun 07 11:21:43 PM PDT 24 46873170250 ps
T1395 /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.1001519448 Jun 07 09:58:04 PM PDT 24 Jun 07 10:57:32 PM PDT 24 14653197792 ps
T1396 /workspace/coverage/default/0.chip_sw_example_flash.2174514374 Jun 07 09:35:59 PM PDT 24 Jun 07 09:39:32 PM PDT 24 2702951192 ps
T1397 /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.1749089935 Jun 07 10:09:35 PM PDT 24 Jun 07 10:15:43 PM PDT 24 3923110416 ps
T1398 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.1541136410 Jun 07 10:03:59 PM PDT 24 Jun 07 10:17:50 PM PDT 24 4601274426 ps
T877 /workspace/coverage/default/51.chip_sw_all_escalation_resets.646385497 Jun 07 10:11:28 PM PDT 24 Jun 07 10:21:06 PM PDT 24 4565558450 ps
T107 /workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.336242977 Jun 07 09:51:50 PM PDT 24 Jun 07 10:35:11 PM PDT 24 19191921098 ps
T1399 /workspace/coverage/default/1.chip_tap_straps_rma.2518076035 Jun 07 09:53:38 PM PDT 24 Jun 07 09:57:40 PM PDT 24 3650692493 ps
T431 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.835961458 Jun 07 09:49:29 PM PDT 24 Jun 07 10:19:07 PM PDT 24 21808824320 ps
T1400 /workspace/coverage/default/0.chip_sw_aes_enc.769243687 Jun 07 09:45:17 PM PDT 24 Jun 07 09:51:21 PM PDT 24 3146510916 ps
T1401 /workspace/coverage/default/0.chip_sw_edn_kat.2686386112 Jun 07 09:41:18 PM PDT 24 Jun 07 09:52:32 PM PDT 24 3078882256 ps
T1402 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.1322245596 Jun 07 09:46:38 PM PDT 24 Jun 07 11:12:58 PM PDT 24 22304369684 ps
T1403 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.1954895923 Jun 07 09:47:38 PM PDT 24 Jun 07 10:53:48 PM PDT 24 15539756560 ps
T1404 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.744664747 Jun 07 09:38:26 PM PDT 24 Jun 07 09:50:16 PM PDT 24 7297198002 ps
T1405 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3510194147 Jun 07 09:39:18 PM PDT 24 Jun 07 09:50:21 PM PDT 24 6002754525 ps
T1406 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.2834068828 Jun 07 09:37:31 PM PDT 24 Jun 07 11:16:38 PM PDT 24 51175182786 ps
T13 /workspace/coverage/default/0.chip_sw_sleep_pin_retention.3763758475 Jun 07 09:37:06 PM PDT 24 Jun 07 09:41:58 PM PDT 24 4075539740 ps
T1407 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2665629559 Jun 07 09:49:25 PM PDT 24 Jun 07 09:57:37 PM PDT 24 4954531608 ps
T1408 /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.287424484 Jun 07 09:42:31 PM PDT 24 Jun 07 09:48:46 PM PDT 24 5579021392 ps
T825 /workspace/coverage/default/7.chip_sw_all_escalation_resets.242944225 Jun 07 10:06:24 PM PDT 24 Jun 07 10:17:33 PM PDT 24 4543596412 ps
T814 /workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.3701658857 Jun 07 09:41:39 PM PDT 24 Jun 07 10:25:22 PM PDT 24 12501559050 ps
T1409 /workspace/coverage/default/2.chip_sw_hmac_enc_idle.3371841192 Jun 07 09:58:32 PM PDT 24 Jun 07 10:03:28 PM PDT 24 2853004600 ps
T1410 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.3185179596 Jun 07 09:48:18 PM PDT 24 Jun 07 11:24:56 PM PDT 24 18084055790 ps
T1411 /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.2878319273 Jun 07 09:42:42 PM PDT 24 Jun 07 09:48:25 PM PDT 24 2548523764 ps
T1412 /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.4178089365 Jun 07 09:39:12 PM PDT 24 Jun 07 09:43:31 PM PDT 24 2793751048 ps
T1413 /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.563614665 Jun 07 10:13:15 PM PDT 24 Jun 07 10:18:40 PM PDT 24 3741016780 ps
T1414 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.2060523619 Jun 07 09:44:58 PM PDT 24 Jun 07 09:58:00 PM PDT 24 8292135996 ps
T1415 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.315564670 Jun 07 09:37:17 PM PDT 24 Jun 07 09:48:38 PM PDT 24 3323411002 ps
T1416 /workspace/coverage/default/2.chip_sival_flash_info_access.3041245676 Jun 07 09:53:28 PM PDT 24 Jun 07 09:58:31 PM PDT 24 2779870088 ps
T1417 /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.2409161479 Jun 07 09:47:50 PM PDT 24 Jun 07 09:52:05 PM PDT 24 2940006485 ps
T1418 /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.3362774692 Jun 07 09:37:20 PM PDT 24 Jun 07 09:53:40 PM PDT 24 5506276680 ps
T1419 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.1554253005 Jun 07 09:44:02 PM PDT 24 Jun 07 09:45:53 PM PDT 24 2997137492 ps
T382 /workspace/coverage/default/5.chip_sw_all_escalation_resets.836151865 Jun 07 10:05:14 PM PDT 24 Jun 07 10:13:14 PM PDT 24 5366566400 ps
T1420 /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.2795981957 Jun 07 09:40:57 PM PDT 24 Jun 07 09:48:32 PM PDT 24 3674480184 ps
T881 /workspace/coverage/default/76.chip_sw_all_escalation_resets.484120037 Jun 07 10:14:24 PM PDT 24 Jun 07 10:24:18 PM PDT 24 4950815872 ps
T348 /workspace/coverage/default/2.chip_plic_all_irqs_20.1453777896 Jun 07 09:59:57 PM PDT 24 Jun 07 10:14:25 PM PDT 24 4471805250 ps
T1421 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.3722417241 Jun 07 10:00:09 PM PDT 24 Jun 07 10:06:12 PM PDT 24 3061072790 ps
T1422 /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.698079872 Jun 07 09:57:02 PM PDT 24 Jun 07 10:02:36 PM PDT 24 3599492104 ps
T1423 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3685854897 Jun 07 09:50:18 PM PDT 24 Jun 07 10:50:36 PM PDT 24 24980933362 ps
T1424 /workspace/coverage/default/0.rom_volatile_raw_unlock.430812824 Jun 07 09:43:49 PM PDT 24 Jun 07 09:45:46 PM PDT 24 2847105761 ps
T181 /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.1156126052 Jun 07 09:41:31 PM PDT 24 Jun 07 10:58:59 PM PDT 24 43494420105 ps
T1425 /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.3724023143 Jun 07 09:48:38 PM PDT 24 Jun 07 10:24:47 PM PDT 24 32433216845 ps
T1426 /workspace/coverage/default/70.chip_sw_all_escalation_resets.3794842563 Jun 07 10:15:54 PM PDT 24 Jun 07 10:25:05 PM PDT 24 5101150400 ps
T1427 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.1261746151 Jun 07 09:36:47 PM PDT 24 Jun 07 09:50:11 PM PDT 24 4505437800 ps
T73 /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.3159415145 Jun 07 09:21:28 PM PDT 24 Jun 07 09:27:58 PM PDT 24 4805585834 ps
T74 /workspace/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.2708801385 Jun 07 09:16:52 PM PDT 24 Jun 07 09:18:00 PM PDT 24 3974612301 ps
T75 /workspace/coverage/cover_reg_top/8.chip_tl_errors.2091890115 Jun 07 09:08:01 PM PDT 24 Jun 07 09:14:41 PM PDT 24 4194341331 ps
T78 /workspace/coverage/cover_reg_top/68.xbar_random_zero_delays.719921234 Jun 07 09:22:47 PM PDT 24 Jun 07 09:22:59 PM PDT 24 98443153 ps
T125 /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_error.3497384313 Jun 07 09:11:11 PM PDT 24 Jun 07 09:12:08 PM PDT 24 710352896 ps
T262 /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_error.3248203375 Jun 07 09:23:29 PM PDT 24 Jun 07 09:25:03 PM PDT 24 2485762146 ps
T558 /workspace/coverage/cover_reg_top/91.xbar_smoke_zero_delays.1714741310 Jun 07 09:26:31 PM PDT 24 Jun 07 09:26:38 PM PDT 24 49511644 ps
T548 /workspace/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.4147787773 Jun 07 09:19:46 PM PDT 24 Jun 07 09:35:33 PM PDT 24 51837347666 ps
T549 /workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.1719080506 Jun 07 09:09:42 PM PDT 24 Jun 07 09:10:23 PM PDT 24 410041718 ps
T557 /workspace/coverage/cover_reg_top/70.xbar_random_slow_rsp.4274914912 Jun 07 09:23:08 PM PDT 24 Jun 07 09:38:19 PM PDT 24 52116722618 ps
T550 /workspace/coverage/cover_reg_top/67.xbar_random_large_delays.351329720 Jun 07 09:22:34 PM PDT 24 Jun 07 09:35:28 PM PDT 24 63679835366 ps
T434 /workspace/coverage/cover_reg_top/96.xbar_unmapped_addr.486913271 Jun 07 09:27:23 PM PDT 24 Jun 07 09:28:24 PM PDT 24 1350831213 ps
T556 /workspace/coverage/cover_reg_top/34.xbar_random.2436094796 Jun 07 09:16:17 PM PDT 24 Jun 07 09:17:07 PM PDT 24 1135138645 ps
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