Unified Coverage Report :: Module :: prim_alert_sender

Module : prim_alert_sender

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_sender.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender	75.00			75.00
tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender	79.17			79.17
tb.dut.top_earlgrey.u_pinmux_aon.gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
tb.dut.top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender	100.00			100.00
tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.77	94.12	89.29	87.28		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17			79.17

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17			79.17

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.77	94.12	89.29	87.28		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_alert_tx[0].u_prim_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
88.58	98.96	79.90	97.97		74.10	92.00	u_pinmux_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.09	99.65	100.00	90.78		100.00	90.00	u_rv_plic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.77	94.12	89.29	87.28		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.77	94.12	89.29	87.28		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T6,T17,T18	Yes	T4,T5,T6	INPUT
alert_test_i	Yes	Yes	T78,T245,T76	Yes	T78,T245,T76	INPUT
alert_req_i	Yes	Yes	T17,T73,T244	Yes	T17,T73,T244	INPUT
alert_ack_o	Yes	Yes	T17,T73,T127	Yes	T17,T73,T127	OUTPUT
alert_state_o	Yes	Yes	T17,T73,T127	Yes	T17,T73,T244	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i.ack_p	Yes	Yes	T17,T27,T29	Yes	T17,T27,T29	INPUT
alert_rx_i.ping_n	Yes	Yes	T27,T29,T128	Yes	T27,T29,T128	INPUT
alert_rx_i.ping_p	Yes	Yes	T27,T29,T128	Yes	T27,T29,T128	INPUT
alert_tx_o.alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T17,T27,T29	Yes	T17,T27,T29	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender

	Total	Covered	Percent
Totals	12	9	75.00
Total Bits	24	18	75.00
Total Bits 0->1	12	9	75.00
Total Bits 1->0	12	9	75.00

Ports	12	9	75.00
Port Bits	24	18	75.00
Port Bits 0->1	12	9	75.00
Port Bits 1->0	12	9	75.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T6,T17,T18	Yes	T4,T5,T6	INPUT
alert_test_i	Yes	Yes	T78,T245,T79	Yes	T78,T245,T79	INPUT
alert_req_i	No	No		No		INPUT
alert_ack_o	No	No		No		OUTPUT
alert_state_o	No	No		No		OUTPUT
alert_rx_i.ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i.ack_p	Yes	Yes	T27,T29,T128	Yes	T27,T29,T128	INPUT
alert_rx_i.ping_n	Yes	Yes	T27,T29,T128	Yes	T27,T29,T128	INPUT
alert_rx_i.ping_p	Yes	Yes	T27,T29,T128	Yes	T27,T29,T128	INPUT
alert_tx_o.alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T27,T29,T128	Yes	T27,T29,T128	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender

	Total	Covered	Percent
Totals	12	9	75.00
Total Bits	24	19	79.17
Total Bits 0->1	12	10	83.33
Total Bits 1->0	12	9	75.00

Ports	12	9	75.00
Port Bits	24	19	79.17
Port Bits 0->1	12	10	83.33
Port Bits 1->0	12	9	75.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T6,T17,T18	Yes	T4,T5,T6	INPUT
alert_test_i	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
alert_req_i	No	No		Yes	T280	INPUT
alert_ack_o	No	No		No		OUTPUT
alert_state_o	No	No		No		OUTPUT
alert_rx_i.ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i.ack_p	Yes	Yes	T27,T29,T128	Yes	T27,T29,T128	INPUT
alert_rx_i.ping_n	Yes	Yes	T27,T29,T128	Yes	T27,T29,T128	INPUT
alert_rx_i.ping_p	Yes	Yes	T27,T29,T128	Yes	T27,T29,T128	INPUT
alert_tx_o.alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T27,T29,T128	Yes	T27,T29,T128	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_alert_tx[0].u_prim_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T6,T17,T18	Yes	T4,T5,T6	INPUT
alert_test_i	Yes	Yes	T78,T76,T79	Yes	T78,T76,T79	INPUT
alert_req_i	Yes	Yes	T127	Yes	T127,T131,T132	INPUT
alert_ack_o	Yes	Yes	T127,T131,T132	Yes	T127,T131,T132	OUTPUT
alert_state_o	Yes	Yes	T127	Yes	T127,T131,T132	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i.ack_p	Yes	Yes	T27,T29,T127	Yes	T27,T29,T127	INPUT
alert_rx_i.ping_n	Yes	Yes	T27,T29,T128	Yes	T27,T29,T128	INPUT
alert_rx_i.ping_p	Yes	Yes	T27,T29,T128	Yes	T27,T29,T128	INPUT
alert_tx_o.alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T27,T29,T127	Yes	T27,T29,T127	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T6,T17,T18	Yes	T4,T5,T6	INPUT
alert_test_i	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
alert_req_i	Yes	Yes	T351,T374,T394	Yes	T351,T374,T375	INPUT
alert_ack_o	Yes	Yes	T351,T374,T375	Yes	T351,T374,T375	OUTPUT
alert_state_o	Yes	Yes	T351,T374,T394	Yes	T351,T374,T375	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i.ack_p	Yes	Yes	T27,T29,T128	Yes	T27,T29,T128	INPUT
alert_rx_i.ping_n	Yes	Yes	T27,T29,T128	Yes	T27,T29,T128	INPUT
alert_rx_i.ping_p	Yes	Yes	T27,T29,T128	Yes	T27,T29,T128	INPUT
alert_tx_o.alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T27,T29,T128	Yes	T27,T29,T128	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T6,T17,T18	Yes	T4,T5,T6	INPUT
alert_test_i	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
alert_req_i	Yes	Yes	T73,T309,T310	Yes	T73,T309,T310	INPUT
alert_ack_o	Yes	Yes	T73,T309,T310	Yes	T73,T309,T310	OUTPUT
alert_state_o	Yes	Yes	T73,T309,T310	Yes	T73,T309,T310	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i.ack_p	Yes	Yes	T27,T29,T73	Yes	T27,T29,T73	INPUT
alert_rx_i.ping_n	Yes	Yes	T27,T29,T128	Yes	T27,T29,T128	INPUT
alert_rx_i.ping_p	Yes	Yes	T27,T29,T128	Yes	T27,T29,T128	INPUT
alert_tx_o.alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T27,T29,T73	Yes	T27,T29,T73	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T6,T17,T18	Yes	T4,T5,T6	INPUT
alert_test_i	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
alert_req_i	Yes	Yes	T17,T244,T113	Yes	T17,T244,T113	INPUT
alert_ack_o	Yes	Yes	T17,T113,T114	Yes	T17,T113,T114	OUTPUT
alert_state_o	Yes	Yes	T17,T113,T114	Yes	T17,T244,T113	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i.ack_p	Yes	Yes	T17,T27,T29	Yes	T17,T27,T29	INPUT
alert_rx_i.ping_n	Yes	Yes	T27,T29,T128	Yes	T29,T128,T263	INPUT
alert_rx_i.ping_p	Yes	Yes	T29,T128,T263	Yes	T27,T29,T128	INPUT
alert_tx_o.alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T17,T27,T29	Yes	T17,T27,T29	OUTPUT