Unified Coverage Report :: Module :: rv_core_ibex

Module : rv_core_ibex

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.56	94.12	89.29	86.21		100.00	68.18

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex	87.77	94.12	89.29	87.28		100.00	68.18

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.77	94.12	89.29	87.28		100.00	68.18

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.09	94.18	75.50	90.34		93.28	92.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.12	88.53		87.83			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
fifo_d	100.00	100.00	100.00			100.00	100.00
fifo_i	93.75	75.00	100.00			100.00	100.00
gen_alert_senders[0].u_alert_sender	100.00			100.00
gen_alert_senders[1].u_alert_sender	75.00			75.00
gen_alert_senders[2].u_alert_sender	100.00			100.00
gen_alert_senders[3].u_alert_sender	79.17			79.17
tl_adapter_host_d_ibex	91.79	95.35	81.82			90.00	100.00
tl_adapter_host_i_ibex	87.90	90.48	72.22			88.89	100.00
u_alert_nmi_sync	100.00	100.00				100.00
u_core	96.51			96.51
u_core_sleeping_buf	100.00	100.00
u_dbus_trans	96.36	100.00	92.59			100.00	92.86
u_edn_if	89.08	100.00	86.44			94.87	75.00
u_ibus_trans	96.36	100.00	92.59			100.00	92.86
u_intr_timer_sync	100.00	100.00				100.00
u_lc_sync	100.00	100.00				100.00	100.00
u_prim_buf_irq	100.00	100.00
u_prim_esc_receiver	100.00			100.00
u_prim_lc_sender	100.00	100.00				100.00
u_prim_sync_reqack_data	91.67	100.00	66.67			100.00	100.00
u_pwrmgr_sync	100.00	100.00				100.00	100.00
u_reg_cfg	88.94	92.30	72.28			91.18	100.00
u_sim_win_rsp	89.32	77.27	80.00			100.00	100.00
u_tlul_req_buf	100.00	100.00
u_tlul_rsp_buf	100.00	100.00
u_wdog_nmi_sync	100.00	100.00				100.00

Line Coverage for Module : rv_core_ibex

	Line No.	Total	Covered	Percent
TOTAL		85	80	94.12
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	216	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	348	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
ALWAYS	492	3	3	100.00
CONT_ASSIGN	512	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	514	1	1	100.00
CONT_ASSIGN	515	1	1	100.00
ALWAYS	518	8	8	100.00
CONT_ASSIGN	702	1	1	100.00
CONT_ASSIGN	702	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	708	1	1	100.00
CONT_ASSIGN	708	1	1	100.00
CONT_ASSIGN	709	1	1	100.00
CONT_ASSIGN	709	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	717	1	1	100.00
CONT_ASSIGN	718	1	1	100.00
CONT_ASSIGN	719	1	1	100.00
CONT_ASSIGN	722	1	1	100.00
CONT_ASSIGN	724	1	1	100.00
CONT_ASSIGN	726	1	1	100.00
CONT_ASSIGN	728	1	1	100.00
CONT_ASSIGN	735	1	1	100.00
CONT_ASSIGN	737	1	1	100.00
CONT_ASSIGN	739	1	1	100.00
CONT_ASSIGN	741	1	1	100.00
CONT_ASSIGN	751	1	1	100.00
CONT_ASSIGN	752	1	0	0.00
CONT_ASSIGN	753	1	1	100.00
CONT_ASSIGN	754	1	1	100.00
CONT_ASSIGN	757	1	1	100.00
CONT_ASSIGN	760	1	0	0.00
ALWAYS	792	11	11	100.00
ALWAYS	808	7	7	100.00
CONT_ASSIGN	819	1	1	100.00
CONT_ASSIGN	838	1	1	100.00
CONT_ASSIGN	839	1	1	100.00
CONT_ASSIGN	840	1	1	100.00
CONT_ASSIGN	843	1	0	0.00
CONT_ASSIGN	847	0	0
CONT_ASSIGN	886	1	1	100.00
ALWAYS	945	0	0
CONT_ASSIGN	986	1	0	0.00
CONT_ASSIGN	988	1	0	0.00
CONT_ASSIGN	990	1	1	100.00
CONT_ASSIGN	992	1	1	100.00
CONT_ASSIGN	994	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
202	1	1
203	1	1
216	1	1
217	1	1
218	1	1
225	1	1
263	1	1
265	1	1
268	1	1
342	1	1
348	1	1
363	1	1
492	1	1
493	1	1
495	1	1
512	1	1
513	1	1
514	1	1
515	1	1
518	1	1
519	1	1
520	1	1
521	1	1
522	1	1
523	1	1
524	1	1
525	1	1
			MISSING_ELSE
702	2	2
703	2	2
704	2	2
708	2	2
709	2	2
710	2	2
717	1	1
718	1	1
719	1	1
722	1	1
724	1	1
726	1	1
728	1	1
735	1	1
737	1	1
739	1	1
741	1	1
751	1	1
752	0	1
753	1	1
754	1	1
757	1	1
760	0	1
792	1	1
793	1	1
794	1	1
796	1	1
797	1	1
798	1	1
799	1	1
800	1	1
801	1	1
802	1	1
803	1	1
			MISSING_ELSE
808	1	1
809	1	1
810	1	1
811	1	1
813	1	1
814	1	1
815	1	1
819	1	1
838	1	1
839	1	1
840	1	1
843	0	1
847		unreachable
886	1	1
945		unreachable
946		unreachable
947		unreachable
948		unreachable
			==> MISSING_ELSE
986	0	1
988	0	1
990	1	1
992	1	1
994	1	1

---

Cond Coverage for Module : rv_core_ibex

	Total	Covered	Percent
Conditions	28	25	89.29
Logical	28	25	89.29
Non-Logical	0	0
Event	0	0

 LINE       216
 EXPRESSION (ibus_intg_err | dbus_intg_err | alert_major_bus)
             ------1------   ------2------   -------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T5,T6
0	0	1	Covered	T17,T113,T114
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       217
 EXPRESSION (alert_major_internal | double_fault)
             ----------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T241,T242,T243
1	0	Covered	T33,T244,T68

 LINE       348
 EXPRESSION (fatal_core_err ? Off : local_fetch_enable_q)
             -------1------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T33,T244,T241

 LINE       735
 EXPRESSION (reg2hw.alert_test.fatal_sw_err.q & reg2hw.alert_test.fatal_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T78,T245,T79
1	0	Covered	T4,T5,T6
1	1	Covered	T78,T79,T80

 LINE       737
 EXPRESSION (reg2hw.alert_test.recov_sw_err.q & reg2hw.alert_test.recov_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T78,T79,T80
1	0	Covered	T4,T5,T6
1	1	Covered	T78,T245,T79

 LINE       739
 EXPRESSION (reg2hw.alert_test.fatal_hw_err.q & reg2hw.alert_test.fatal_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T78,T245,T79
1	0	Covered	T4,T5,T6
1	1	Covered	T78,T79,T80

 LINE       741
 EXPRESSION (reg2hw.alert_test.recov_hw_err.q & reg2hw.alert_test.recov_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T78,T245,T79
1	0	Covered	T4,T5,T6
1	1	Covered	T78,T79,T80

 LINE       753
 EXPRESSION (intg_err | fatal_intg_err | fatal_core_err)
             ----1---   -------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T5,T6
0	0	1	Covered	T33,T244,T241
0	1	0	Covered	T17,T113,T114
1	0	0	Covered	T246,T247,T248

 LINE       800
 EXPRESSION (edn_req && edn_ack)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Toggle Coverage for Module : rv_core_ibex

	Total	Covered	Percent
Totals	121	90	74.38
Total Bits	1624	1400	86.21
Total Bits 0->1	812	701	86.33
Total Bits 1->0	812	699	86.08

Ports	121	90	74.38
Port Bits	1624	1400	86.21
Port Bits 0->1	812	701	86.33
Port Bits 1->0	812	699	86.08

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T6,T17,T18	Yes	T4,T5,T6	INPUT
clk_edn_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_edn_ni	Yes	Yes	T6,T17,T18	Yes	T4,T5,T6	INPUT
clk_esc_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_esc_ni	Yes	Yes	T6,T17,T18	Yes	T4,T5,T6	INPUT
rst_cpu_n_o	Yes	Yes	T6,T17,T18	Yes	T4,T5,T6	OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
hart_id_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
boot_addr_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_o.d_ready	No	No		No		OUTPUT
corei_tl_h_o.a_user.data_intg[6:0]	No	No		No		OUTPUT
corei_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
corei_tl_h_o.a_user.instr_type[3:0]	No	No		No		OUTPUT
corei_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_data[31:0]	No	No		No		OUTPUT
corei_tl_h_o.a_mask[3:0]	No	No		No		OUTPUT
corei_tl_h_o.a_address[1:0]	No	No		No		OUTPUT
corei_tl_h_o.a_address[16:2]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
corei_tl_h_o.a_address[18:17]	No	No		No		OUTPUT
corei_tl_h_o.a_address[19]	No	No		Yes	T249,T250,T251	OUTPUT
corei_tl_h_o.a_address[27:20]	No	No		No		OUTPUT
corei_tl_h_o.a_address[29:28]	Yes	Yes	*T252,*T115,*T253	Yes	T252,T115,T253	OUTPUT
corei_tl_h_o.a_address[31:30]	No	No		No		OUTPUT
corei_tl_h_o.a_source[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
corei_tl_h_o.a_source[5:3]	No	No		No		OUTPUT
corei_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_size[1:0]	No	No		No		OUTPUT
corei_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_opcode[2:0]	No	No		No		OUTPUT
corei_tl_h_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
corei_tl_h_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
corei_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_user.rsp_intg[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
corei_tl_h_i.d_user.rsp_intg[6]	No	No		No		INPUT
corei_tl_h_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_sink	No	No		No		INPUT
corei_tl_h_i.d_source[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_source[5:3]	No	No		No		INPUT
corei_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_size[0]	No	No		No		INPUT
corei_tl_h_i.d_size[1]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cored_tl_h_o.d_ready	Yes	Yes	T22,T24,T76	Yes	T22,T24,T76	OUTPUT
cored_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T76,T26,T55	Yes	T76,T26,T55	OUTPUT
cored_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_address[31:0]	Yes	Yes	T76,T26,T55	Yes	T76,T26,T55	OUTPUT
cored_tl_h_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_size[1:0]	Yes	Yes	T76,T26,T55	Yes	T76,T26,T55	OUTPUT
cored_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_opcode[1]	No	No		No		OUTPUT
cored_tl_h_o.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_error	Yes	Yes	T77,T73,T74	Yes	T77,T73,T74	INPUT
cored_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_user.rsp_intg[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_user.rsp_intg[6]	No	No		No		INPUT
cored_tl_h_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_sink	No	No		No		INPUT
cored_tl_h_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_size[1:0]	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	INPUT
cored_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
irq_software_i	Yes	Yes	T254,T255,T256	Yes	T254,T255,T256	INPUT
irq_timer_i	Yes	Yes	T257,T258,T259	Yes	T257,T258,T259	INPUT
irq_external_i	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	INPUT
esc_tx_i.esc_n	Yes	Yes	T31,T19,T27	Yes	T31,T19,T27	INPUT
esc_tx_i.esc_p	Yes	Yes	T31,T19,T27	Yes	T31,T19,T27	INPUT
esc_rx_o.resp_n	Yes	Yes	T31,T19,T27	Yes	T31,T19,T27	OUTPUT
esc_rx_o.resp_p	Yes	Yes	T31,T19,T27	Yes	T31,T19,T27	OUTPUT
nmi_wdog_i	Yes	Yes	T143,T260,T261	Yes	T143,T260,T261	INPUT
debug_req_i	Yes	Yes	T20,T25,T21	Yes	T20,T25,T21	INPUT
crash_dump_o.current.exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.last_data_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.next_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.current_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_valid	Unreachable	Unreachable		Unreachable		OUTPUT
lc_cpu_en_i[3:0]	Yes	Yes	T6,T17,T18	Yes	T4,T5,T6	INPUT
pwrmgr_cpu_en_i[3:0]	Yes	Yes	T6,T17,T31	Yes	T4,T5,T6	INPUT
pwrmgr_o.core_sleeping	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_user.cmd_intg[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_user.cmd_intg[1]	No	No		No		INPUT
cfg_tl_d_i.a_user.cmd_intg[6:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_user.instr_type[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_user.instr_type[2:1]	No	No		No		INPUT
cfg_tl_d_i.a_user.instr_type[3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_address[1:0]	No	No		No		INPUT
cfg_tl_d_i.a_address[7:2]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_address[15:8]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[20:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[24]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_source[1:0]	Yes	Yes	*T25,*T4,*T5	Yes	T25,T4,T5	INPUT
cfg_tl_d_i.a_source[5:2]	No	No		No		INPUT
cfg_tl_d_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_size[0]	No	No		No		INPUT
cfg_tl_d_i.a_size[1]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_opcode[1:0]	No	No		No		INPUT
cfg_tl_d_i.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cfg_tl_d_o.d_error	No	No		No		OUTPUT
cfg_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T30	Yes	T4,T5,T30	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[1:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
cfg_tl_d_o.d_user.rsp_intg[5:4]	Yes	Yes	T6,T17,*T18	Yes	T4,T5,T6	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
cfg_tl_d_o.d_data[31:0]	Yes	Yes	T4,T5,T30	Yes	T4,T5,T30	OUTPUT
cfg_tl_d_o.d_sink	No	No		No		OUTPUT
cfg_tl_d_o.d_source[0]	No	No		Yes	T25	OUTPUT
cfg_tl_d_o.d_source[1]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
cfg_tl_d_o.d_source[5:2]	No	No		No		OUTPUT
cfg_tl_d_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_size[0]	No	No		No		OUTPUT
cfg_tl_d_o.d_size[1]	Yes	Yes	T6,T17,T18	Yes	T4,T5,T6	OUTPUT
cfg_tl_d_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
cfg_tl_d_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_o.edn_req	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_i.edn_bus[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
edn_i.edn_fips	Yes	Yes	T154,T155,T262	Yes	T99,T101,T154	INPUT
edn_i.edn_ack	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_otp_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_otp_ni	Yes	Yes	T6,T17,T18	Yes	T4,T5,T6	INPUT
icache_otp_key_o.req	Yes	Yes	T115,T194,T195	Yes	T115,T194,T195	OUTPUT
icache_otp_key_i.seed_valid	Yes	Yes	T6,T17,T18	Yes	T4,T5,T6	INPUT
icache_otp_key_i.nonce[127:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
icache_otp_key_i.key[127:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
icache_otp_key_i.ack	Yes	Yes	T194,T195,T196	Yes	T194,T195,T196	INPUT
fpga_info_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T27,T29,T73	Yes	T27,T29,T73	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T27,T29,T128	Yes	T27,T29,T128	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T27,T29,T128	Yes	T27,T29,T128	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T27,T29,T128	Yes	T27,T29,T128	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T27,T29,T128	Yes	T27,T29,T128	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T27,T29,T128	Yes	T27,T29,T128	INPUT
alert_rx_i[2].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T17,T27,T29	Yes	T17,T27,T29	INPUT
alert_rx_i[2].ping_n	Yes	Yes	T27,T29,T128	Yes	T29,T128,T263	INPUT
alert_rx_i[2].ping_p	Yes	Yes	T29,T128,T263	Yes	T27,T29,T128	INPUT
alert_rx_i[3].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[3].ack_p	Yes	Yes	T27,T29,T128	Yes	T27,T29,T128	INPUT
alert_rx_i[3].ping_n	Yes	Yes	T27,T29,T128	Yes	T27,T29,T128	INPUT
alert_rx_i[3].ping_p	Yes	Yes	T27,T29,T128	Yes	T27,T29,T128	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T27,T29,T73	Yes	T27,T29,T73	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T27,T29,T128	Yes	T27,T29,T128	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T17,T27,T29	Yes	T17,T27,T29	OUTPUT
alert_tx_o[3].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[3].alert_p	Yes	Yes	T27,T29,T128	Yes	T27,T29,T128	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : rv_core_ibex

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	348	2	2	100.00
IF	492	2	2	100.00
IF	518	3	3	100.00
IF	796	3	3	100.00
IF	808	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	348	(fatal_core_err) ? 

Branches:

-1-	Status	Tests
1	Covered	T33,T244,T241
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	492	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	518	if ((!rst_ni))
-2-:	522	if (double_fault)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T241,T242,T243
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	796	if (reg2hw.rnd_data.re)
-2-:	800	if ((edn_req && edn_ack))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T30
0	1	Covered	T4,T5,T6
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	808	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Module : rv_core_ibex

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	15	68.18
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	15	68.18

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FpvSecCmIbexFetchEnable0_A	491570711	7	0	0
FpvSecCmIbexFetchEnable1_A	491570711	24351043	0	90
FpvSecCmIbexFetchEnable2_A	491570711	65035603	0	82
FpvSecCmIbexFetchEnable3Rev_A	491570711	422047623	0	1980
FpvSecCmIbexFetchEnable3_A	491570711	422049461	0	1878
FpvSecCmIbexInstrIntgErrCheck_A	491570711	153	0	0
FpvSecCmIbexLoadRespIntgErrCheck_A	491570711	586	0	0
FpvSecCmIbexLockstepResetCountAlertCheck_A	491570711	0	0	0
FpvSecCmIbexPcMismatchCheck_A	491570711	0	0	0
FpvSecCmIbexRfEccErrCheck_A	491570711	0	0	0
FpvSecCmIbexStoreRespIntgErrCheck_A	491570711	0	0	0
FpvSecCmRegWeOnehotCheck_A	491570711	3	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A	491570711	0	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A	491570711	0	0	0
FpvSecCmRvCoreRegWeOnehotCheck_A	491570711	0	0	0
g_instr_intg_err_assert_signals.AssertConnected_A	1001	1001	0	0
g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A	1001	1001	0	0
g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A	1001	1001	0	0
g_pc_mismatch_alert_o_assert_signals.AssertConnected_A	1001	1001	0	0
g_rf_ecc_err_comb_assert_signals.AssertConnected_A	1001	1001	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A	491570711	172	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A	491570711	191	0	0

FpvSecCmIbexFetchEnable0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	7	0	0
T2	159234	0	0	0
T154	168610	0	0	0
T241	220085	1	0	0
T242	0	1	0	0
T243	0	1	0	0
T264	0	1	0	0
T265	0	1	0	0
T266	0	1	0	0
T267	0	1	0	0
T268	224093	0	0	0
T269	175235	0	0	0
T270	162359	0	0	0
T271	100008	0	0	0
T272	157010	0	0	0
T273	133809	0	0	0
T274	619996	0	0	0

FpvSecCmIbexFetchEnable1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	24351043	0	90
T4	142498	9919	0	0
T5	122533	9927	0	0
T6	737721	19842	0	0
T17	214832	19858	0	0
T22	0	0	0	2
T24	0	0	0	2
T30	283999	9931	0	0
T31	161782	9919	0	0
T58	112394	9919	0	0
T68	0	0	0	2
T70	0	0	0	2
T71	0	0	0	2
T93	472771	9919	0	0
T95	93145	9927	0	0
T96	95721	9919	0	0
T185	0	0	0	2
T190	0	0	0	2
T275	0	0	0	2
T276	0	0	0	2
T277	0	0	0	2

FpvSecCmIbexFetchEnable2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	65035603	0	82
T4	142498	34771	0	0
T5	122533	34775	0	0
T6	737721	69554	0	0
T17	214832	69555	0	0
T22	0	0	0	2
T24	0	0	0	2
T30	283999	34775	0	0
T31	161782	38799	0	0
T58	112394	34775	0	0
T68	0	0	0	2
T70	0	0	0	2
T76	0	0	0	2
T82	0	0	0	2
T93	472771	34775	0	0
T95	93145	34775	0	0
T96	95721	34771	0	0
T190	0	0	0	2
T275	0	0	0	2
T276	0	0	0	2
T278	0	0	0	2

FpvSecCmIbexFetchEnable3Rev_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	422047623	0	1980
T4	142498	139015	0	2
T5	122533	119049	0	2
T6	737721	668055	0	2
T17	214832	145155	0	2
T30	283999	249159	0	2
T31	161782	122924	0	2
T58	112394	77565	0	2
T93	472771	437942	0	2
T95	93145	58309	0	2
T96	95721	60893	0	2

FpvSecCmIbexFetchEnable3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	422049461	0	1878
T4	142498	139015	0	2
T5	122533	119049	0	2
T6	737721	668057	0	2
T17	214832	145157	0	2
T30	283999	249160	0	2
T31	161782	122926	0	2
T58	112394	77566	0	2
T93	472771	437943	0	2
T95	93145	58310	0	2
T96	95721	60893	0	2

FpvSecCmIbexInstrIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	153	0	0
T48	100827	0	0	0
T119	595213	0	0	0
T133	129678	0	0	0
T149	203852	0	0	0
T279	317390	76	0	0
T280	0	1	0	0
T281	0	76	0	0
T282	159842	0	0	0
T283	537649	0	0	0
T284	224977	0	0	0
T285	123489	0	0	0
T286	228584	0	0	0

FpvSecCmIbexLoadRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	586	0	0
T1	617723	0	0	0
T17	214832	32	0	0
T18	465858	0	0	0
T19	287139	0	0	0
T27	137787	0	0	0
T31	161782	0	0	0
T32	232228	0	0	0
T45	106208	0	0	0
T93	472771	0	0	0
T111	165702	0	0	0
T113	0	32	0	0
T114	0	32	0	0
T252	0	1	0	0
T253	0	1	0	0
T287	0	32	0	0
T288	0	31	0	0
T289	0	98	0	0
T290	0	32	0	0
T291	0	31	0	0

FpvSecCmIbexLockstepResetCountAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	0	0	0

FpvSecCmIbexPcMismatchCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	0	0	0

FpvSecCmIbexRfEccErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	0	0	0

FpvSecCmIbexStoreRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	3	0	0
T152	612464	0	0	0
T165	228536	0	0	0
T175	423303	0	0	0
T190	87099	0	0	0
T246	145539	1	0	0
T247	0	1	0	0
T248	0	1	0	0
T287	191350	0	0	0
T292	105279	0	0	0
T293	158092	0	0	0
T294	105925	0	0	0
T295	70526	0	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	0	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	0	0	0

FpvSecCmRvCoreRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	0	0	0

g_instr_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1001	1001	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T58	1	1	0	0
T93	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0

g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1001	1001	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T58	1	1	0	0
T93	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0

g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1001	1001	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T58	1	1	0	0
T93	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0

g_pc_mismatch_alert_o_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1001	1001	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T58	1	1	0	0
T93	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0

g_rf_ecc_err_comb_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1001	1001	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T58	1	1	0	0
T93	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	172	0	0
T59	91867	0	0	0
T121	515132	0	0	0
T122	298587	0	0	0
T167	242156	0	0	0
T194	88508	32	0	0
T195	0	29	0	0
T196	0	13	0	0
T199	155039	0	0	0
T296	0	30	0	0
T297	0	33	0	0
T298	0	35	0	0
T299	398187	0	0	0
T300	525963	0	0	0
T301	38311	0	0	0
T302	580275	0	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	191	0	0
T41	221143	0	0	0
T78	104396	0	0	0
T109	124200	0	0	0
T115	350701	16	0	0
T116	0	16	0	0
T126	110634	0	0	0
T130	80769	0	0	0
T194	0	42	0	0
T195	0	7	0	0
T196	0	3	0	0
T296	0	7	0	0
T297	0	42	0	0
T298	0	42	0	0
T303	0	16	0	0
T304	371548	0	0	0
T305	191358	0	0	0
T306	131806	0	0	0
T307	161912	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Line No.	Total	Covered	Percent
TOTAL		85	80	94.12
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	216	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	348	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
ALWAYS	492	3	3	100.00
CONT_ASSIGN	512	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	514	1	1	100.00
CONT_ASSIGN	515	1	1	100.00
ALWAYS	518	8	8	100.00
CONT_ASSIGN	702	1	1	100.00
CONT_ASSIGN	702	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	708	1	1	100.00
CONT_ASSIGN	708	1	1	100.00
CONT_ASSIGN	709	1	1	100.00
CONT_ASSIGN	709	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	717	1	1	100.00
CONT_ASSIGN	718	1	1	100.00
CONT_ASSIGN	719	1	1	100.00
CONT_ASSIGN	722	1	1	100.00
CONT_ASSIGN	724	1	1	100.00
CONT_ASSIGN	726	1	1	100.00
CONT_ASSIGN	728	1	1	100.00
CONT_ASSIGN	735	1	1	100.00
CONT_ASSIGN	737	1	1	100.00
CONT_ASSIGN	739	1	1	100.00
CONT_ASSIGN	741	1	1	100.00
CONT_ASSIGN	751	1	1	100.00
CONT_ASSIGN	752	1	0	0.00
CONT_ASSIGN	753	1	1	100.00
CONT_ASSIGN	754	1	1	100.00
CONT_ASSIGN	757	1	1	100.00
CONT_ASSIGN	760	1	0	0.00
ALWAYS	792	11	11	100.00
ALWAYS	808	7	7	100.00
CONT_ASSIGN	819	1	1	100.00
CONT_ASSIGN	838	1	1	100.00
CONT_ASSIGN	839	1	1	100.00
CONT_ASSIGN	840	1	1	100.00
CONT_ASSIGN	843	1	0	0.00
CONT_ASSIGN	847	0	0
CONT_ASSIGN	886	1	1	100.00
ALWAYS	945	0	0
CONT_ASSIGN	986	1	0	0.00
CONT_ASSIGN	988	1	0	0.00
CONT_ASSIGN	990	1	1	100.00
CONT_ASSIGN	992	1	1	100.00
CONT_ASSIGN	994	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
202	1	1
203	1	1
216	1	1
217	1	1
218	1	1
225	1	1
263	1	1
265	1	1
268	1	1
342	1	1
348	1	1
363	1	1
492	1	1
493	1	1
495	1	1
512	1	1
513	1	1
514	1	1
515	1	1
518	1	1
519	1	1
520	1	1
521	1	1
522	1	1
523	1	1
524	1	1
525	1	1
			MISSING_ELSE
702	2	2
703	2	2
704	2	2
708	2	2
709	2	2
710	2	2
717	1	1
718	1	1
719	1	1
722	1	1
724	1	1
726	1	1
728	1	1
735	1	1
737	1	1
739	1	1
741	1	1
751	1	1
752	0	1
753	1	1
754	1	1
757	1	1
760	0	1
792	1	1
793	1	1
794	1	1
796	1	1
797	1	1
798	1	1
799	1	1
800	1	1
801	1	1
802	1	1
803	1	1
			MISSING_ELSE
808	1	1
809	1	1
810	1	1
811	1	1
813	1	1
814	1	1
815	1	1
819	1	1
838	1	1
839	1	1
840	1	1
843	0	1
847		unreachable
886	1	1
945		unreachable
946		unreachable
947		unreachable
948		unreachable
			==> MISSING_ELSE
986	0	1
988	0	1
990	1	1
992	1	1
994	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Total	Covered	Percent
Conditions	28	25	89.29
Logical	28	25	89.29
Non-Logical	0	0
Event	0	0

 LINE       216
 EXPRESSION (ibus_intg_err | dbus_intg_err | alert_major_bus)
             ------1------   ------2------   -------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T5,T6
0	0	1	Covered	T17,T113,T114
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       217
 EXPRESSION (alert_major_internal | double_fault)
             ----------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T241,T242,T243
1	0	Covered	T33,T244,T68

 LINE       348
 EXPRESSION (fatal_core_err ? Off : local_fetch_enable_q)
             -------1------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T33,T244,T241

 LINE       735
 EXPRESSION (reg2hw.alert_test.fatal_sw_err.q & reg2hw.alert_test.fatal_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T78,T245,T79
1	0	Covered	T4,T5,T6
1	1	Covered	T78,T79,T80

 LINE       737
 EXPRESSION (reg2hw.alert_test.recov_sw_err.q & reg2hw.alert_test.recov_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T78,T79,T80
1	0	Covered	T4,T5,T6
1	1	Covered	T78,T245,T79

 LINE       739
 EXPRESSION (reg2hw.alert_test.fatal_hw_err.q & reg2hw.alert_test.fatal_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T78,T245,T79
1	0	Covered	T4,T5,T6
1	1	Covered	T78,T79,T80

 LINE       741
 EXPRESSION (reg2hw.alert_test.recov_hw_err.q & reg2hw.alert_test.recov_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T78,T245,T79
1	0	Covered	T4,T5,T6
1	1	Covered	T78,T79,T80

 LINE       753
 EXPRESSION (intg_err | fatal_intg_err | fatal_core_err)
             ----1---   -------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T5,T6
0	0	1	Covered	T33,T244,T241
0	1	0	Covered	T17,T113,T114
1	0	0	Covered	T246,T247,T248

 LINE       800
 EXPRESSION (edn_req && edn_ack)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Total	Covered	Percent
Totals	117	90	76.92
Total Bits	1604	1400	87.28
Total Bits 0->1	802	701	87.41
Total Bits 1->0	802	699	87.16

Ports	117	90	76.92
Port Bits	1604	1400	87.28
Port Bits 0->1	802	701	87.41
Port Bits 1->0	802	699	87.16

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T6,T17,T18	Yes	T4,T5,T6	INPUT
clk_edn_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_edn_ni	Yes	Yes	T6,T17,T18	Yes	T4,T5,T6	INPUT
clk_esc_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_esc_ni	Yes	Yes	T6,T17,T18	Yes	T4,T5,T6	INPUT
rst_cpu_n_o	Yes	Yes	T6,T17,T18	Yes	T4,T5,T6	OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.rf_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
hart_id_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
boot_addr_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_o.d_ready	No	No		No		OUTPUT
corei_tl_h_o.a_user.data_intg[6:0]	No	No		No		OUTPUT
corei_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
corei_tl_h_o.a_user.instr_type[3:0]	No	No		No		OUTPUT
corei_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_data[31:0]	No	No		No		OUTPUT
corei_tl_h_o.a_mask[3:0]	No	No		No		OUTPUT
corei_tl_h_o.a_address[1:0]	No	No		No		OUTPUT
corei_tl_h_o.a_address[16:2]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
corei_tl_h_o.a_address[18:17]	No	No		No		OUTPUT
corei_tl_h_o.a_address[19]	No	No		Yes	T249,T250,T251	OUTPUT
corei_tl_h_o.a_address[27:20]	No	No		No		OUTPUT
corei_tl_h_o.a_address[29:28]	Yes	Yes	*T252,*T115,*T253	Yes	T252,T115,T253	OUTPUT
corei_tl_h_o.a_address[31:30]	No	No		No		OUTPUT
corei_tl_h_o.a_source[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
corei_tl_h_o.a_source[5:3]	No	No		No		OUTPUT
corei_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_size[1:0]	No	No		No		OUTPUT
corei_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_opcode[2:0]	No	No		No		OUTPUT
corei_tl_h_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
corei_tl_h_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
corei_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_user.rsp_intg[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
corei_tl_h_i.d_user.rsp_intg[6]	No	No		No		INPUT
corei_tl_h_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_sink	No	No		No		INPUT
corei_tl_h_i.d_source[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_source[5:3]	No	No		No		INPUT
corei_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_size[0]	No	No		No		INPUT
corei_tl_h_i.d_size[1]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cored_tl_h_o.d_ready	Yes	Yes	T22,T24,T76	Yes	T22,T24,T76	OUTPUT
cored_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T76,T26,T55	Yes	T76,T26,T55	OUTPUT
cored_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_address[31:0]	Yes	Yes	T76,T26,T55	Yes	T76,T26,T55	OUTPUT
cored_tl_h_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_size[1:0]	Yes	Yes	T76,T26,T55	Yes	T76,T26,T55	OUTPUT
cored_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_opcode[1]	No	No		No		OUTPUT
cored_tl_h_o.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_error	Yes	Yes	T77,T73,T74	Yes	T77,T73,T74	INPUT
cored_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_user.rsp_intg[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_user.rsp_intg[6]	No	No		No		INPUT
cored_tl_h_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_sink	No	No		No		INPUT
cored_tl_h_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_size[1:0]	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	INPUT
cored_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
irq_software_i	Yes	Yes	T254,T255,T256	Yes	T254,T255,T256	INPUT
irq_timer_i	Yes	Yes	T257,T258,T259	Yes	T257,T258,T259	INPUT
irq_external_i	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	INPUT
esc_tx_i.esc_n	Yes	Yes	T31,T19,T27	Yes	T31,T19,T27	INPUT
esc_tx_i.esc_p	Yes	Yes	T31,T19,T27	Yes	T31,T19,T27	INPUT
esc_rx_o.resp_n	Yes	Yes	T31,T19,T27	Yes	T31,T19,T27	OUTPUT
esc_rx_o.resp_p	Yes	Yes	T31,T19,T27	Yes	T31,T19,T27	OUTPUT
nmi_wdog_i	Yes	Yes	T143,T260,T261	Yes	T143,T260,T261	INPUT
debug_req_i	Yes	Yes	T20,T25,T21	Yes	T20,T25,T21	INPUT
crash_dump_o.current.exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.last_data_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.next_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.current_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_valid	Unreachable	Unreachable		Unreachable		OUTPUT
lc_cpu_en_i[3:0]	Yes	Yes	T6,T17,T18	Yes	T4,T5,T6	INPUT
pwrmgr_cpu_en_i[3:0]	Yes	Yes	T6,T17,T31	Yes	T4,T5,T6	INPUT
pwrmgr_o.core_sleeping	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_user.cmd_intg[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_user.cmd_intg[1]	No	No		No		INPUT
cfg_tl_d_i.a_user.cmd_intg[6:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_user.instr_type[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_user.instr_type[2:1]	No	No		No		INPUT
cfg_tl_d_i.a_user.instr_type[3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_address[1:0]	No	No		No		INPUT
cfg_tl_d_i.a_address[7:2]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_address[15:8]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[20:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[24]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_source[1:0]	Yes	Yes	*T25,*T4,*T5	Yes	T25,T4,T5	INPUT
cfg_tl_d_i.a_source[5:2]	No	No		No		INPUT
cfg_tl_d_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_size[0]	No	No		No		INPUT
cfg_tl_d_i.a_size[1]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_opcode[1:0]	No	No		No		INPUT
cfg_tl_d_i.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cfg_tl_d_o.d_error	No	No		No		OUTPUT
cfg_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T30	Yes	T4,T5,T30	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[1:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
cfg_tl_d_o.d_user.rsp_intg[5:4]	Yes	Yes	T6,T17,*T18	Yes	T4,T5,T6	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
cfg_tl_d_o.d_data[31:0]	Yes	Yes	T4,T5,T30	Yes	T4,T5,T30	OUTPUT
cfg_tl_d_o.d_sink	No	No		No		OUTPUT
cfg_tl_d_o.d_source[0]	No	No		Yes	T25	OUTPUT
cfg_tl_d_o.d_source[1]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
cfg_tl_d_o.d_source[5:2]	No	No		No		OUTPUT
cfg_tl_d_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_size[0]	No	No		No		OUTPUT
cfg_tl_d_o.d_size[1]	Yes	Yes	T6,T17,T18	Yes	T4,T5,T6	OUTPUT
cfg_tl_d_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
cfg_tl_d_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_o.edn_req	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_i.edn_bus[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
edn_i.edn_fips	Yes	Yes	T154,T155,T262	Yes	T99,T101,T154	INPUT
edn_i.edn_ack	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_otp_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_otp_ni	Yes	Yes	T6,T17,T18	Yes	T4,T5,T6	INPUT
icache_otp_key_o.req	Yes	Yes	T115,T194,T195	Yes	T115,T194,T195	OUTPUT
icache_otp_key_i.seed_valid	Yes	Yes	T6,T17,T18	Yes	T4,T5,T6	INPUT
icache_otp_key_i.nonce[127:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
icache_otp_key_i.key[127:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
icache_otp_key_i.ack	Yes	Yes	T194,T195,T196	Yes	T194,T195,T196	INPUT
fpga_info_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T27,T29,T73	Yes	T27,T29,T73	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T27,T29,T128	Yes	T27,T29,T128	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T27,T29,T128	Yes	T27,T29,T128	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T27,T29,T128	Yes	T27,T29,T128	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T27,T29,T128	Yes	T27,T29,T128	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T27,T29,T128	Yes	T27,T29,T128	INPUT
alert_rx_i[2].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T17,T27,T29	Yes	T17,T27,T29	INPUT
alert_rx_i[2].ping_n	Yes	Yes	T27,T29,T128	Yes	T29,T128,T263	INPUT
alert_rx_i[2].ping_p	Yes	Yes	T29,T128,T263	Yes	T27,T29,T128	INPUT
alert_rx_i[3].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[3].ack_p	Yes	Yes	T27,T29,T128	Yes	T27,T29,T128	INPUT
alert_rx_i[3].ping_n	Yes	Yes	T27,T29,T128	Yes	T27,T29,T128	INPUT
alert_rx_i[3].ping_p	Yes	Yes	T27,T29,T128	Yes	T27,T29,T128	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T27,T29,T73	Yes	T27,T29,T73	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T27,T29,T128	Yes	T27,T29,T128	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T17,T27,T29	Yes	T17,T27,T29	OUTPUT
alert_tx_o[3].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[3].alert_p	Yes	Yes	T27,T29,T128	Yes	T27,T29,T128	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	348	2	2	100.00
IF	492	2	2	100.00
IF	518	3	3	100.00
IF	796	3	3	100.00
IF	808	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	348	(fatal_core_err) ? 

Branches:

-1-	Status	Tests
1	Covered	T33,T244,T241
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	492	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	518	if ((!rst_ni))
-2-:	522	if (double_fault)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T241,T242,T243
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	796	if (reg2hw.rnd_data.re)
-2-:	800	if ((edn_req && edn_ack))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T30
0	1	Covered	T4,T5,T6
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	808	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	15	68.18
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	15	68.18

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FpvSecCmIbexFetchEnable0_A	491570711	7	0	0
FpvSecCmIbexFetchEnable1_A	491570711	24351043	0	90
FpvSecCmIbexFetchEnable2_A	491570711	65035603	0	82
FpvSecCmIbexFetchEnable3Rev_A	491570711	422047623	0	1980
FpvSecCmIbexFetchEnable3_A	491570711	422049461	0	1878
FpvSecCmIbexInstrIntgErrCheck_A	491570711	153	0	0
FpvSecCmIbexLoadRespIntgErrCheck_A	491570711	586	0	0
FpvSecCmIbexLockstepResetCountAlertCheck_A	491570711	0	0	0
FpvSecCmIbexPcMismatchCheck_A	491570711	0	0	0
FpvSecCmIbexRfEccErrCheck_A	491570711	0	0	0
FpvSecCmIbexStoreRespIntgErrCheck_A	491570711	0	0	0
FpvSecCmRegWeOnehotCheck_A	491570711	3	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A	491570711	0	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A	491570711	0	0	0
FpvSecCmRvCoreRegWeOnehotCheck_A	491570711	0	0	0
g_instr_intg_err_assert_signals.AssertConnected_A	1001	1001	0	0
g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A	1001	1001	0	0
g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A	1001	1001	0	0
g_pc_mismatch_alert_o_assert_signals.AssertConnected_A	1001	1001	0	0
g_rf_ecc_err_comb_assert_signals.AssertConnected_A	1001	1001	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A	491570711	172	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A	491570711	191	0	0

FpvSecCmIbexFetchEnable0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	7	0	0
T2	159234	0	0	0
T154	168610	0	0	0
T241	220085	1	0	0
T242	0	1	0	0
T243	0	1	0	0
T264	0	1	0	0
T265	0	1	0	0
T266	0	1	0	0
T267	0	1	0	0
T268	224093	0	0	0
T269	175235	0	0	0
T270	162359	0	0	0
T271	100008	0	0	0
T272	157010	0	0	0
T273	133809	0	0	0
T274	619996	0	0	0

FpvSecCmIbexFetchEnable1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	24351043	0	90
T4	142498	9919	0	0
T5	122533	9927	0	0
T6	737721	19842	0	0
T17	214832	19858	0	0
T22	0	0	0	2
T24	0	0	0	2
T30	283999	9931	0	0
T31	161782	9919	0	0
T58	112394	9919	0	0
T68	0	0	0	2
T70	0	0	0	2
T71	0	0	0	2
T93	472771	9919	0	0
T95	93145	9927	0	0
T96	95721	9919	0	0
T185	0	0	0	2
T190	0	0	0	2
T275	0	0	0	2
T276	0	0	0	2
T277	0	0	0	2

FpvSecCmIbexFetchEnable2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	65035603	0	82
T4	142498	34771	0	0
T5	122533	34775	0	0
T6	737721	69554	0	0
T17	214832	69555	0	0
T22	0	0	0	2
T24	0	0	0	2
T30	283999	34775	0	0
T31	161782	38799	0	0
T58	112394	34775	0	0
T68	0	0	0	2
T70	0	0	0	2
T76	0	0	0	2
T82	0	0	0	2
T93	472771	34775	0	0
T95	93145	34775	0	0
T96	95721	34771	0	0
T190	0	0	0	2
T275	0	0	0	2
T276	0	0	0	2
T278	0	0	0	2

FpvSecCmIbexFetchEnable3Rev_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	422047623	0	1980
T4	142498	139015	0	2
T5	122533	119049	0	2
T6	737721	668055	0	2
T17	214832	145155	0	2
T30	283999	249159	0	2
T31	161782	122924	0	2
T58	112394	77565	0	2
T93	472771	437942	0	2
T95	93145	58309	0	2
T96	95721	60893	0	2

FpvSecCmIbexFetchEnable3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	422049461	0	1878
T4	142498	139015	0	2
T5	122533	119049	0	2
T6	737721	668057	0	2
T17	214832	145157	0	2
T30	283999	249160	0	2
T31	161782	122926	0	2
T58	112394	77566	0	2
T93	472771	437943	0	2
T95	93145	58310	0	2
T96	95721	60893	0	2

FpvSecCmIbexInstrIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	153	0	0
T48	100827	0	0	0
T119	595213	0	0	0
T133	129678	0	0	0
T149	203852	0	0	0
T279	317390	76	0	0
T280	0	1	0	0
T281	0	76	0	0
T282	159842	0	0	0
T283	537649	0	0	0
T284	224977	0	0	0
T285	123489	0	0	0
T286	228584	0	0	0

FpvSecCmIbexLoadRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	586	0	0
T1	617723	0	0	0
T17	214832	32	0	0
T18	465858	0	0	0
T19	287139	0	0	0
T27	137787	0	0	0
T31	161782	0	0	0
T32	232228	0	0	0
T45	106208	0	0	0
T93	472771	0	0	0
T111	165702	0	0	0
T113	0	32	0	0
T114	0	32	0	0
T252	0	1	0	0
T253	0	1	0	0
T287	0	32	0	0
T288	0	31	0	0
T289	0	98	0	0
T290	0	32	0	0
T291	0	31	0	0

FpvSecCmIbexLockstepResetCountAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	0	0	0

FpvSecCmIbexPcMismatchCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	0	0	0

FpvSecCmIbexRfEccErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	0	0	0

FpvSecCmIbexStoreRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	3	0	0
T152	612464	0	0	0
T165	228536	0	0	0
T175	423303	0	0	0
T190	87099	0	0	0
T246	145539	1	0	0
T247	0	1	0	0
T248	0	1	0	0
T287	191350	0	0	0
T292	105279	0	0	0
T293	158092	0	0	0
T294	105925	0	0	0
T295	70526	0	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	0	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	0	0	0

FpvSecCmRvCoreRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	0	0	0

g_instr_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1001	1001	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T58	1	1	0	0
T93	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0

g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1001	1001	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T58	1	1	0	0
T93	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0

g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1001	1001	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T58	1	1	0	0
T93	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0

g_pc_mismatch_alert_o_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1001	1001	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T58	1	1	0	0
T93	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0

g_rf_ecc_err_comb_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1001	1001	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T58	1	1	0	0
T93	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	172	0	0
T59	91867	0	0	0
T121	515132	0	0	0
T122	298587	0	0	0
T167	242156	0	0	0
T194	88508	32	0	0
T195	0	29	0	0
T196	0	13	0	0
T199	155039	0	0	0
T296	0	30	0	0
T297	0	33	0	0
T298	0	35	0	0
T299	398187	0	0	0
T300	525963	0	0	0
T301	38311	0	0	0
T302	580275	0	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	191	0	0
T41	221143	0	0	0
T78	104396	0	0	0
T109	124200	0	0	0
T115	350701	16	0	0
T116	0	16	0	0
T126	110634	0	0	0
T130	80769	0	0	0
T194	0	42	0	0
T195	0	7	0	0
T196	0	3	0	0
T296	0	7	0	0
T297	0	42	0	0
T298	0	42	0	0
T303	0	16	0	0
T304	371548	0	0	0
T305	191358	0	0	0
T306	131806	0	0	0
T307	161912	0	0	0