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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 95.48 94.18 95.43 94.99 96.65 99.51


Total test records in report: 2900
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T124 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1862513046 Jun 10 08:23:15 PM PDT 24 Jun 10 08:33:40 PM PDT 24 4060031848 ps
T217 /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.956331775 Jun 10 08:44:11 PM PDT 24 Jun 10 09:09:32 PM PDT 24 8008483828 ps
T66 /workspace/coverage/default/0.chip_tap_straps_testunlock0.3151881099 Jun 10 08:19:51 PM PDT 24 Jun 10 08:25:20 PM PDT 24 4036194620 ps
T283 /workspace/coverage/default/1.chip_sw_kmac_entropy.2558577563 Jun 10 08:25:51 PM PDT 24 Jun 10 08:30:14 PM PDT 24 2648206328 ps
T284 /workspace/coverage/default/0.chip_sw_flash_ctrl_access.231109661 Jun 10 08:18:04 PM PDT 24 Jun 10 08:32:39 PM PDT 24 5400618950 ps
T285 /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.2816011734 Jun 10 08:38:44 PM PDT 24 Jun 10 09:21:54 PM PDT 24 11307054791 ps
T286 /workspace/coverage/default/1.chip_tap_straps_dev.2086580859 Jun 10 08:27:50 PM PDT 24 Jun 10 08:29:58 PM PDT 24 2494423917 ps
T288 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.234014601 Jun 10 08:27:19 PM PDT 24 Jun 10 09:25:06 PM PDT 24 13999526305 ps
T781 /workspace/coverage/default/73.chip_sw_all_escalation_resets.1993676442 Jun 10 08:49:39 PM PDT 24 Jun 10 08:58:04 PM PDT 24 5130911480 ps
T202 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.2270073137 Jun 10 08:25:57 PM PDT 24 Jun 10 08:31:00 PM PDT 24 2800608362 ps
T840 /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.2896045604 Jun 10 08:47:54 PM PDT 24 Jun 10 08:55:19 PM PDT 24 3554333980 ps
T978 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3583716707 Jun 10 08:20:18 PM PDT 24 Jun 10 08:51:09 PM PDT 24 16560567466 ps
T826 /workspace/coverage/default/46.chip_sw_all_escalation_resets.3425123923 Jun 10 08:47:06 PM PDT 24 Jun 10 08:56:55 PM PDT 24 5518720916 ps
T245 /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.1159265714 Jun 10 08:44:34 PM PDT 24 Jun 10 08:56:52 PM PDT 24 11873916857 ps
T979 /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.1779154676 Jun 10 08:31:49 PM PDT 24 Jun 10 08:35:50 PM PDT 24 2638179480 ps
T361 /workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.633924452 Jun 10 08:19:00 PM PDT 24 Jun 10 08:25:08 PM PDT 24 4265983162 ps
T980 /workspace/coverage/default/0.chip_sw_hmac_enc_idle.3144658434 Jun 10 08:20:09 PM PDT 24 Jun 10 08:23:39 PM PDT 24 2625485288 ps
T24 /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.2882285447 Jun 10 08:19:53 PM PDT 24 Jun 10 08:25:41 PM PDT 24 2732632474 ps
T981 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.2235315801 Jun 10 08:31:48 PM PDT 24 Jun 10 08:42:11 PM PDT 24 4200593788 ps
T982 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.71120492 Jun 10 08:20:03 PM PDT 24 Jun 10 08:31:35 PM PDT 24 4101281784 ps
T983 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.2852598772 Jun 10 08:39:25 PM PDT 24 Jun 10 08:44:54 PM PDT 24 2809938590 ps
T984 /workspace/coverage/default/0.chip_sw_otbn_smoketest.4286270039 Jun 10 08:23:16 PM PDT 24 Jun 10 08:45:59 PM PDT 24 6177513728 ps
T985 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3851685666 Jun 10 08:33:10 PM PDT 24 Jun 10 08:46:12 PM PDT 24 4154785500 ps
T986 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1302831630 Jun 10 08:30:10 PM PDT 24 Jun 10 08:43:14 PM PDT 24 4532345970 ps
T246 /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.4009847976 Jun 10 08:45:17 PM PDT 24 Jun 10 08:51:35 PM PDT 24 7125476482 ps
T230 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.3632276646 Jun 10 08:18:27 PM PDT 24 Jun 10 08:42:14 PM PDT 24 6485790990 ps
T987 /workspace/coverage/default/0.chip_sw_uart_smoketest.2851801634 Jun 10 08:22:13 PM PDT 24 Jun 10 08:26:43 PM PDT 24 2495862872 ps
T988 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1310774581 Jun 10 08:26:54 PM PDT 24 Jun 10 09:50:17 PM PDT 24 23304287698 ps
T233 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.3844249371 Jun 10 08:28:06 PM PDT 24 Jun 10 08:55:40 PM PDT 24 8295136389 ps
T468 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.1325133911 Jun 10 08:42:07 PM PDT 24 Jun 10 09:55:00 PM PDT 24 21047837694 ps
T789 /workspace/coverage/default/99.chip_sw_all_escalation_resets.3401417310 Jun 10 08:50:53 PM PDT 24 Jun 10 08:58:24 PM PDT 24 6131101832 ps
T331 /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.720597334 Jun 10 08:29:27 PM PDT 24 Jun 10 08:34:38 PM PDT 24 3355033764 ps
T209 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.269059620 Jun 10 08:19:53 PM PDT 24 Jun 10 08:56:33 PM PDT 24 8794236568 ps
T228 /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.2705351656 Jun 10 08:40:42 PM PDT 24 Jun 10 09:12:50 PM PDT 24 9077854560 ps
T173 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.2502619777 Jun 10 08:34:26 PM PDT 24 Jun 10 10:12:22 PM PDT 24 47928585964 ps
T782 /workspace/coverage/default/89.chip_sw_all_escalation_resets.2662343029 Jun 10 08:50:56 PM PDT 24 Jun 10 09:01:33 PM PDT 24 5463407810 ps
T758 /workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.1001399008 Jun 10 08:19:44 PM PDT 24 Jun 10 08:37:18 PM PDT 24 7934699932 ps
T337 /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.1605836614 Jun 10 08:38:42 PM PDT 24 Jun 10 08:57:46 PM PDT 24 9151094558 ps
T554 /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.85414903 Jun 10 08:25:52 PM PDT 24 Jun 10 08:41:35 PM PDT 24 4910076832 ps
T367 /workspace/coverage/default/1.chip_sw_pattgen_ios.1572814667 Jun 10 08:23:36 PM PDT 24 Jun 10 08:28:39 PM PDT 24 3035071414 ps
T989 /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.326034673 Jun 10 08:32:29 PM PDT 24 Jun 10 08:54:06 PM PDT 24 8153430216 ps
T990 /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.817918342 Jun 10 08:44:38 PM PDT 24 Jun 10 09:03:04 PM PDT 24 11990975008 ps
T991 /workspace/coverage/default/0.chip_sw_example_concurrency.490213225 Jun 10 08:17:11 PM PDT 24 Jun 10 08:20:46 PM PDT 24 2658895720 ps
T85 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.1058716558 Jun 10 08:25:36 PM PDT 24 Jun 10 08:50:07 PM PDT 24 12717194000 ps
T992 /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.1435405299 Jun 10 08:25:43 PM PDT 24 Jun 10 08:31:56 PM PDT 24 7273128628 ps
T36 /workspace/coverage/default/2.chip_sw_gpio.2611254093 Jun 10 08:39:21 PM PDT 24 Jun 10 08:49:22 PM PDT 24 3934234400 ps
T37 /workspace/coverage/default/1.chip_sw_gpio.1389769834 Jun 10 08:25:11 PM PDT 24 Jun 10 08:33:56 PM PDT 24 4495072762 ps
T69 /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.1371018331 Jun 10 08:40:30 PM PDT 24 Jun 10 08:48:14 PM PDT 24 4619923970 ps
T993 /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.402714845 Jun 10 08:42:34 PM PDT 24 Jun 10 08:51:06 PM PDT 24 5541464725 ps
T994 /workspace/coverage/default/1.chip_sw_aes_smoketest.3993335948 Jun 10 08:33:41 PM PDT 24 Jun 10 08:38:12 PM PDT 24 3167314504 ps
T304 /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.2442147172 Jun 10 08:36:04 PM PDT 24 Jun 10 08:44:34 PM PDT 24 3635537008 ps
T33 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.155908691 Jun 10 08:27:19 PM PDT 24 Jun 10 08:56:53 PM PDT 24 22997724868 ps
T111 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.257455129 Jun 10 08:31:28 PM PDT 24 Jun 10 09:36:20 PM PDT 24 21279079068 ps
T790 /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.2242316906 Jun 10 08:45:37 PM PDT 24 Jun 10 08:51:58 PM PDT 24 3850512200 ps
T995 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.3733463344 Jun 10 08:20:05 PM PDT 24 Jun 10 08:23:22 PM PDT 24 2348764771 ps
T824 /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.2248235196 Jun 10 08:49:04 PM PDT 24 Jun 10 08:55:30 PM PDT 24 3724603128 ps
T996 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.892760232 Jun 10 08:33:39 PM PDT 24 Jun 10 08:51:17 PM PDT 24 6100850222 ps
T179 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.380970699 Jun 10 08:37:08 PM PDT 24 Jun 10 08:49:38 PM PDT 24 4004070311 ps
T31 /workspace/coverage/default/0.chip_sw_usbdev_config_host.3932732580 Jun 10 08:19:13 PM PDT 24 Jun 10 08:55:22 PM PDT 24 7517502248 ps
T841 /workspace/coverage/default/70.chip_sw_all_escalation_resets.573923497 Jun 10 08:49:44 PM PDT 24 Jun 10 08:57:57 PM PDT 24 5895093570 ps
T804 /workspace/coverage/default/27.chip_sw_all_escalation_resets.3028450055 Jun 10 08:46:49 PM PDT 24 Jun 10 08:57:02 PM PDT 24 5814325240 ps
T997 /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.3015858378 Jun 10 08:31:16 PM PDT 24 Jun 10 08:35:29 PM PDT 24 2454384912 ps
T362 /workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.3080336542 Jun 10 08:41:17 PM PDT 24 Jun 10 08:48:50 PM PDT 24 3960688108 ps
T998 /workspace/coverage/default/4.chip_tap_straps_dev.3250743547 Jun 10 08:43:19 PM PDT 24 Jun 10 08:46:58 PM PDT 24 3251229465 ps
T371 /workspace/coverage/default/38.chip_sw_all_escalation_resets.2385083560 Jun 10 08:47:35 PM PDT 24 Jun 10 08:56:55 PM PDT 24 3990605980 ps
T825 /workspace/coverage/default/33.chip_sw_all_escalation_resets.2377245955 Jun 10 08:49:08 PM PDT 24 Jun 10 09:00:32 PM PDT 24 5791958984 ps
T811 /workspace/coverage/default/66.chip_sw_all_escalation_resets.3585105964 Jun 10 08:49:17 PM PDT 24 Jun 10 08:57:56 PM PDT 24 5952920840 ps
T239 /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.24211502 Jun 10 08:18:27 PM PDT 24 Jun 10 10:03:09 PM PDT 24 50438807471 ps
T821 /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.3680251372 Jun 10 08:50:29 PM PDT 24 Jun 10 08:56:24 PM PDT 24 2938973400 ps
T289 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.1523575959 Jun 10 08:27:50 PM PDT 24 Jun 10 09:32:03 PM PDT 24 13847600028 ps
T3 /workspace/coverage/default/2.chip_sw_sleep_pin_retention.1094968349 Jun 10 08:32:50 PM PDT 24 Jun 10 08:39:53 PM PDT 24 4023008304 ps
T417 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.3556779411 Jun 10 08:40:32 PM PDT 24 Jun 10 09:01:47 PM PDT 24 6575504926 ps
T418 /workspace/coverage/default/2.chip_sw_aes_idle.3846074951 Jun 10 08:38:51 PM PDT 24 Jun 10 08:45:28 PM PDT 24 2975154080 ps
T419 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.4196155701 Jun 10 08:33:36 PM PDT 24 Jun 10 08:50:09 PM PDT 24 6855805294 ps
T420 /workspace/coverage/default/7.chip_sw_all_escalation_resets.3222208987 Jun 10 08:45:05 PM PDT 24 Jun 10 08:56:13 PM PDT 24 5378606832 ps
T421 /workspace/coverage/default/81.chip_sw_all_escalation_resets.585182338 Jun 10 08:53:10 PM PDT 24 Jun 10 09:05:45 PM PDT 24 5543284704 ps
T422 /workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.3221286898 Jun 10 08:37:10 PM PDT 24 Jun 10 09:06:28 PM PDT 24 8178691868 ps
T423 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.4022412364 Jun 10 08:26:50 PM PDT 24 Jun 10 08:45:47 PM PDT 24 8849325488 ps
T424 /workspace/coverage/default/72.chip_sw_all_escalation_resets.4246054415 Jun 10 08:49:49 PM PDT 24 Jun 10 08:58:13 PM PDT 24 5451368680 ps
T425 /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.1616649563 Jun 10 08:32:03 PM PDT 24 Jun 10 08:35:55 PM PDT 24 2692741752 ps
T401 /workspace/coverage/default/2.chip_sw_edn_boot_mode.1202956788 Jun 10 08:36:39 PM PDT 24 Jun 10 08:46:35 PM PDT 24 3250984976 ps
T70 /workspace/coverage/default/0.chip_tap_straps_rma.1091790473 Jun 10 08:20:50 PM PDT 24 Jun 10 08:26:31 PM PDT 24 4286412879 ps
T253 /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.2724676675 Jun 10 08:47:00 PM PDT 24 Jun 10 08:53:49 PM PDT 24 3332273832 ps
T7 /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.3838272920 Jun 10 08:39:56 PM PDT 24 Jun 10 08:46:29 PM PDT 24 3840321276 ps
T274 /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.1304281898 Jun 10 08:20:48 PM PDT 24 Jun 10 08:24:20 PM PDT 24 2884678760 ps
T447 /workspace/coverage/default/79.chip_sw_all_escalation_resets.429709735 Jun 10 08:53:36 PM PDT 24 Jun 10 09:02:10 PM PDT 24 5998493270 ps
T448 /workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.185778427 Jun 10 08:33:59 PM PDT 24 Jun 10 08:38:25 PM PDT 24 2571155861 ps
T449 /workspace/coverage/default/0.chip_sw_alert_handler_entropy.3376729369 Jun 10 08:20:41 PM PDT 24 Jun 10 08:27:49 PM PDT 24 3160115580 ps
T290 /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.761878237 Jun 10 08:20:19 PM PDT 24 Jun 10 08:32:18 PM PDT 24 9262322314 ps
T450 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2820915622 Jun 10 08:28:41 PM PDT 24 Jun 10 08:38:26 PM PDT 24 4069062516 ps
T238 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.1513316386 Jun 10 08:19:33 PM PDT 24 Jun 10 10:07:51 PM PDT 24 49865817200 ps
T451 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.938727792 Jun 10 08:36:57 PM PDT 24 Jun 10 09:15:46 PM PDT 24 12154574400 ps
T372 /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.51586401 Jun 10 08:35:53 PM PDT 24 Jun 10 08:50:32 PM PDT 24 19160098624 ps
T765 /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3324325445 Jun 10 08:50:02 PM PDT 24 Jun 10 08:55:59 PM PDT 24 3602364674 ps
T34 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.2149135872 Jun 10 08:35:15 PM PDT 24 Jun 10 08:41:54 PM PDT 24 3852185156 ps
T726 /workspace/coverage/default/2.chip_sw_power_idle_load.1454945835 Jun 10 08:41:45 PM PDT 24 Jun 10 08:53:30 PM PDT 24 4322011864 ps
T846 /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.3888610529 Jun 10 08:50:17 PM PDT 24 Jun 10 08:58:31 PM PDT 24 3807737826 ps
T999 /workspace/coverage/default/2.chip_sw_csrng_kat_test.3829004251 Jun 10 08:36:08 PM PDT 24 Jun 10 08:41:59 PM PDT 24 2740041150 ps
T1000 /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.1169834866 Jun 10 08:25:45 PM PDT 24 Jun 10 08:30:58 PM PDT 24 3083597314 ps
T1001 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.1766950232 Jun 10 08:42:22 PM PDT 24 Jun 10 08:52:37 PM PDT 24 3922093110 ps
T397 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.1261377634 Jun 10 08:34:58 PM PDT 24 Jun 10 08:51:14 PM PDT 24 5651068072 ps
T67 /workspace/coverage/default/4.chip_tap_straps_testunlock0.3395800489 Jun 10 08:42:27 PM PDT 24 Jun 10 08:49:30 PM PDT 24 4450480965 ps
T1002 /workspace/coverage/default/0.rom_e2e_jtag_inject_rma.882068593 Jun 10 08:25:24 PM PDT 24 Jun 10 09:23:40 PM PDT 24 31138902109 ps
T1003 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.2646071909 Jun 10 08:42:15 PM PDT 24 Jun 10 08:55:57 PM PDT 24 4645442281 ps
T280 /workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.1132823405 Jun 10 08:39:24 PM PDT 24 Jun 10 08:41:17 PM PDT 24 2504048416 ps
T312 /workspace/coverage/default/78.chip_sw_all_escalation_resets.483833089 Jun 10 08:53:12 PM PDT 24 Jun 10 09:00:45 PM PDT 24 5405819326 ps
T313 /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.984417440 Jun 10 08:35:53 PM PDT 24 Jun 10 09:00:32 PM PDT 24 11582233224 ps
T314 /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.3179378845 Jun 10 08:25:02 PM PDT 24 Jun 10 08:39:16 PM PDT 24 7323092100 ps
T315 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.741030902 Jun 10 08:31:31 PM PDT 24 Jun 10 08:35:38 PM PDT 24 2345010774 ps
T316 /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3055760471 Jun 10 08:42:43 PM PDT 24 Jun 10 08:53:28 PM PDT 24 8043879320 ps
T13 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1380838159 Jun 10 08:29:14 PM PDT 24 Jun 10 09:02:25 PM PDT 24 25537504358 ps
T267 /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.3322432024 Jun 10 08:26:23 PM PDT 24 Jun 10 08:39:18 PM PDT 24 6823240386 ps
T317 /workspace/coverage/default/75.chip_sw_all_escalation_resets.1956200358 Jun 10 08:49:11 PM PDT 24 Jun 10 08:59:31 PM PDT 24 4632083352 ps
T177 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.201466934 Jun 10 08:34:35 PM PDT 24 Jun 10 08:48:15 PM PDT 24 7054544339 ps
T1004 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.3743181120 Jun 10 08:27:39 PM PDT 24 Jun 10 09:35:58 PM PDT 24 13675220600 ps
T1005 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.2813326373 Jun 10 08:18:42 PM PDT 24 Jun 10 08:30:30 PM PDT 24 5778488040 ps
T1006 /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.2934521109 Jun 10 08:51:38 PM PDT 24 Jun 10 08:57:01 PM PDT 24 4110327080 ps
T1007 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.2047140538 Jun 10 08:38:35 PM PDT 24 Jun 10 08:53:02 PM PDT 24 11297748444 ps
T47 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3291563436 Jun 10 08:24:50 PM PDT 24 Jun 10 08:33:41 PM PDT 24 7193187600 ps
T383 /workspace/coverage/default/4.chip_sw_all_escalation_resets.3644283399 Jun 10 08:43:21 PM PDT 24 Jun 10 08:55:35 PM PDT 24 5145532508 ps
T1008 /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.1390971359 Jun 10 08:23:38 PM PDT 24 Jun 10 08:34:25 PM PDT 24 4759486800 ps
T1009 /workspace/coverage/default/2.rom_e2e_smoke.2735275668 Jun 10 08:44:09 PM PDT 24 Jun 10 09:33:32 PM PDT 24 14219741696 ps
T1010 /workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.835015404 Jun 10 08:26:48 PM PDT 24 Jun 10 08:51:19 PM PDT 24 7676136210 ps
T237 /workspace/coverage/default/1.chip_sw_flash_init.2409065000 Jun 10 08:24:32 PM PDT 24 Jun 10 08:59:12 PM PDT 24 22902464560 ps
T25 /workspace/coverage/default/2.chip_sw_spi_device_pass_through.605004765 Jun 10 08:34:54 PM PDT 24 Jun 10 08:48:57 PM PDT 24 7028623458 ps
T1011 /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.2654430256 Jun 10 08:21:00 PM PDT 24 Jun 10 08:50:53 PM PDT 24 9199555512 ps
T784 /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.388520892 Jun 10 08:47:59 PM PDT 24 Jun 10 08:55:32 PM PDT 24 3590598186 ps
T1012 /workspace/coverage/default/1.chip_tap_straps_rma.4254427468 Jun 10 08:29:30 PM PDT 24 Jun 10 08:46:10 PM PDT 24 9350465270 ps
T165 /workspace/coverage/default/61.chip_sw_all_escalation_resets.1959073008 Jun 10 08:48:17 PM PDT 24 Jun 10 08:59:13 PM PDT 24 5315305344 ps
T1013 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.2194614852 Jun 10 08:36:28 PM PDT 24 Jun 10 09:04:44 PM PDT 24 8462646678 ps
T1014 /workspace/coverage/default/1.chip_sw_alert_handler_escalation.305688101 Jun 10 08:26:58 PM PDT 24 Jun 10 08:34:56 PM PDT 24 5137888332 ps
T1015 /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.3773192437 Jun 10 08:34:18 PM PDT 24 Jun 10 08:43:41 PM PDT 24 5441201426 ps
T1016 /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.2888321011 Jun 10 08:39:53 PM PDT 24 Jun 10 08:49:14 PM PDT 24 4138725286 ps
T1017 /workspace/coverage/default/2.rom_e2e_static_critical.1507825279 Jun 10 08:45:19 PM PDT 24 Jun 10 09:55:41 PM PDT 24 16551700126 ps
T809 /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.1345885938 Jun 10 08:53:38 PM PDT 24 Jun 10 08:59:13 PM PDT 24 4059044008 ps
T356 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.2203669875 Jun 10 08:32:18 PM PDT 24 Jun 10 08:43:43 PM PDT 24 5029351480 ps
T1018 /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.2573511028 Jun 10 08:20:24 PM PDT 24 Jun 10 08:25:21 PM PDT 24 3466551298 ps
T241 /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.418800582 Jun 10 08:29:54 PM PDT 24 Jun 10 08:59:08 PM PDT 24 24308963850 ps
T242 /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.1143013674 Jun 10 08:21:08 PM PDT 24 Jun 10 08:55:04 PM PDT 24 23418957851 ps
T250 /workspace/coverage/default/0.chip_sw_plic_sw_irq.1266051008 Jun 10 08:19:39 PM PDT 24 Jun 10 08:24:43 PM PDT 24 2967347656 ps
T1019 /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.4111798826 Jun 10 08:22:24 PM PDT 24 Jun 10 08:34:49 PM PDT 24 5216220148 ps
T1020 /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.554073846 Jun 10 08:31:40 PM PDT 24 Jun 10 08:35:47 PM PDT 24 3021536460 ps
T174 /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.1952039999 Jun 10 08:22:51 PM PDT 24 Jun 10 08:26:39 PM PDT 24 3121055682 ps
T1021 /workspace/coverage/default/2.rom_e2e_asm_init_dev.3061923997 Jun 10 08:44:53 PM PDT 24 Jun 10 09:31:59 PM PDT 24 14072661293 ps
T1022 /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.2708793583 Jun 10 08:40:12 PM PDT 24 Jun 10 09:01:36 PM PDT 24 5615587004 ps
T180 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.3699125894 Jun 10 08:26:58 PM PDT 24 Jun 10 08:38:41 PM PDT 24 5049357590 ps
T305 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.2773449741 Jun 10 08:27:57 PM PDT 24 Jun 10 08:37:34 PM PDT 24 5363494166 ps
T1023 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2207017374 Jun 10 08:42:15 PM PDT 24 Jun 10 09:17:06 PM PDT 24 13520338132 ps
T779 /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.2765754472 Jun 10 08:46:54 PM PDT 24 Jun 10 08:53:12 PM PDT 24 4092487904 ps
T306 /workspace/coverage/default/1.chip_sw_data_integrity_escalation.1856397409 Jun 10 08:22:32 PM PDT 24 Jun 10 08:35:48 PM PDT 24 6035954516 ps
T380 /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1011463278 Jun 10 08:30:17 PM PDT 24 Jun 10 08:38:46 PM PDT 24 5811298920 ps
T99 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.803030027 Jun 10 08:39:42 PM PDT 24 Jun 10 09:07:05 PM PDT 24 20784110690 ps
T1024 /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.2871767131 Jun 10 08:43:05 PM PDT 24 Jun 10 08:46:10 PM PDT 24 2400509960 ps
T1025 /workspace/coverage/default/1.chip_sw_hmac_enc.975371801 Jun 10 08:29:00 PM PDT 24 Jun 10 08:33:37 PM PDT 24 3439475096 ps
T1026 /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.3031283443 Jun 10 08:34:16 PM PDT 24 Jun 10 08:42:00 PM PDT 24 8143709483 ps
T50 /workspace/coverage/default/0.chip_sw_spi_device_tpm.2039796474 Jun 10 08:22:19 PM PDT 24 Jun 10 08:28:14 PM PDT 24 3154000786 ps
T455 /workspace/coverage/default/1.chip_sw_kmac_app_rom.1270508504 Jun 10 08:27:42 PM PDT 24 Jun 10 08:32:54 PM PDT 24 3200808488 ps
T1027 /workspace/coverage/default/0.chip_sw_kmac_smoketest.1711594526 Jun 10 08:23:06 PM PDT 24 Jun 10 08:30:47 PM PDT 24 3152948096 ps
T777 /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2222811243 Jun 10 08:50:40 PM PDT 24 Jun 10 08:57:15 PM PDT 24 4061475300 ps
T802 /workspace/coverage/default/8.chip_sw_all_escalation_resets.1900505830 Jun 10 08:43:30 PM PDT 24 Jun 10 08:55:32 PM PDT 24 6345689920 ps
T214 /workspace/coverage/default/2.chip_sw_inject_scramble_seed.334149293 Jun 10 08:32:57 PM PDT 24 Jun 10 11:28:33 PM PDT 24 66660856051 ps
T384 /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.3906345841 Jun 10 08:44:05 PM PDT 24 Jun 10 08:51:19 PM PDT 24 4462868824 ps
T1028 /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.3918040557 Jun 10 08:20:10 PM PDT 24 Jun 10 08:40:09 PM PDT 24 5760793947 ps
T724 /workspace/coverage/default/82.chip_sw_all_escalation_resets.3760310770 Jun 10 08:50:21 PM PDT 24 Jun 10 09:02:38 PM PDT 24 6631662120 ps
T1029 /workspace/coverage/default/2.chip_sw_aes_smoketest.994629468 Jun 10 08:40:07 PM PDT 24 Jun 10 08:43:57 PM PDT 24 3517252364 ps
T231 /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.3345982669 Jun 10 08:28:42 PM PDT 24 Jun 10 09:06:02 PM PDT 24 12425995600 ps
T1030 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.3217228907 Jun 10 08:36:12 PM PDT 24 Jun 10 08:50:12 PM PDT 24 6956976534 ps
T1031 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.3180100970 Jun 10 08:47:16 PM PDT 24 Jun 10 09:38:29 PM PDT 24 15791775988 ps
T1032 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.601174886 Jun 10 08:35:18 PM PDT 24 Jun 10 09:35:17 PM PDT 24 15418197000 ps
T1033 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.1625471976 Jun 10 08:46:46 PM PDT 24 Jun 10 09:37:06 PM PDT 24 13905956892 ps
T166 /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.344484429 Jun 10 08:21:06 PM PDT 24 Jun 10 08:29:33 PM PDT 24 4590676144 ps
T1034 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3401363437 Jun 10 08:20:43 PM PDT 24 Jun 10 08:30:56 PM PDT 24 4811351088 ps
T817 /workspace/coverage/default/12.chip_sw_all_escalation_resets.574377349 Jun 10 08:45:10 PM PDT 24 Jun 10 08:54:46 PM PDT 24 4313425320 ps
T835 /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.1649819756 Jun 10 08:50:29 PM PDT 24 Jun 10 08:56:46 PM PDT 24 3462238930 ps
T1035 /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.189907852 Jun 10 08:18:12 PM PDT 24 Jun 10 08:23:32 PM PDT 24 3878912756 ps
T1036 /workspace/coverage/default/50.chip_sw_all_escalation_resets.2032353884 Jun 10 08:51:29 PM PDT 24 Jun 10 09:01:20 PM PDT 24 5109639240 ps
T1037 /workspace/coverage/default/0.chip_sw_aes_smoketest.1094613147 Jun 10 08:20:55 PM PDT 24 Jun 10 08:24:44 PM PDT 24 2401170750 ps
T10 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.239614345 Jun 10 08:39:12 PM PDT 24 Jun 10 09:02:49 PM PDT 24 19550638052 ps
T1038 /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.2419734729 Jun 10 08:18:21 PM PDT 24 Jun 10 08:30:28 PM PDT 24 5772559560 ps
T766 /workspace/coverage/default/97.chip_sw_all_escalation_resets.1997398656 Jun 10 08:50:25 PM PDT 24 Jun 10 08:58:01 PM PDT 24 4991956376 ps
T838 /workspace/coverage/default/59.chip_sw_all_escalation_resets.3078735413 Jun 10 08:48:18 PM PDT 24 Jun 10 08:56:13 PM PDT 24 6272324788 ps
T848 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.2444996465 Jun 10 08:19:48 PM PDT 24 Jun 10 08:27:46 PM PDT 24 3892796920 ps
T243 /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.281054254 Jun 10 08:22:51 PM PDT 24 Jun 10 08:33:43 PM PDT 24 4101873560 ps
T1039 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.742950801 Jun 10 08:27:33 PM PDT 24 Jun 10 09:33:51 PM PDT 24 14461913445 ps
T1040 /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.1545081704 Jun 10 08:49:46 PM PDT 24 Jun 10 08:55:05 PM PDT 24 4373823350 ps
T240 /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.3812502967 Jun 10 08:34:53 PM PDT 24 Jun 10 08:41:19 PM PDT 24 4398589140 ps
T1041 /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.1700299351 Jun 10 08:37:02 PM PDT 24 Jun 10 08:46:36 PM PDT 24 4430924122 ps
T203 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.3383526814 Jun 10 08:38:37 PM PDT 24 Jun 10 08:44:20 PM PDT 24 3084174585 ps
T175 /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.3909407883 Jun 10 08:34:48 PM PDT 24 Jun 10 08:37:13 PM PDT 24 2442849993 ps
T1042 /workspace/coverage/default/0.chip_sw_aon_timer_irq.1747609156 Jun 10 08:19:50 PM PDT 24 Jun 10 08:26:07 PM PDT 24 3586343316 ps
T1043 /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.434694642 Jun 10 08:23:39 PM PDT 24 Jun 10 08:32:33 PM PDT 24 5037992100 ps
T1044 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.746898923 Jun 10 08:42:12 PM PDT 24 Jun 10 09:22:26 PM PDT 24 8761925874 ps
T1045 /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.3517528248 Jun 10 08:24:47 PM PDT 24 Jun 10 08:29:52 PM PDT 24 2858182284 ps
T408 /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.1738143805 Jun 10 08:19:40 PM PDT 24 Jun 10 08:23:52 PM PDT 24 2896698848 ps
T1046 /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.4210336978 Jun 10 08:20:40 PM PDT 24 Jun 10 08:42:21 PM PDT 24 7995085676 ps
T275 /workspace/coverage/default/2.chip_sw_rv_timer_irq.1768310213 Jun 10 08:35:05 PM PDT 24 Jun 10 08:39:15 PM PDT 24 3689915964 ps
T1047 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.573967065 Jun 10 08:36:22 PM PDT 24 Jun 10 09:06:47 PM PDT 24 9425975310 ps
T1048 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.3340946136 Jun 10 08:32:45 PM PDT 24 Jun 10 09:30:59 PM PDT 24 14112880566 ps
T732 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.3020041943 Jun 10 08:18:11 PM PDT 24 Jun 10 08:20:06 PM PDT 24 2920850374 ps
T466 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.4166494615 Jun 10 08:29:49 PM PDT 24 Jun 10 09:30:45 PM PDT 24 16951727520 ps
T456 /workspace/coverage/default/2.chip_sw_kmac_app_rom.845586716 Jun 10 08:40:22 PM PDT 24 Jun 10 08:44:58 PM PDT 24 2601059804 ps
T1049 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.3455666745 Jun 10 08:40:32 PM PDT 24 Jun 10 09:15:29 PM PDT 24 11098492616 ps
T774 /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.1842908896 Jun 10 08:47:25 PM PDT 24 Jun 10 08:56:36 PM PDT 24 4243793404 ps
T1050 /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.3908507075 Jun 10 08:20:09 PM PDT 24 Jun 10 08:25:32 PM PDT 24 2314772680 ps
T138 /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.2631077032 Jun 10 08:36:57 PM PDT 24 Jun 10 08:54:31 PM PDT 24 6100405128 ps
T1051 /workspace/coverage/default/1.rom_e2e_asm_init_prod.2617697985 Jun 10 08:37:03 PM PDT 24 Jun 10 09:36:11 PM PDT 24 14768808162 ps
T11 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.1317135700 Jun 10 08:23:09 PM PDT 24 Jun 10 08:48:55 PM PDT 24 24812926136 ps
T1052 /workspace/coverage/default/2.chip_sw_flash_init.3006058143 Jun 10 08:33:57 PM PDT 24 Jun 10 09:07:26 PM PDT 24 24193349445 ps
T810 /workspace/coverage/default/3.chip_sw_all_escalation_resets.2958761318 Jun 10 08:41:38 PM PDT 24 Jun 10 08:54:08 PM PDT 24 4697403720 ps
T1053 /workspace/coverage/default/9.chip_sw_all_escalation_resets.3513830972 Jun 10 08:44:58 PM PDT 24 Jun 10 09:00:02 PM PDT 24 5495119328 ps
T1054 /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.1371458676 Jun 10 08:41:55 PM PDT 24 Jun 10 08:45:36 PM PDT 24 2654873540 ps
T856 /workspace/coverage/default/69.chip_sw_all_escalation_resets.2309968434 Jun 10 08:50:07 PM PDT 24 Jun 10 09:01:19 PM PDT 24 5574943972 ps
T1055 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.898698935 Jun 10 08:30:07 PM PDT 24 Jun 10 08:39:54 PM PDT 24 3272405994 ps
T764 /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.550245937 Jun 10 08:49:16 PM PDT 24 Jun 10 08:55:04 PM PDT 24 3887466552 ps
T1056 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2908703170 Jun 10 08:38:43 PM PDT 24 Jun 10 08:50:35 PM PDT 24 4611308244 ps
T1057 /workspace/coverage/default/0.chip_sw_flash_crash_alert.3784868177 Jun 10 08:23:00 PM PDT 24 Jun 10 08:34:32 PM PDT 24 5424265108 ps
T14 /workspace/coverage/default/1.chip_sw_sleep_pin_wake.689856378 Jun 10 08:24:22 PM PDT 24 Jun 10 08:33:05 PM PDT 24 6591724496 ps
T1058 /workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.3145912260 Jun 10 08:43:20 PM PDT 24 Jun 10 09:21:09 PM PDT 24 11125427988 ps
T1059 /workspace/coverage/default/10.chip_sw_all_escalation_resets.1985850225 Jun 10 08:44:03 PM PDT 24 Jun 10 08:54:41 PM PDT 24 4959658804 ps
T1060 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.2951889477 Jun 10 08:27:35 PM PDT 24 Jun 10 08:36:31 PM PDT 24 7452232584 ps
T1061 /workspace/coverage/default/2.rom_keymgr_functest.3440021005 Jun 10 08:40:33 PM PDT 24 Jun 10 08:49:00 PM PDT 24 4748823840 ps
T1062 /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.2079325523 Jun 10 08:19:44 PM PDT 24 Jun 10 08:44:45 PM PDT 24 12781814036 ps
T1063 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.2189380571 Jun 10 08:27:25 PM PDT 24 Jun 10 09:00:51 PM PDT 24 8489496552 ps
T1064 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.3966088887 Jun 10 08:26:33 PM PDT 24 Jun 10 09:31:19 PM PDT 24 14448945884 ps
T1065 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.19151905 Jun 10 08:34:21 PM PDT 24 Jun 10 09:16:17 PM PDT 24 28326663314 ps
T787 /workspace/coverage/default/58.chip_sw_all_escalation_resets.3114964376 Jun 10 08:48:53 PM PDT 24 Jun 10 08:58:15 PM PDT 24 5125840280 ps
T707 /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.2356597023 Jun 10 08:44:20 PM PDT 24 Jun 10 10:05:40 PM PDT 24 24445532112 ps
T1066 /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.638508822 Jun 10 08:25:05 PM PDT 24 Jun 10 08:27:37 PM PDT 24 2138034076 ps
T204 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.806455902 Jun 10 08:26:14 PM PDT 24 Jun 10 08:35:12 PM PDT 24 3712671000 ps
T1067 /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.3285952836 Jun 10 08:38:04 PM PDT 24 Jun 10 08:46:17 PM PDT 24 3881865810 ps
T307 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.3179756472 Jun 10 08:38:14 PM PDT 24 Jun 10 08:47:28 PM PDT 24 4116417100 ps
T1068 /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.94012289 Jun 10 08:33:47 PM PDT 24 Jun 10 08:42:26 PM PDT 24 4151990000 ps
T1069 /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.1274696886 Jun 10 08:27:18 PM PDT 24 Jun 10 08:32:37 PM PDT 24 6307314030 ps
T1070 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.1109424067 Jun 10 08:20:47 PM PDT 24 Jun 10 08:25:46 PM PDT 24 2910110866 ps
T1071 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.1269286662 Jun 10 08:36:40 PM PDT 24 Jun 10 09:28:59 PM PDT 24 17292757840 ps
T157 /workspace/coverage/default/0.chip_plic_all_irqs_10.2754652763 Jun 10 08:19:50 PM PDT 24 Jun 10 08:27:16 PM PDT 24 4577579524 ps
T1072 /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.2343378220 Jun 10 08:18:25 PM PDT 24 Jun 10 09:07:02 PM PDT 24 23687183260 ps
T343 /workspace/coverage/default/1.chip_plic_all_irqs_20.3140670782 Jun 10 08:28:29 PM PDT 24 Jun 10 08:41:25 PM PDT 24 5368908704 ps
T457 /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.3337183690 Jun 10 08:28:09 PM PDT 24 Jun 10 08:38:50 PM PDT 24 8375372970 ps
T1073 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.2302155963 Jun 10 08:38:46 PM PDT 24 Jun 10 09:25:14 PM PDT 24 20887950995 ps
T1074 /workspace/coverage/default/2.rom_e2e_asm_init_rma.1981482992 Jun 10 08:45:20 PM PDT 24 Jun 10 09:42:52 PM PDT 24 14097434476 ps
T1075 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.4141417268 Jun 10 08:20:35 PM PDT 24 Jun 10 08:44:04 PM PDT 24 6556513246 ps
T1076 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.925551292 Jun 10 08:37:12 PM PDT 24 Jun 10 08:53:23 PM PDT 24 9648690438 ps
T1077 /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.239173758 Jun 10 08:26:12 PM PDT 24 Jun 10 09:01:14 PM PDT 24 32820304824 ps
T205 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.1592656961 Jun 10 08:20:50 PM PDT 24 Jun 10 08:31:43 PM PDT 24 4615381083 ps
T385 /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.1942440905 Jun 10 08:47:44 PM PDT 24 Jun 10 08:54:15 PM PDT 24 3715660280 ps
T1078 /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.3511883408 Jun 10 08:33:13 PM PDT 24 Jun 11 12:51:03 AM PDT 24 77983115036 ps
T791 /workspace/coverage/default/15.chip_sw_all_escalation_resets.1156076200 Jun 10 08:46:18 PM PDT 24 Jun 10 08:57:50 PM PDT 24 5994361888 ps
T1079 /workspace/coverage/default/0.chip_sw_example_rom.4246165986 Jun 10 08:16:54 PM PDT 24 Jun 10 08:19:16 PM PDT 24 3177823240 ps
T1080 /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.1381725738 Jun 10 08:37:22 PM PDT 24 Jun 10 08:41:35 PM PDT 24 3006056904 ps
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