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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 95.48 94.18 95.43 94.99 96.65 99.51


Total test records in report: 2900
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T1231 /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.2727898221 Jun 10 08:32:38 PM PDT 24 Jun 10 08:47:16 PM PDT 24 5254483478 ps
T1232 /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.637739549 Jun 10 08:23:45 PM PDT 24 Jun 10 08:45:07 PM PDT 24 6835709306 ps
T154 /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.1447183206 Jun 10 08:20:55 PM PDT 24 Jun 10 11:19:42 PM PDT 24 57751756680 ps
T1233 /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.3638128458 Jun 10 08:45:23 PM PDT 24 Jun 10 08:58:55 PM PDT 24 10307224736 ps
T1234 /workspace/coverage/default/1.chip_sw_aes_enc.3970714366 Jun 10 08:28:56 PM PDT 24 Jun 10 08:33:14 PM PDT 24 3886410170 ps
T133 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3516275106 Jun 10 08:22:31 PM PDT 24 Jun 10 08:30:00 PM PDT 24 5739980176 ps
T1235 /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.3933698801 Jun 10 08:34:04 PM PDT 24 Jun 10 08:39:05 PM PDT 24 4104832808 ps
T775 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.809224677 Jun 10 08:31:52 PM PDT 24 Jun 10 08:37:46 PM PDT 24 3853400114 ps
T1236 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2190032253 Jun 10 08:18:49 PM PDT 24 Jun 10 09:10:07 PM PDT 24 35698523384 ps
T1237 /workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.2891466194 Jun 10 08:31:28 PM PDT 24 Jun 10 08:37:27 PM PDT 24 2968919352 ps
T831 /workspace/coverage/default/93.chip_sw_all_escalation_resets.3802031784 Jun 10 08:50:19 PM PDT 24 Jun 10 09:01:06 PM PDT 24 4638999030 ps
T1238 /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.1972411872 Jun 10 08:18:41 PM PDT 24 Jun 10 08:24:20 PM PDT 24 3275573700 ps
T1239 /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.271723401 Jun 10 08:28:55 PM PDT 24 Jun 10 09:03:45 PM PDT 24 11450488090 ps
T332 /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.1136339831 Jun 10 08:28:57 PM PDT 24 Jun 10 08:33:06 PM PDT 24 3007160888 ps
T1240 /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.431394167 Jun 10 08:35:36 PM PDT 24 Jun 10 08:41:09 PM PDT 24 3120443586 ps
T1241 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.3048579969 Jun 10 08:27:37 PM PDT 24 Jun 10 09:31:51 PM PDT 24 13976879653 ps
T1242 /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.540685799 Jun 10 08:18:03 PM PDT 24 Jun 10 08:26:36 PM PDT 24 3342897044 ps
T785 /workspace/coverage/default/76.chip_sw_all_escalation_resets.2491904474 Jun 10 08:49:37 PM PDT 24 Jun 10 09:01:26 PM PDT 24 6268269576 ps
T1243 /workspace/coverage/default/2.chip_sw_aes_enc.2793276627 Jun 10 08:37:40 PM PDT 24 Jun 10 08:41:17 PM PDT 24 3116050654 ps
T1244 /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.794747991 Jun 10 08:20:36 PM PDT 24 Jun 10 08:31:20 PM PDT 24 5740440144 ps
T1245 /workspace/coverage/default/57.chip_sw_all_escalation_resets.1580016124 Jun 10 08:47:54 PM PDT 24 Jun 10 08:56:34 PM PDT 24 5470924808 ps
T739 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.2953187533 Jun 10 08:34:26 PM PDT 24 Jun 10 08:40:38 PM PDT 24 3348609338 ps
T254 /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.1972424701 Jun 10 08:46:23 PM PDT 24 Jun 10 08:55:10 PM PDT 24 4011046792 ps
T792 /workspace/coverage/default/30.chip_sw_all_escalation_resets.2006626711 Jun 10 08:46:54 PM PDT 24 Jun 10 08:55:46 PM PDT 24 4300089840 ps
T1246 /workspace/coverage/default/1.chip_sw_otbn_smoketest.2221208918 Jun 10 08:32:30 PM PDT 24 Jun 10 09:12:48 PM PDT 24 10021300168 ps
T1247 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.2347334064 Jun 10 08:28:47 PM PDT 24 Jun 10 10:15:32 PM PDT 24 22669764958 ps
T1248 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.3512712557 Jun 10 08:20:39 PM PDT 24 Jun 10 09:18:43 PM PDT 24 19316988645 ps
T1249 /workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.59150389 Jun 10 08:44:29 PM PDT 24 Jun 10 10:00:34 PM PDT 24 19879558466 ps
T1250 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.2268187312 Jun 10 08:29:48 PM PDT 24 Jun 10 08:39:12 PM PDT 24 5487778644 ps
T386 /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.162598084 Jun 10 08:48:22 PM PDT 24 Jun 10 08:55:17 PM PDT 24 3834427020 ps
T1251 /workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.1953379609 Jun 10 08:45:05 PM PDT 24 Jun 10 09:49:45 PM PDT 24 17675457304 ps
T1252 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.1067946743 Jun 10 08:26:11 PM PDT 24 Jun 10 09:10:47 PM PDT 24 11173795836 ps
T1253 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.499516217 Jun 10 08:35:57 PM PDT 24 Jun 10 08:46:10 PM PDT 24 4969857452 ps
T1254 /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.3698290377 Jun 10 08:27:22 PM PDT 24 Jun 10 09:28:27 PM PDT 24 14204217860 ps
T1255 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.2373455830 Jun 10 08:23:02 PM PDT 24 Jun 10 08:35:25 PM PDT 24 4713999720 ps
T281 /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.3808721991 Jun 10 08:19:29 PM PDT 24 Jun 10 08:28:11 PM PDT 24 4453158200 ps
T87 /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.1990550989 Jun 10 08:46:18 PM PDT 24 Jun 10 08:52:38 PM PDT 24 4287201020 ps
T91 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.2298500936 Jun 10 08:45:33 PM PDT 24 Jun 10 08:54:01 PM PDT 24 4375042744 ps
T92 /workspace/coverage/default/2.chip_sw_aes_masking_off.1970993204 Jun 10 08:35:32 PM PDT 24 Jun 10 08:39:48 PM PDT 24 2484962844 ps
T93 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3575925951 Jun 10 08:26:29 PM PDT 24 Jun 10 08:37:16 PM PDT 24 7583083520 ps
T94 /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.3804011482 Jun 10 08:45:17 PM PDT 24 Jun 10 08:49:50 PM PDT 24 2957979176 ps
T95 /workspace/coverage/default/83.chip_sw_all_escalation_resets.788177230 Jun 10 08:50:29 PM PDT 24 Jun 10 08:58:47 PM PDT 24 5125121824 ps
T96 /workspace/coverage/default/40.chip_sw_all_escalation_resets.229638234 Jun 10 08:48:25 PM PDT 24 Jun 10 09:00:45 PM PDT 24 4924237200 ps
T97 /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.3007009029 Jun 10 08:45:39 PM PDT 24 Jun 10 09:13:41 PM PDT 24 8300304832 ps
T98 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.979737947 Jun 10 08:19:05 PM PDT 24 Jun 10 08:27:21 PM PDT 24 4628841366 ps
T21 /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.1565285405 Jun 10 08:24:11 PM PDT 24 Jun 10 08:28:34 PM PDT 24 3429911124 ps
T1256 /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.1864204034 Jun 10 08:28:37 PM PDT 24 Jun 10 08:36:18 PM PDT 24 4056499288 ps
T783 /workspace/coverage/default/87.chip_sw_all_escalation_resets.3309276481 Jun 10 08:53:33 PM PDT 24 Jun 10 09:05:56 PM PDT 24 5352676218 ps
T191 /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.2243141946 Jun 10 08:18:38 PM PDT 24 Jun 10 08:27:40 PM PDT 24 3939509319 ps
T1257 /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.2382675901 Jun 10 08:50:33 PM PDT 24 Jun 10 08:56:30 PM PDT 24 4049171898 ps
T1258 /workspace/coverage/default/2.chip_sw_ast_clk_outputs.1875575691 Jun 10 08:38:07 PM PDT 24 Jun 10 08:53:23 PM PDT 24 7339661272 ps
T1259 /workspace/coverage/default/2.chip_sw_kmac_smoketest.205263912 Jun 10 08:44:44 PM PDT 24 Jun 10 08:49:01 PM PDT 24 2280391910 ps
T1260 /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.3035755877 Jun 10 08:45:52 PM PDT 24 Jun 10 09:07:31 PM PDT 24 8517221404 ps
T1261 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.1900824969 Jun 10 08:27:33 PM PDT 24 Jun 10 09:23:33 PM PDT 24 13580307872 ps
T1262 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.859217286 Jun 10 08:36:20 PM PDT 24 Jun 10 08:38:22 PM PDT 24 2639640316 ps
T140 /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.1341819428 Jun 10 08:42:37 PM PDT 24 Jun 10 08:54:59 PM PDT 24 6195693624 ps
T1263 /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.3063273244 Jun 10 08:38:42 PM PDT 24 Jun 10 08:47:27 PM PDT 24 5286311648 ps
T292 /workspace/coverage/default/3.chip_sw_data_integrity_escalation.1760404609 Jun 10 08:41:48 PM PDT 24 Jun 10 08:55:17 PM PDT 24 6565930808 ps
T1264 /workspace/coverage/default/1.chip_sw_csrng_smoketest.3954394248 Jun 10 08:31:10 PM PDT 24 Jun 10 08:34:07 PM PDT 24 2304016090 ps
T710 /workspace/coverage/default/0.chip_sw_edn_boot_mode.96424840 Jun 10 08:20:22 PM PDT 24 Jun 10 08:31:00 PM PDT 24 3297036152 ps
T321 /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.2629615257 Jun 10 08:47:43 PM PDT 24 Jun 10 08:54:50 PM PDT 24 4050065104 ps
T1265 /workspace/coverage/default/0.rom_e2e_smoke.567860965 Jun 10 08:26:24 PM PDT 24 Jun 10 09:32:25 PM PDT 24 14016298664 ps
T1266 /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.2333537929 Jun 10 08:38:20 PM PDT 24 Jun 10 09:12:59 PM PDT 24 23304332760 ps
T786 /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.3056112302 Jun 10 08:48:33 PM PDT 24 Jun 10 08:53:56 PM PDT 24 3690322160 ps
T155 /workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.3677649862 Jun 10 08:34:15 PM PDT 24 Jun 10 11:23:47 PM PDT 24 57675566564 ps
T1267 /workspace/coverage/default/0.chip_sw_power_sleep_load.3843857388 Jun 10 08:20:45 PM PDT 24 Jun 10 08:31:28 PM PDT 24 9969831280 ps
T1268 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.2666375980 Jun 10 08:35:58 PM PDT 24 Jun 10 09:28:19 PM PDT 24 18738693714 ps
T12 /workspace/coverage/default/2.chip_sw_sleep_pin_wake.1278245782 Jun 10 08:33:48 PM PDT 24 Jun 10 08:38:13 PM PDT 24 3264520536 ps
T433 /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.1731368175 Jun 10 08:31:18 PM PDT 24 Jun 10 08:36:36 PM PDT 24 3364292800 ps
T434 /workspace/coverage/default/2.chip_sw_pattgen_ios.1662534214 Jun 10 08:36:45 PM PDT 24 Jun 10 08:40:12 PM PDT 24 2067670542 ps
T435 /workspace/coverage/default/74.chip_sw_all_escalation_resets.1553044548 Jun 10 08:52:51 PM PDT 24 Jun 10 09:01:11 PM PDT 24 5608255680 ps
T436 /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.2791995 Jun 10 08:45:48 PM PDT 24 Jun 10 09:55:04 PM PDT 24 18030355928 ps
T437 /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.1635469830 Jun 10 08:51:50 PM PDT 24 Jun 10 08:58:33 PM PDT 24 3000311280 ps
T438 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2744795800 Jun 10 08:40:17 PM PDT 24 Jun 10 09:34:57 PM PDT 24 25596713861 ps
T439 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1437575353 Jun 10 08:21:00 PM PDT 24 Jun 10 08:40:48 PM PDT 24 8052816521 ps
T440 /workspace/coverage/default/0.chip_sival_flash_info_access.2716069648 Jun 10 08:21:05 PM PDT 24 Jun 10 08:27:27 PM PDT 24 3259052058 ps
T88 /workspace/coverage/default/0.chip_sw_all_escalation_resets.3607913466 Jun 10 08:16:47 PM PDT 24 Jun 10 08:25:54 PM PDT 24 3936593470 ps
T803 /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.2463965403 Jun 10 08:53:01 PM PDT 24 Jun 10 08:59:06 PM PDT 24 3304504508 ps
T816 /workspace/coverage/default/24.chip_sw_all_escalation_resets.4042040616 Jun 10 08:47:52 PM PDT 24 Jun 10 09:01:00 PM PDT 24 5814362680 ps
T1269 /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.2464280724 Jun 10 08:21:12 PM PDT 24 Jun 10 08:53:09 PM PDT 24 8373535518 ps
T769 /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.1416247366 Jun 10 08:47:57 PM PDT 24 Jun 10 08:53:25 PM PDT 24 3774975654 ps
T839 /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.1403853089 Jun 10 08:47:11 PM PDT 24 Jun 10 08:53:04 PM PDT 24 3725882048 ps
T807 /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.377915243 Jun 10 08:49:55 PM PDT 24 Jun 10 08:57:23 PM PDT 24 3557139440 ps
T1270 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.1491817542 Jun 10 08:18:18 PM PDT 24 Jun 10 08:33:56 PM PDT 24 9638240659 ps
T1271 /workspace/coverage/default/0.chip_sw_inject_scramble_seed.865378759 Jun 10 08:19:24 PM PDT 24 Jun 11 12:05:32 AM PDT 24 64122280608 ps
T1272 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.2349258273 Jun 10 08:18:51 PM PDT 24 Jun 10 08:30:47 PM PDT 24 4072861796 ps
T1273 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.4227390187 Jun 10 08:28:08 PM PDT 24 Jun 10 08:36:48 PM PDT 24 5708882597 ps
T1274 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3883254018 Jun 10 08:24:44 PM PDT 24 Jun 10 08:33:32 PM PDT 24 4102666602 ps
T1275 /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3404458945 Jun 10 08:25:43 PM PDT 24 Jun 11 12:00:15 AM PDT 24 255069855816 ps
T1276 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.3210944647 Jun 10 08:29:04 PM PDT 24 Jun 10 09:42:51 PM PDT 24 14211189902 ps
T1277 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.927622112 Jun 10 08:45:35 PM PDT 24 Jun 10 08:55:40 PM PDT 24 5072844268 ps
T1278 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3477572307 Jun 10 08:31:49 PM PDT 24 Jun 10 08:45:54 PM PDT 24 4055460362 ps
T1279 /workspace/coverage/default/0.chip_sw_alert_handler_escalation.1123095198 Jun 10 08:19:30 PM PDT 24 Jun 10 08:30:00 PM PDT 24 6189986932 ps
T162 /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.538340006 Jun 10 08:24:15 PM PDT 24 Jun 10 08:26:02 PM PDT 24 2271092403 ps
T1280 /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.1065154513 Jun 10 08:41:04 PM PDT 24 Jun 10 08:49:33 PM PDT 24 4734882840 ps
T1281 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.3372368143 Jun 10 08:29:07 PM PDT 24 Jun 10 08:52:23 PM PDT 24 13504952889 ps
T1282 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3003287545 Jun 10 08:21:38 PM PDT 24 Jun 10 08:25:55 PM PDT 24 3055725964 ps
T1283 /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.905570194 Jun 10 08:44:52 PM PDT 24 Jun 10 08:52:19 PM PDT 24 6474153728 ps
T347 /workspace/coverage/default/1.chip_plic_all_irqs_0.3224526891 Jun 10 08:29:22 PM PDT 24 Jun 10 08:52:23 PM PDT 24 5889629816 ps
T1284 /workspace/coverage/default/1.rom_e2e_shutdown_output.3976473908 Jun 10 08:34:42 PM PDT 24 Jun 10 09:20:32 PM PDT 24 22294827428 ps
T1285 /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.3221934908 Jun 10 08:28:05 PM PDT 24 Jun 10 09:24:09 PM PDT 24 11300983965 ps
T1286 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1890680446 Jun 10 08:38:23 PM PDT 24 Jun 10 08:50:24 PM PDT 24 3696447060 ps
T800 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.4238478260 Jun 10 08:36:46 PM PDT 24 Jun 10 08:43:01 PM PDT 24 3507035230 ps
T1287 /workspace/coverage/default/0.chip_sw_edn_kat.360014727 Jun 10 08:25:32 PM PDT 24 Jun 10 08:36:38 PM PDT 24 3792826616 ps
T1288 /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.720862584 Jun 10 08:21:41 PM PDT 24 Jun 10 08:27:45 PM PDT 24 3046196704 ps
T1289 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.480040728 Jun 10 08:25:03 PM PDT 24 Jun 10 08:37:49 PM PDT 24 5746644884 ps
T1290 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.3145122297 Jun 10 08:29:11 PM PDT 24 Jun 10 10:11:30 PM PDT 24 22088793784 ps
T1291 /workspace/coverage/default/1.chip_sw_aon_timer_irq.504046559 Jun 10 08:24:52 PM PDT 24 Jun 10 08:31:39 PM PDT 24 3964165384 ps
T1292 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.3946086970 Jun 10 08:35:19 PM PDT 24 Jun 10 08:41:55 PM PDT 24 5494137403 ps
T1293 /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.2438412124 Jun 10 08:44:50 PM PDT 24 Jun 10 08:51:10 PM PDT 24 3737576504 ps
T1294 /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.2847556625 Jun 10 08:26:03 PM PDT 24 Jun 10 08:38:27 PM PDT 24 6175340986 ps
T1295 /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3462809815 Jun 10 08:44:56 PM PDT 24 Jun 10 09:30:18 PM PDT 24 12636086664 ps
T134 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2910868097 Jun 10 08:27:16 PM PDT 24 Jun 10 08:34:35 PM PDT 24 5469753436 ps
T1296 /workspace/coverage/default/0.chip_sw_flash_init.3630553098 Jun 10 08:18:03 PM PDT 24 Jun 10 09:04:42 PM PDT 24 23695945711 ps
T1297 /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.3028963611 Jun 10 08:30:50 PM PDT 24 Jun 10 08:39:38 PM PDT 24 5788039752 ps
T387 /workspace/coverage/default/63.chip_sw_all_escalation_resets.1230860113 Jun 10 08:49:41 PM PDT 24 Jun 10 08:59:14 PM PDT 24 5915196696 ps
T348 /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.3113817438 Jun 10 08:18:41 PM PDT 24 Jun 10 08:50:45 PM PDT 24 13511923720 ps
T1298 /workspace/coverage/default/1.chip_sw_edn_auto_mode.2592168452 Jun 10 08:28:53 PM PDT 24 Jun 10 08:40:41 PM PDT 24 3414487128 ps
T1299 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.965842767 Jun 10 08:36:46 PM PDT 24 Jun 10 08:41:11 PM PDT 24 2814552504 ps
T1300 /workspace/coverage/default/2.chip_sw_alert_handler_entropy.243186565 Jun 10 08:36:30 PM PDT 24 Jun 10 08:40:50 PM PDT 24 2960838836 ps
T1301 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.2914632777 Jun 10 08:34:48 PM PDT 24 Jun 10 09:03:02 PM PDT 24 22086589960 ps
T235 /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.4293473537 Jun 10 08:22:35 PM PDT 24 Jun 10 09:22:47 PM PDT 24 15434598348 ps
T1302 /workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.1250743252 Jun 10 08:42:50 PM PDT 24 Jun 10 10:18:23 PM PDT 24 27277829052 ps
T756 /workspace/coverage/default/0.rom_e2e_jtag_debug_rma.4053502933 Jun 10 08:22:47 PM PDT 24 Jun 10 09:04:38 PM PDT 24 14008345360 ps
T793 /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.2922397146 Jun 10 08:44:58 PM PDT 24 Jun 10 08:52:41 PM PDT 24 3629955704 ps
T1303 /workspace/coverage/default/2.rom_volatile_raw_unlock.1127389357 Jun 10 08:40:57 PM PDT 24 Jun 10 08:42:44 PM PDT 24 2047351815 ps
T761 /workspace/coverage/default/98.chip_sw_all_escalation_resets.241726029 Jun 10 08:51:45 PM PDT 24 Jun 10 09:00:42 PM PDT 24 5760073600 ps
T1304 /workspace/coverage/default/0.chip_sw_aes_masking_off.3802553233 Jun 10 08:18:29 PM PDT 24 Jun 10 08:22:48 PM PDT 24 3001619353 ps
T1305 /workspace/coverage/default/0.chip_sw_edn_sw_mode.610875270 Jun 10 08:20:40 PM PDT 24 Jun 10 08:54:42 PM PDT 24 8299766556 ps
T1306 /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.1484671481 Jun 10 08:39:26 PM PDT 24 Jun 10 08:48:01 PM PDT 24 4695249524 ps
T1307 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.2829461870 Jun 10 08:31:10 PM PDT 24 Jun 10 08:48:09 PM PDT 24 5944787482 ps
T1308 /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.2956195301 Jun 10 08:28:57 PM PDT 24 Jun 10 09:00:32 PM PDT 24 25838120294 ps
T1309 /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.985670964 Jun 10 08:22:19 PM PDT 24 Jun 10 08:32:06 PM PDT 24 4599363040 ps
T1310 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.2328033739 Jun 10 08:27:50 PM PDT 24 Jun 10 09:33:39 PM PDT 24 15126694306 ps
T232 /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.1755950464 Jun 10 08:38:33 PM PDT 24 Jun 10 09:03:29 PM PDT 24 7870041442 ps
T1311 /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.2517525062 Jun 10 08:17:40 PM PDT 24 Jun 10 08:28:00 PM PDT 24 4877089800 ps
T1312 /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.4182337918 Jun 10 08:20:47 PM PDT 24 Jun 10 08:28:57 PM PDT 24 3706869668 ps
T801 /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.399685246 Jun 10 08:48:33 PM PDT 24 Jun 10 08:54:52 PM PDT 24 3600945064 ps
T89 /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1736319750 Jun 10 08:44:23 PM PDT 24 Jun 10 08:51:41 PM PDT 24 3694093582 ps
T1313 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.1539889603 Jun 10 08:33:46 PM PDT 24 Jun 10 08:57:20 PM PDT 24 9509630414 ps
T1314 /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.2048052994 Jun 10 08:46:30 PM PDT 24 Jun 10 08:51:18 PM PDT 24 3542467188 ps
T780 /workspace/coverage/default/51.chip_sw_all_escalation_resets.3553218135 Jun 10 08:51:23 PM PDT 24 Jun 10 09:02:03 PM PDT 24 4886752562 ps
T1315 /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.3052013607 Jun 10 08:24:10 PM PDT 24 Jun 10 08:54:48 PM PDT 24 12108091868 ps
T1316 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.958150548 Jun 10 08:20:54 PM PDT 24 Jun 10 08:54:15 PM PDT 24 8296151350 ps
T1317 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.1844853991 Jun 10 08:42:25 PM PDT 24 Jun 10 08:52:53 PM PDT 24 4110434288 ps
T1318 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.3402823138 Jun 10 08:37:04 PM PDT 24 Jun 10 09:47:00 PM PDT 24 14638085972 ps
T1319 /workspace/coverage/default/2.chip_sw_flash_crash_alert.2392669553 Jun 10 08:41:23 PM PDT 24 Jun 10 08:54:54 PM PDT 24 5338664360 ps
T22 /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3067018775 Jun 10 08:33:37 PM PDT 24 Jun 10 08:38:09 PM PDT 24 3636839053 ps
T1320 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.306876454 Jun 10 08:36:05 PM PDT 24 Jun 10 08:45:13 PM PDT 24 4741370644 ps
T1321 /workspace/coverage/default/4.chip_sw_uart_tx_rx.1189973840 Jun 10 08:42:33 PM PDT 24 Jun 10 08:53:19 PM PDT 24 4406451870 ps
T1322 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.1836488685 Jun 10 08:25:01 PM PDT 24 Jun 10 08:49:07 PM PDT 24 9453762462 ps
T322 /workspace/coverage/default/80.chip_sw_all_escalation_resets.503610602 Jun 10 08:53:26 PM PDT 24 Jun 10 09:04:21 PM PDT 24 5922708070 ps
T796 /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.2177242407 Jun 10 08:49:09 PM PDT 24 Jun 10 08:56:38 PM PDT 24 4186992650 ps
T1323 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.1110228637 Jun 10 08:36:51 PM PDT 24 Jun 10 08:59:21 PM PDT 24 7053919960 ps
T752 /workspace/coverage/default/2.chip_sw_power_sleep_load.3732239228 Jun 10 08:41:12 PM PDT 24 Jun 10 08:48:25 PM PDT 24 5325737160 ps
T1324 /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.2468951740 Jun 10 08:26:59 PM PDT 24 Jun 10 08:37:19 PM PDT 24 4699654408 ps
T1325 /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.2893371564 Jun 10 08:19:51 PM PDT 24 Jun 10 08:30:08 PM PDT 24 5485295840 ps
T1326 /workspace/coverage/default/0.chip_sw_gpio_smoketest.562182335 Jun 10 08:23:17 PM PDT 24 Jun 10 08:26:58 PM PDT 24 2841758878 ps
T74 /workspace/coverage/default/0.chip_sw_usbdev_pullup.1753918183 Jun 10 08:18:24 PM PDT 24 Jun 10 08:23:40 PM PDT 24 3051731498 ps
T1327 /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.2732330250 Jun 10 08:41:26 PM PDT 24 Jun 10 08:47:31 PM PDT 24 4860997240 ps
T8 /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.590277720 Jun 10 08:19:56 PM PDT 24 Jun 10 08:24:53 PM PDT 24 4665275680 ps
T725 /workspace/coverage/default/1.chip_sw_all_escalation_resets.728344111 Jun 10 08:25:02 PM PDT 24 Jun 10 08:36:43 PM PDT 24 6052900476 ps
T1328 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.2166870092 Jun 10 08:28:16 PM PDT 24 Jun 10 08:37:51 PM PDT 24 7696627006 ps
T1329 /workspace/coverage/default/1.chip_sw_uart_smoketest.1858336686 Jun 10 08:31:35 PM PDT 24 Jun 10 08:37:17 PM PDT 24 3003001080 ps
T1330 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.2203383177 Jun 10 08:18:09 PM PDT 24 Jun 10 08:22:58 PM PDT 24 3531360973 ps
T1331 /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.2244369527 Jun 10 08:41:58 PM PDT 24 Jun 10 08:55:23 PM PDT 24 12161359950 ps
T1332 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.96428953 Jun 10 08:24:13 PM PDT 24 Jun 10 09:20:25 PM PDT 24 11231042788 ps
T1333 /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3660838364 Jun 10 08:48:26 PM PDT 24 Jun 10 08:55:35 PM PDT 24 3908982038 ps
T1334 /workspace/coverage/default/0.chip_sw_ast_clk_outputs.1438861869 Jun 10 08:21:53 PM PDT 24 Jun 10 08:37:01 PM PDT 24 7125953468 ps
T360 /workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.1660598748 Jun 10 08:28:46 PM PDT 24 Jun 10 08:35:26 PM PDT 24 3346870452 ps
T1335 /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.3620313594 Jun 10 08:43:15 PM PDT 24 Jun 10 09:08:11 PM PDT 24 8108658900 ps
T1336 /workspace/coverage/default/3.chip_tap_straps_prod.3498860564 Jun 10 08:41:14 PM PDT 24 Jun 10 08:44:01 PM PDT 24 2651957261 ps
T1337 /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3016917570 Jun 10 08:50:19 PM PDT 24 Jun 10 08:55:13 PM PDT 24 4229138074 ps
T1338 /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.4134275361 Jun 10 08:19:25 PM PDT 24 Jun 10 08:27:31 PM PDT 24 3769207986 ps
T696 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.1454498102 Jun 10 08:20:24 PM PDT 24 Jun 10 08:31:20 PM PDT 24 5777213032 ps
T1339 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.3260133029 Jun 10 08:27:16 PM PDT 24 Jun 10 10:02:49 PM PDT 24 25306524318 ps
T1340 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.2118460003 Jun 10 08:41:40 PM PDT 24 Jun 10 08:52:25 PM PDT 24 5094127940 ps
T1341 /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.1316347384 Jun 10 08:19:30 PM PDT 24 Jun 10 09:02:21 PM PDT 24 26838804595 ps
T1342 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1900377984 Jun 10 08:25:44 PM PDT 24 Jun 10 09:14:15 PM PDT 24 34688683620 ps
T1343 /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.346521997 Jun 10 08:46:15 PM PDT 24 Jun 10 08:51:18 PM PDT 24 3585164750 ps
T1344 /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2365650562 Jun 10 08:43:20 PM PDT 24 Jun 10 08:49:31 PM PDT 24 6624362100 ps
T293 /workspace/coverage/default/0.chip_sw_data_integrity_escalation.3983517378 Jun 10 08:17:16 PM PDT 24 Jun 10 08:30:10 PM PDT 24 6124413136 ps
T388 /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.264586480 Jun 10 08:50:28 PM PDT 24 Jun 10 08:57:10 PM PDT 24 3622850612 ps
T344 /workspace/coverage/default/2.chip_plic_all_irqs_20.2345965664 Jun 10 08:38:13 PM PDT 24 Jun 10 08:51:05 PM PDT 24 4225910378 ps
T1345 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.2131473714 Jun 10 08:21:05 PM PDT 24 Jun 10 08:44:59 PM PDT 24 6867890200 ps
T711 /workspace/coverage/default/1.chip_sw_edn_boot_mode.818761204 Jun 10 08:25:35 PM PDT 24 Jun 10 08:34:00 PM PDT 24 2712409172 ps
T1346 /workspace/coverage/default/2.chip_sw_alert_handler_escalation.2096362721 Jun 10 08:35:25 PM PDT 24 Jun 10 08:46:03 PM PDT 24 4689907856 ps
T1347 /workspace/coverage/default/1.chip_sw_gpio_smoketest.1780479369 Jun 10 08:31:48 PM PDT 24 Jun 10 08:35:40 PM PDT 24 2394560505 ps
T1348 /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.1076904756 Jun 10 08:24:03 PM PDT 24 Jun 10 08:29:42 PM PDT 24 3073232304 ps
T1349 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2878068139 Jun 10 08:17:45 PM PDT 24 Jun 10 08:30:10 PM PDT 24 4453362251 ps
T1350 /workspace/coverage/default/3.chip_tap_straps_dev.3374912217 Jun 10 08:41:29 PM PDT 24 Jun 10 08:44:16 PM PDT 24 2096017946 ps
T1351 /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.2468550843 Jun 10 08:36:10 PM PDT 24 Jun 10 08:42:35 PM PDT 24 7485107888 ps
T185 /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.3773163729 Jun 10 08:24:05 PM PDT 24 Jun 10 09:43:03 PM PDT 24 45434447698 ps
T1352 /workspace/coverage/default/60.chip_sw_all_escalation_resets.2808372845 Jun 10 08:48:25 PM PDT 24 Jun 10 08:59:09 PM PDT 24 4406312342 ps
T413 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.818683294 Jun 10 08:21:25 PM PDT 24 Jun 10 08:51:41 PM PDT 24 22171263100 ps
T1353 /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.273624480 Jun 10 08:33:32 PM PDT 24 Jun 10 08:40:47 PM PDT 24 4104354602 ps
T1354 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.861267886 Jun 10 08:25:42 PM PDT 24 Jun 10 08:35:48 PM PDT 24 4251738336 ps
T1355 /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.352124235 Jun 10 08:47:25 PM PDT 24 Jun 10 08:53:51 PM PDT 24 3350435126 ps
T1356 /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.2226505057 Jun 10 08:17:45 PM PDT 24 Jun 10 08:19:56 PM PDT 24 3520919776 ps
T1357 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.4071757342 Jun 10 08:28:38 PM PDT 24 Jun 10 08:38:37 PM PDT 24 4800805912 ps
T1358 /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.2791156107 Jun 10 08:42:08 PM PDT 24 Jun 10 08:51:31 PM PDT 24 3365436608 ps
T414 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.428401698 Jun 10 08:32:24 PM PDT 24 Jun 10 08:54:26 PM PDT 24 20716285656 ps
T1359 /workspace/coverage/default/0.chip_tap_straps_prod.2051232349 Jun 10 08:23:22 PM PDT 24 Jun 10 08:54:57 PM PDT 24 16460940747 ps
T1360 /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.1036857879 Jun 10 08:28:22 PM PDT 24 Jun 10 08:35:46 PM PDT 24 4094928490 ps
T323 /workspace/coverage/default/62.chip_sw_all_escalation_resets.1763315116 Jun 10 08:49:23 PM PDT 24 Jun 10 08:58:47 PM PDT 24 6183514904 ps
T255 /workspace/coverage/default/92.chip_sw_all_escalation_resets.268003809 Jun 10 08:51:54 PM PDT 24 Jun 10 09:01:40 PM PDT 24 5700733044 ps
T1361 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.2929271679 Jun 10 08:41:27 PM PDT 24 Jun 10 08:50:41 PM PDT 24 6842998976 ps
T1362 /workspace/coverage/default/0.chip_sw_aes_enc.2744593834 Jun 10 08:19:10 PM PDT 24 Jun 10 08:23:36 PM PDT 24 2794902574 ps
T1363 /workspace/coverage/default/0.chip_sw_otbn_randomness.2057773428 Jun 10 08:20:39 PM PDT 24 Jun 10 08:34:58 PM PDT 24 6165373244 ps
T1364 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.523671105 Jun 10 08:29:59 PM PDT 24 Jun 10 08:40:40 PM PDT 24 4734602801 ps
T1365 /workspace/coverage/default/0.chip_sw_edn_auto_mode.3574607430 Jun 10 08:20:27 PM PDT 24 Jun 10 08:31:58 PM PDT 24 3510149572 ps
T9 /workspace/coverage/default/2.chip_jtag_csr_rw.2404180362 Jun 10 08:31:52 PM PDT 24 Jun 10 09:03:08 PM PDT 24 18975959080 ps
T427 /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.2411140542 Jun 10 08:26:59 PM PDT 24 Jun 10 08:32:24 PM PDT 24 2937655608 ps
T90 /workspace/coverage/default/96.chip_sw_all_escalation_resets.514931558 Jun 10 08:50:58 PM PDT 24 Jun 10 09:00:31 PM PDT 24 4984155956 ps
T159 /workspace/coverage/default/2.chip_plic_all_irqs_10.815964250 Jun 10 08:37:39 PM PDT 24 Jun 10 08:45:10 PM PDT 24 4106482296 ps
T324 /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.304866209 Jun 10 08:49:24 PM PDT 24 Jun 10 08:55:37 PM PDT 24 3393012632 ps
T333 /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1861621612 Jun 10 08:20:20 PM PDT 24 Jun 10 08:25:55 PM PDT 24 3356061864 ps
T428 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.1047332572 Jun 10 08:19:46 PM PDT 24 Jun 10 08:26:08 PM PDT 24 3212857577 ps
T429 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.3271644616 Jun 10 08:41:54 PM PDT 24 Jun 10 08:45:37 PM PDT 24 2960173259 ps
T430 /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.2190319415 Jun 10 08:45:11 PM PDT 24 Jun 10 09:01:12 PM PDT 24 9674504649 ps
T431 /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.4153021252 Jun 10 08:24:52 PM PDT 24 Jun 10 08:34:02 PM PDT 24 5484203180 ps
T1366 /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.1903307 Jun 10 08:34:07 PM PDT 24 Jun 10 08:41:32 PM PDT 24 6887363518 ps
T1367 /workspace/coverage/default/65.chip_sw_all_escalation_resets.3429581672 Jun 10 08:49:40 PM PDT 24 Jun 10 08:58:12 PM PDT 24 4789311020 ps
T1368 /workspace/coverage/default/18.chip_sw_all_escalation_resets.3883703931 Jun 10 08:44:46 PM PDT 24 Jun 10 08:53:32 PM PDT 24 4906726380 ps
T1369 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.2642223057 Jun 10 08:18:55 PM PDT 24 Jun 10 08:22:59 PM PDT 24 3348025452 ps
T1370 /workspace/coverage/default/1.chip_tap_straps_testunlock0.2841035537 Jun 10 08:27:46 PM PDT 24 Jun 10 08:35:25 PM PDT 24 5485592003 ps
T1371 /workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.4126970874 Jun 10 08:24:48 PM PDT 24 Jun 10 08:28:32 PM PDT 24 3262943133 ps
T201 /workspace/coverage/default/0.chip_sw_usbdev_setuprx.3757220068 Jun 10 08:17:04 PM PDT 24 Jun 10 08:25:40 PM PDT 24 4064785320 ps
T1372 /workspace/coverage/default/0.chip_sw_example_manufacturer.2548611756 Jun 10 08:17:49 PM PDT 24 Jun 10 08:20:55 PM PDT 24 2788720540 ps
T1373 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3077948851 Jun 10 08:44:12 PM PDT 24 Jun 10 08:55:28 PM PDT 24 4348559302 ps
T186 /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.503212939 Jun 10 08:17:03 PM PDT 24 Jun 10 09:43:58 PM PDT 24 44594907924 ps
T1374 /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2549851406 Jun 10 08:49:44 PM PDT 24 Jun 10 08:57:40 PM PDT 24 3891210026 ps
T1375 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.790228661 Jun 10 08:19:09 PM PDT 24 Jun 10 08:30:30 PM PDT 24 4439236180 ps
T1376 /workspace/coverage/default/1.chip_sw_rv_timer_irq.3781210383 Jun 10 08:24:30 PM PDT 24 Jun 10 08:30:52 PM PDT 24 3371389488 ps
T256 /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.2081929424 Jun 10 08:44:57 PM PDT 24 Jun 10 08:51:32 PM PDT 24 3837480804 ps
T1377 /workspace/coverage/default/1.chip_sw_example_manufacturer.3287015159 Jun 10 08:25:42 PM PDT 24 Jun 10 08:29:57 PM PDT 24 2993524064 ps
T1378 /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.3041689018 Jun 10 08:45:21 PM PDT 24 Jun 10 08:55:38 PM PDT 24 4635254896 ps
T1379 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.3691707242 Jun 10 08:28:28 PM PDT 24 Jun 10 09:35:38 PM PDT 24 15019197880 ps
T1380 /workspace/coverage/default/2.chip_sw_csrng_smoketest.3870719800 Jun 10 08:42:24 PM PDT 24 Jun 10 08:45:59 PM PDT 24 2822831530 ps
T1381 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.969986521 Jun 10 08:34:57 PM PDT 24 Jun 10 08:49:31 PM PDT 24 3700095603 ps
T818 /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.3055354381 Jun 10 08:43:05 PM PDT 24 Jun 10 08:50:54 PM PDT 24 4095659080 ps
T1382 /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.648201776 Jun 10 08:45:43 PM PDT 24 Jun 10 08:55:15 PM PDT 24 3701752164 ps
T834 /workspace/coverage/default/55.chip_sw_all_escalation_resets.1055538827 Jun 10 08:49:22 PM PDT 24 Jun 10 09:00:37 PM PDT 24 6106737418 ps
T400 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.2954723727 Jun 10 08:23:15 PM PDT 24 Jun 10 08:36:31 PM PDT 24 5339065490 ps
T16 /workspace/coverage/default/0.chip_sw_sleep_pin_retention.3837135831 Jun 10 08:16:48 PM PDT 24 Jun 10 08:22:18 PM PDT 24 3491145906 ps
T788 /workspace/coverage/default/31.chip_sw_all_escalation_resets.3543207962 Jun 10 08:46:00 PM PDT 24 Jun 10 08:56:22 PM PDT 24 5337185566 ps
T1383 /workspace/coverage/default/1.chip_sw_aes_entropy.1220322008 Jun 10 08:25:15 PM PDT 24 Jun 10 08:30:12 PM PDT 24 2967022420 ps
T1384 /workspace/coverage/default/3.chip_tap_straps_testunlock0.4235120610 Jun 10 08:41:53 PM PDT 24 Jun 10 08:52:22 PM PDT 24 5559552592 ps
T163 /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.1021731301 Jun 10 08:18:05 PM PDT 24 Jun 10 08:20:03 PM PDT 24 2218498585 ps
T75 /workspace/coverage/cover_reg_top/34.xbar_same_source.1377543001 Jun 10 07:58:40 PM PDT 24 Jun 10 07:58:56 PM PDT 24 448043355 ps
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