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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 95.48 94.18 95.43 94.99 96.65 99.51


Total test records in report: 2900
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T555 /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.3151046191 Jun 10 08:22:40 PM PDT 24 Jun 10 08:38:00 PM PDT 24 4500572664 ps
T1081 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.378522132 Jun 10 08:36:13 PM PDT 24 Jun 10 08:55:56 PM PDT 24 10346203021 ps
T1082 /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.1318071907 Jun 10 08:46:23 PM PDT 24 Jun 10 09:38:18 PM PDT 24 15313493786 ps
T1083 /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.892011259 Jun 10 08:21:29 PM PDT 24 Jun 10 08:28:56 PM PDT 24 5069230330 ps
T1084 /workspace/coverage/default/2.chip_sw_otbn_smoketest.1836177519 Jun 10 08:41:31 PM PDT 24 Jun 10 09:07:21 PM PDT 24 8198939562 ps
T1085 /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.2621591918 Jun 10 08:27:50 PM PDT 24 Jun 10 08:32:24 PM PDT 24 3213553056 ps
T1086 /workspace/coverage/default/2.chip_sw_uart_smoketest.1708855214 Jun 10 08:42:47 PM PDT 24 Jun 10 08:47:32 PM PDT 24 3017944680 ps
T1087 /workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.2306383006 Jun 10 08:19:04 PM PDT 24 Jun 10 08:23:29 PM PDT 24 3582710585 ps
T44 /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.3390227767 Jun 10 08:24:28 PM PDT 24 Jun 10 08:30:03 PM PDT 24 2731844232 ps
T1088 /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.942016328 Jun 10 08:45:14 PM PDT 24 Jun 10 09:09:10 PM PDT 24 8993470536 ps
T1089 /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.3536767331 Jun 10 08:17:39 PM PDT 24 Jun 10 08:25:37 PM PDT 24 4639645320 ps
T189 /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.3222974661 Jun 10 08:22:40 PM PDT 24 Jun 10 08:32:00 PM PDT 24 4425880717 ps
T1090 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.1413512523 Jun 10 08:24:29 PM PDT 24 Jun 10 09:54:19 PM PDT 24 46151827341 ps
T359 /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.1482801865 Jun 10 08:33:33 PM PDT 24 Jun 10 08:43:02 PM PDT 24 3688647488 ps
T1091 /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2848587174 Jun 10 08:25:07 PM PDT 24 Jun 10 08:33:23 PM PDT 24 18390605352 ps
T1092 /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.980126240 Jun 10 08:35:38 PM PDT 24 Jun 10 09:31:36 PM PDT 24 13894016994 ps
T1093 /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.1724501013 Jun 10 08:44:30 PM PDT 24 Jun 10 08:54:00 PM PDT 24 4514836988 ps
T1094 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.312417032 Jun 10 08:21:18 PM PDT 24 Jun 10 08:28:11 PM PDT 24 2699482408 ps
T158 /workspace/coverage/default/1.chip_plic_all_irqs_10.2213947063 Jun 10 08:28:28 PM PDT 24 Jun 10 08:36:35 PM PDT 24 4240611854 ps
T1095 /workspace/coverage/default/84.chip_sw_all_escalation_resets.680210269 Jun 10 08:51:47 PM PDT 24 Jun 10 09:03:51 PM PDT 24 5635033808 ps
T1096 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.3086175851 Jun 10 08:39:41 PM PDT 24 Jun 10 08:43:22 PM PDT 24 3289815166 ps
T35 /workspace/coverage/default/0.chip_sw_usbdev_dpi.2960241104 Jun 10 08:17:56 PM PDT 24 Jun 10 09:09:10 PM PDT 24 12280745912 ps
T733 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.428606598 Jun 10 08:26:02 PM PDT 24 Jun 10 08:27:50 PM PDT 24 2573869044 ps
T1097 /workspace/coverage/default/1.chip_sw_example_concurrency.1597506942 Jun 10 08:25:34 PM PDT 24 Jun 10 08:29:16 PM PDT 24 3334729176 ps
T167 /workspace/coverage/default/67.chip_sw_all_escalation_resets.984564591 Jun 10 08:49:37 PM PDT 24 Jun 10 08:58:38 PM PDT 24 5355842984 ps
T1098 /workspace/coverage/default/4.chip_sw_data_integrity_escalation.686010401 Jun 10 08:44:02 PM PDT 24 Jun 10 08:56:11 PM PDT 24 5604405428 ps
T1099 /workspace/coverage/default/2.chip_sw_edn_auto_mode.2370366772 Jun 10 08:36:08 PM PDT 24 Jun 10 09:01:43 PM PDT 24 6908522000 ps
T1100 /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.3512877901 Jun 10 08:44:09 PM PDT 24 Jun 10 08:52:51 PM PDT 24 6780765203 ps
T847 /workspace/coverage/default/37.chip_sw_all_escalation_resets.1599732644 Jun 10 08:46:46 PM PDT 24 Jun 10 08:57:08 PM PDT 24 4395009096 ps
T341 /workspace/coverage/default/0.chip_plic_all_irqs_20.1595251831 Jun 10 08:20:53 PM PDT 24 Jun 10 08:36:16 PM PDT 24 4703972684 ps
T851 /workspace/coverage/default/19.chip_sw_all_escalation_resets.2895713340 Jun 10 08:44:54 PM PDT 24 Jun 10 08:54:35 PM PDT 24 5818143028 ps
T206 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.3642531548 Jun 10 08:19:00 PM PDT 24 Jun 10 08:27:02 PM PDT 24 4082004776 ps
T1101 /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.3818980559 Jun 10 08:23:14 PM PDT 24 Jun 10 08:31:32 PM PDT 24 6488245240 ps
T234 /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.1094944513 Jun 10 08:37:09 PM PDT 24 Jun 10 09:40:28 PM PDT 24 13770723148 ps
T373 /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.1855685511 Jun 10 08:20:30 PM PDT 24 Jun 10 08:25:09 PM PDT 24 3243339067 ps
T270 /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.2586023527 Jun 10 08:44:50 PM PDT 24 Jun 10 08:51:29 PM PDT 24 4069915656 ps
T1102 /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.1355922037 Jun 10 08:22:27 PM PDT 24 Jun 10 08:26:45 PM PDT 24 2549527648 ps
T1103 /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.2879033053 Jun 10 08:37:54 PM PDT 24 Jun 10 08:43:22 PM PDT 24 2892932216 ps
T1104 /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.4043111123 Jun 10 08:42:46 PM PDT 24 Jun 10 08:48:31 PM PDT 24 3334757070 ps
T822 /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.2596169554 Jun 10 08:47:34 PM PDT 24 Jun 10 08:55:08 PM PDT 24 3943670420 ps
T364 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.3379906758 Jun 10 08:23:06 PM PDT 24 Jun 10 08:34:54 PM PDT 24 3889667048 ps
T1105 /workspace/coverage/default/0.chip_sw_kmac_idle.873328982 Jun 10 08:19:59 PM PDT 24 Jun 10 08:25:13 PM PDT 24 3167960300 ps
T1106 /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.3015996606 Jun 10 08:33:34 PM PDT 24 Jun 10 08:53:37 PM PDT 24 5650899526 ps
T1107 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.830159581 Jun 10 08:20:49 PM PDT 24 Jun 10 08:57:21 PM PDT 24 9906924528 ps
T812 /workspace/coverage/default/13.chip_sw_all_escalation_resets.2026515166 Jun 10 08:45:06 PM PDT 24 Jun 10 08:54:19 PM PDT 24 5229482076 ps
T1108 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.1592500896 Jun 10 08:33:29 PM PDT 24 Jun 10 08:37:46 PM PDT 24 3015396824 ps
T734 /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.1401272797 Jun 10 08:19:13 PM PDT 24 Jun 10 08:21:54 PM PDT 24 3888380069 ps
T73 /workspace/coverage/default/0.chip_sw_usbdev_pincfg.4248722175 Jun 10 08:18:58 PM PDT 24 Jun 10 10:14:47 PM PDT 24 32524169760 ps
T1109 /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.2159323489 Jun 10 08:44:37 PM PDT 24 Jun 10 08:52:07 PM PDT 24 5197160117 ps
T814 /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.3217987560 Jun 10 08:51:46 PM PDT 24 Jun 10 08:58:28 PM PDT 24 4482952568 ps
T1110 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1344536180 Jun 10 08:40:25 PM PDT 24 Jun 10 08:59:35 PM PDT 24 7423047763 ps
T845 /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.3440457273 Jun 10 08:48:59 PM PDT 24 Jun 10 08:56:40 PM PDT 24 4097055120 ps
T1111 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.1377932354 Jun 10 08:30:54 PM PDT 24 Jun 10 08:36:35 PM PDT 24 2985154108 ps
T805 /workspace/coverage/default/71.chip_sw_all_escalation_resets.3333070976 Jun 10 08:50:05 PM PDT 24 Jun 10 08:58:41 PM PDT 24 5296017660 ps
T1112 /workspace/coverage/default/2.chip_tap_straps_testunlock0.652570294 Jun 10 08:38:29 PM PDT 24 Jun 10 08:45:37 PM PDT 24 5163558766 ps
T1113 /workspace/coverage/default/4.chip_tap_straps_prod.1267039719 Jun 10 08:42:48 PM PDT 24 Jun 10 08:45:30 PM PDT 24 2370512442 ps
T798 /workspace/coverage/default/35.chip_sw_all_escalation_resets.509815232 Jun 10 08:46:44 PM PDT 24 Jun 10 08:56:02 PM PDT 24 5586221592 ps
T1114 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.902327360 Jun 10 08:32:59 PM PDT 24 Jun 10 09:09:06 PM PDT 24 11636573160 ps
T735 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.4249267845 Jun 10 08:23:32 PM PDT 24 Jun 10 08:25:23 PM PDT 24 2701900159 ps
T827 /workspace/coverage/default/25.chip_sw_all_escalation_resets.3230487507 Jun 10 08:45:50 PM PDT 24 Jun 10 08:56:02 PM PDT 24 5145619776 ps
T1115 /workspace/coverage/default/1.chip_sival_flash_info_access.2221914729 Jun 10 08:23:38 PM PDT 24 Jun 10 08:28:39 PM PDT 24 3620754920 ps
T62 /workspace/coverage/default/0.chip_sw_sleep_pin_wake.529565329 Jun 10 08:20:17 PM PDT 24 Jun 10 08:30:25 PM PDT 24 6330957750 ps
T1116 /workspace/coverage/default/0.chip_sw_hmac_smoketest.1636362105 Jun 10 08:24:52 PM PDT 24 Jun 10 08:30:52 PM PDT 24 3798292000 ps
T1117 /workspace/coverage/default/94.chip_sw_all_escalation_resets.2344745664 Jun 10 08:50:16 PM PDT 24 Jun 10 08:58:52 PM PDT 24 4658788200 ps
T1118 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.4088694392 Jun 10 08:45:40 PM PDT 24 Jun 10 08:53:38 PM PDT 24 4490557352 ps
T79 /workspace/coverage/default/0.chip_jtag_csr_rw.1989403810 Jun 10 08:11:34 PM PDT 24 Jun 10 08:31:04 PM PDT 24 10473580040 ps
T1119 /workspace/coverage/default/1.chip_sw_aes_idle.1942780249 Jun 10 08:28:15 PM PDT 24 Jun 10 08:32:43 PM PDT 24 3372502684 ps
T1120 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.3623934244 Jun 10 08:16:58 PM PDT 24 Jun 10 08:27:44 PM PDT 24 4268099960 ps
T1121 /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.3353027767 Jun 10 08:17:37 PM PDT 24 Jun 10 08:19:45 PM PDT 24 2496420502 ps
T1122 /workspace/coverage/default/0.chip_sw_kmac_entropy.2919406675 Jun 10 08:20:07 PM PDT 24 Jun 10 08:24:19 PM PDT 24 2787495276 ps
T1123 /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.625116298 Jun 10 08:25:28 PM PDT 24 Jun 10 08:30:17 PM PDT 24 3644986670 ps
T379 /workspace/coverage/default/1.chip_sw_inject_scramble_seed.691243369 Jun 10 08:23:21 PM PDT 24 Jun 10 11:40:34 PM PDT 24 65432012368 ps
T1124 /workspace/coverage/default/2.chip_sw_example_manufacturer.3437357186 Jun 10 08:33:05 PM PDT 24 Jun 10 08:36:23 PM PDT 24 2774831866 ps
T1125 /workspace/coverage/default/0.chip_sw_csrng_kat_test.717804776 Jun 10 08:19:27 PM PDT 24 Jun 10 08:24:03 PM PDT 24 3125403144 ps
T1126 /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.1420621747 Jun 10 08:18:17 PM PDT 24 Jun 10 08:23:43 PM PDT 24 3821159886 ps
T1127 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.1750244475 Jun 10 08:46:19 PM PDT 24 Jun 10 09:41:20 PM PDT 24 15020903600 ps
T1128 /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.3978906887 Jun 10 08:21:06 PM PDT 24 Jun 10 08:27:57 PM PDT 24 3034654104 ps
T1129 /workspace/coverage/default/1.chip_sw_kmac_smoketest.295588072 Jun 10 08:32:45 PM PDT 24 Jun 10 08:37:16 PM PDT 24 2453347590 ps
T15 /workspace/coverage/default/1.chip_sw_sleep_pin_retention.2117962277 Jun 10 08:23:44 PM PDT 24 Jun 10 08:29:41 PM PDT 24 4008644544 ps
T1130 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.3804275485 Jun 10 08:30:51 PM PDT 24 Jun 10 08:38:43 PM PDT 24 3670701948 ps
T1131 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.787473982 Jun 10 08:39:44 PM PDT 24 Jun 10 08:50:04 PM PDT 24 3997986430 ps
T412 /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.1644783618 Jun 10 08:29:42 PM PDT 24 Jun 10 08:35:46 PM PDT 24 3642671876 ps
T268 /workspace/coverage/default/34.chip_sw_all_escalation_resets.2247416184 Jun 10 08:47:06 PM PDT 24 Jun 10 08:57:07 PM PDT 24 5694744820 ps
T1132 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.827210800 Jun 10 08:21:20 PM PDT 24 Jun 10 08:53:18 PM PDT 24 8898283302 ps
T852 /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.2703968153 Jun 10 08:44:14 PM PDT 24 Jun 10 08:51:49 PM PDT 24 4296785600 ps
T190 /workspace/coverage/default/1.chip_sw_spi_device_pass_through.2327977728 Jun 10 08:31:14 PM PDT 24 Jun 10 08:45:47 PM PDT 24 7524199921 ps
T1133 /workspace/coverage/default/2.chip_sw_clkmgr_jitter.4000232129 Jun 10 08:38:18 PM PDT 24 Jun 10 08:42:13 PM PDT 24 2803966794 ps
T853 /workspace/coverage/default/77.chip_sw_all_escalation_resets.2477627728 Jun 10 08:52:58 PM PDT 24 Jun 10 09:01:47 PM PDT 24 6096855384 ps
T1134 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1411146380 Jun 10 08:26:56 PM PDT 24 Jun 10 09:09:13 PM PDT 24 10699778629 ps
T1135 /workspace/coverage/default/2.chip_sw_aes_entropy.4061131906 Jun 10 08:38:15 PM PDT 24 Jun 10 08:43:21 PM PDT 24 3552979466 ps
T207 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.2236038036 Jun 10 08:28:19 PM PDT 24 Jun 10 08:37:58 PM PDT 24 5128083180 ps
T1136 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.2242501672 Jun 10 08:25:30 PM PDT 24 Jun 10 09:47:39 PM PDT 24 22794821992 ps
T1137 /workspace/coverage/default/2.rom_e2e_shutdown_output.3697405701 Jun 10 08:44:50 PM PDT 24 Jun 10 09:29:19 PM PDT 24 27252783166 ps
T1138 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.452051144 Jun 10 08:20:07 PM PDT 24 Jun 10 08:30:06 PM PDT 24 4629886332 ps
T458 /workspace/coverage/default/6.chip_sw_all_escalation_resets.3300899779 Jun 10 08:44:20 PM PDT 24 Jun 10 08:52:53 PM PDT 24 4250928754 ps
T708 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2194859240 Jun 10 08:20:19 PM PDT 24 Jun 10 09:49:28 PM PDT 24 25170601330 ps
T1139 /workspace/coverage/default/1.rom_keymgr_functest.239539441 Jun 10 08:31:59 PM PDT 24 Jun 10 08:43:52 PM PDT 24 5115656990 ps
T351 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.2806187000 Jun 10 08:18:37 PM PDT 24 Jun 10 08:32:51 PM PDT 24 5217414456 ps
T375 /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3136910477 Jun 10 08:45:03 PM PDT 24 Jun 10 09:25:01 PM PDT 24 13350021506 ps
T1140 /workspace/coverage/default/0.chip_sw_clkmgr_jitter.4104782203 Jun 10 08:20:31 PM PDT 24 Jun 10 08:23:28 PM PDT 24 2485607267 ps
T139 /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.3361864325 Jun 10 08:42:18 PM PDT 24 Jun 10 08:55:31 PM PDT 24 9062290104 ps
T318 /workspace/coverage/default/22.chip_sw_all_escalation_resets.964443547 Jun 10 08:48:59 PM PDT 24 Jun 10 09:02:21 PM PDT 24 6455473936 ps
T813 /workspace/coverage/default/52.chip_sw_all_escalation_resets.2412666280 Jun 10 08:47:52 PM PDT 24 Jun 10 09:00:03 PM PDT 24 6374955148 ps
T1141 /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.3339831114 Jun 10 08:19:14 PM PDT 24 Jun 10 08:24:36 PM PDT 24 4865610264 ps
T1142 /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.4231162870 Jun 10 08:20:56 PM PDT 24 Jun 10 11:24:08 PM PDT 24 256383388200 ps
T1143 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3175190837 Jun 10 08:21:51 PM PDT 24 Jun 10 08:31:57 PM PDT 24 5205583033 ps
T1144 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.1152157559 Jun 10 08:25:59 PM PDT 24 Jun 10 09:22:50 PM PDT 24 20214321766 ps
T350 /workspace/coverage/default/0.chip_sw_entropy_src_csrng.3521414950 Jun 10 08:21:38 PM PDT 24 Jun 10 08:49:29 PM PDT 24 7134251460 ps
T1145 /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.196411665 Jun 10 08:27:30 PM PDT 24 Jun 10 08:34:19 PM PDT 24 3594475350 ps
T80 /workspace/coverage/default/1.chip_jtag_mem_access.1302691062 Jun 10 08:21:22 PM PDT 24 Jun 10 08:46:32 PM PDT 24 13491421010 ps
T1146 /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.3488662499 Jun 10 08:18:49 PM PDT 24 Jun 10 10:04:15 PM PDT 24 49263112693 ps
T1147 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.664616241 Jun 10 08:25:54 PM PDT 24 Jun 10 08:53:39 PM PDT 24 7713913640 ps
T815 /workspace/coverage/default/68.chip_sw_all_escalation_resets.2243492404 Jun 10 08:49:02 PM PDT 24 Jun 10 08:59:53 PM PDT 24 5532599064 ps
T112 /workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.761677235 Jun 10 08:24:03 PM PDT 24 Jun 10 09:05:44 PM PDT 24 16056073779 ps
T1148 /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.2475741732 Jun 10 08:30:16 PM PDT 24 Jun 10 08:39:45 PM PDT 24 4533072120 ps
T759 /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.1997848883 Jun 10 08:46:59 PM PDT 24 Jun 10 08:54:39 PM PDT 24 4024425248 ps
T823 /workspace/coverage/default/28.chip_sw_all_escalation_resets.2858605743 Jun 10 08:46:17 PM PDT 24 Jun 10 08:58:07 PM PDT 24 5125173816 ps
T1149 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.1147084653 Jun 10 08:19:17 PM PDT 24 Jun 10 08:37:57 PM PDT 24 6030771972 ps
T1150 /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.4162335947 Jun 10 08:50:29 PM PDT 24 Jun 10 08:58:42 PM PDT 24 4141074696 ps
T1151 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2364243692 Jun 10 08:38:49 PM PDT 24 Jun 10 08:48:49 PM PDT 24 4089273388 ps
T1152 /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.3165270974 Jun 10 08:24:57 PM PDT 24 Jun 10 09:59:48 PM PDT 24 48925892050 ps
T768 /workspace/coverage/default/39.chip_sw_all_escalation_resets.3331022841 Jun 10 08:48:09 PM PDT 24 Jun 10 08:58:51 PM PDT 24 4816104676 ps
T357 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.3305819501 Jun 10 08:25:33 PM PDT 24 Jun 10 08:41:53 PM PDT 24 5069794858 ps
T842 /workspace/coverage/default/5.chip_sw_all_escalation_resets.1273488860 Jun 10 08:43:36 PM PDT 24 Jun 10 08:56:47 PM PDT 24 4870749600 ps
T1153 /workspace/coverage/default/4.chip_tap_straps_rma.3533098904 Jun 10 08:42:15 PM PDT 24 Jun 10 08:48:05 PM PDT 24 4567014346 ps
T1154 /workspace/coverage/default/2.rom_e2e_asm_init_prod.224510698 Jun 10 08:45:04 PM PDT 24 Jun 10 09:36:45 PM PDT 24 14612628488 ps
T81 /workspace/coverage/default/1.chip_jtag_csr_rw.2246964359 Jun 10 08:21:21 PM PDT 24 Jun 10 09:02:10 PM PDT 24 20587789013 ps
T1155 /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.1935251128 Jun 10 08:45:25 PM PDT 24 Jun 10 09:25:10 PM PDT 24 12869003654 ps
T854 /workspace/coverage/default/43.chip_sw_all_escalation_resets.587046122 Jun 10 08:46:18 PM PDT 24 Jun 10 08:56:40 PM PDT 24 5314844958 ps
T819 /workspace/coverage/default/85.chip_sw_all_escalation_resets.3847971387 Jun 10 08:50:41 PM PDT 24 Jun 10 09:00:10 PM PDT 24 4708997078 ps
T1156 /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.4194048443 Jun 10 08:36:08 PM PDT 24 Jun 10 08:56:41 PM PDT 24 5687318164 ps
T319 /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.3199079173 Jun 10 08:45:13 PM PDT 24 Jun 10 08:52:25 PM PDT 24 3517362624 ps
T48 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.558976832 Jun 10 08:34:53 PM PDT 24 Jun 10 08:43:35 PM PDT 24 5874386632 ps
T1157 /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.3333323411 Jun 10 08:19:51 PM PDT 24 Jun 10 08:37:09 PM PDT 24 5009864490 ps
T358 /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.1760847368 Jun 10 08:22:48 PM PDT 24 Jun 10 08:31:21 PM PDT 24 3970143136 ps
T1158 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.1633066895 Jun 10 08:26:48 PM PDT 24 Jun 10 09:34:57 PM PDT 24 14203933408 ps
T459 /workspace/coverage/default/0.rom_e2e_jtag_inject_dev.3815891222 Jun 10 08:23:48 PM PDT 24 Jun 10 09:03:42 PM PDT 24 31884682134 ps
T405 /workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.1130284258 Jun 10 08:21:23 PM PDT 24 Jun 10 08:23:29 PM PDT 24 2667175200 ps
T1159 /workspace/coverage/default/64.chip_sw_all_escalation_resets.3171245667 Jun 10 08:48:37 PM PDT 24 Jun 10 08:57:11 PM PDT 24 4195267208 ps
T460 /workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.4052351771 Jun 10 08:23:25 PM PDT 24 Jun 10 09:17:00 PM PDT 24 39979516059 ps
T1160 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.460276095 Jun 10 08:35:07 PM PDT 24 Jun 10 08:50:53 PM PDT 24 9457107908 ps
T1161 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.3004707956 Jun 10 08:19:37 PM PDT 24 Jun 10 08:46:10 PM PDT 24 8586437100 ps
T1162 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.1284621868 Jun 10 08:18:35 PM PDT 24 Jun 10 08:29:19 PM PDT 24 8201974280 ps
T1163 /workspace/coverage/default/0.chip_sw_uart_tx_rx.107411484 Jun 10 08:18:01 PM PDT 24 Jun 10 08:27:20 PM PDT 24 4657346226 ps
T1164 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2977095382 Jun 10 08:25:35 PM PDT 24 Jun 10 08:50:06 PM PDT 24 12834197791 ps
T198 /workspace/coverage/default/2.chip_jtag_mem_access.1736437036 Jun 10 08:31:34 PM PDT 24 Jun 10 08:55:48 PM PDT 24 14048312712 ps
T1165 /workspace/coverage/default/0.chip_sw_power_idle_load.239637367 Jun 10 08:21:53 PM PDT 24 Jun 10 08:32:05 PM PDT 24 4339606186 ps
T1166 /workspace/coverage/default/1.chip_sw_plic_sw_irq.1682148252 Jun 10 08:28:08 PM PDT 24 Jun 10 08:32:36 PM PDT 24 3115125784 ps
T1167 /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.762342268 Jun 10 08:32:56 PM PDT 24 Jun 10 08:42:29 PM PDT 24 5461059850 ps
T1168 /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.2373439114 Jun 10 08:41:45 PM PDT 24 Jun 10 08:46:27 PM PDT 24 3316914172 ps
T20 /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2111994071 Jun 10 08:17:54 PM PDT 24 Jun 10 08:22:17 PM PDT 24 3284754059 ps
T1169 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.3155897981 Jun 10 08:19:56 PM PDT 24 Jun 10 08:30:45 PM PDT 24 5679849059 ps
T1170 /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.1812537427 Jun 10 08:23:52 PM PDT 24 Jun 10 09:53:04 PM PDT 24 47071716900 ps
T381 /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2745819265 Jun 10 08:38:48 PM PDT 24 Jun 10 08:46:36 PM PDT 24 5364191800 ps
T278 /workspace/coverage/default/0.rom_e2e_jtag_debug_dev.2726352787 Jun 10 08:22:49 PM PDT 24 Jun 10 09:03:27 PM PDT 24 13347398969 ps
T1171 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.2103035732 Jun 10 08:35:28 PM PDT 24 Jun 10 09:02:17 PM PDT 24 7387392050 ps
T829 /workspace/coverage/default/16.chip_sw_all_escalation_resets.1607681560 Jun 10 08:46:12 PM PDT 24 Jun 10 08:57:05 PM PDT 24 5204992308 ps
T1172 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.580985271 Jun 10 08:26:16 PM PDT 24 Jun 10 09:21:44 PM PDT 24 14370611848 ps
T1173 /workspace/coverage/default/1.rom_e2e_asm_init_dev.1272847056 Jun 10 08:36:09 PM PDT 24 Jun 10 09:29:07 PM PDT 24 14033091079 ps
T199 /workspace/coverage/default/0.chip_jtag_mem_access.4288245155 Jun 10 08:11:33 PM PDT 24 Jun 10 08:40:56 PM PDT 24 14037042917 ps
T349 /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.3367468374 Jun 10 08:27:27 PM PDT 24 Jun 10 08:55:27 PM PDT 24 11395259608 ps
T738 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.1987128122 Jun 10 08:27:00 PM PDT 24 Jun 10 08:30:21 PM PDT 24 2305705454 ps
T1174 /workspace/coverage/default/3.chip_sw_uart_tx_rx.497126144 Jun 10 08:41:39 PM PDT 24 Jun 10 08:54:21 PM PDT 24 4792235890 ps
T1175 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.4175147972 Jun 10 08:25:15 PM PDT 24 Jun 10 08:43:28 PM PDT 24 7581372130 ps
T1176 /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.1991302812 Jun 10 08:25:46 PM PDT 24 Jun 10 08:42:19 PM PDT 24 10233018089 ps
T1177 /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.1213480192 Jun 10 08:25:53 PM PDT 24 Jun 10 08:34:46 PM PDT 24 8478935096 ps
T1178 /workspace/coverage/default/2.chip_sw_hmac_smoketest.2159159446 Jun 10 08:40:36 PM PDT 24 Jun 10 08:45:37 PM PDT 24 3074283912 ps
T1179 /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.4175139896 Jun 10 08:25:24 PM PDT 24 Jun 10 08:37:31 PM PDT 24 4789140488 ps
T1180 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.1827342871 Jun 10 08:26:47 PM PDT 24 Jun 10 08:30:23 PM PDT 24 2765678259 ps
T1181 /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.1869737078 Jun 10 08:38:08 PM PDT 24 Jun 10 08:42:42 PM PDT 24 3205963450 ps
T1182 /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.362431607 Jun 10 08:42:12 PM PDT 24 Jun 10 09:06:59 PM PDT 24 8330853610 ps
T320 /workspace/coverage/default/54.chip_sw_all_escalation_resets.2218436152 Jun 10 08:49:14 PM PDT 24 Jun 10 08:56:18 PM PDT 24 5138727716 ps
T1183 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.3219763509 Jun 10 08:39:32 PM PDT 24 Jun 10 08:56:29 PM PDT 24 7449444088 ps
T1184 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.3048628533 Jun 10 08:22:43 PM PDT 24 Jun 10 08:31:59 PM PDT 24 6119709080 ps
T1185 /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.1158629801 Jun 10 08:44:32 PM PDT 24 Jun 10 09:48:39 PM PDT 24 14020127926 ps
T1186 /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.2726666108 Jun 10 08:35:32 PM PDT 24 Jun 10 08:52:49 PM PDT 24 7870239068 ps
T849 /workspace/coverage/default/90.chip_sw_all_escalation_resets.2806750891 Jun 10 08:50:39 PM PDT 24 Jun 10 09:00:19 PM PDT 24 4833099938 ps
T1187 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.3108957302 Jun 10 08:17:44 PM PDT 24 Jun 10 08:35:51 PM PDT 24 6361634917 ps
T1188 /workspace/coverage/default/2.chip_tap_straps_rma.3876891165 Jun 10 08:38:38 PM PDT 24 Jun 10 08:44:44 PM PDT 24 3850488495 ps
T291 /workspace/coverage/default/2.chip_sw_data_integrity_escalation.2854689627 Jun 10 08:32:23 PM PDT 24 Jun 10 08:44:39 PM PDT 24 4687505678 ps
T294 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1168085370 Jun 10 08:24:13 PM PDT 24 Jun 10 08:52:01 PM PDT 24 15060427785 ps
T295 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2807897129 Jun 10 08:40:06 PM PDT 24 Jun 10 08:52:08 PM PDT 24 4711079765 ps
T296 /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.2825417537 Jun 10 08:47:23 PM PDT 24 Jun 10 08:54:02 PM PDT 24 3913219800 ps
T297 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2538375401 Jun 10 08:28:48 PM PDT 24 Jun 10 08:41:31 PM PDT 24 4022255156 ps
T298 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3705123141 Jun 10 08:20:53 PM PDT 24 Jun 10 08:32:23 PM PDT 24 5141697343 ps
T299 /workspace/coverage/default/0.rom_e2e_asm_init_prod.1530942215 Jun 10 08:27:49 PM PDT 24 Jun 10 09:45:29 PM PDT 24 14672977439 ps
T300 /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.489860240 Jun 10 08:44:12 PM PDT 24 Jun 10 08:51:35 PM PDT 24 4069961286 ps
T301 /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.1758578497 Jun 10 08:29:17 PM PDT 24 Jun 10 08:36:30 PM PDT 24 3040409116 ps
T302 /workspace/coverage/default/0.chip_sw_rv_timer_irq.3068855602 Jun 10 08:18:32 PM PDT 24 Jun 10 08:22:12 PM PDT 24 3232694148 ps
T1189 /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.764680826 Jun 10 08:42:26 PM PDT 24 Jun 10 08:47:13 PM PDT 24 3045000444 ps
T1190 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.3068382932 Jun 10 08:32:13 PM PDT 24 Jun 10 08:49:17 PM PDT 24 5272945188 ps
T1191 /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.1994452539 Jun 10 08:34:42 PM PDT 24 Jun 10 09:09:02 PM PDT 24 36361788590 ps
T1192 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.2867704484 Jun 10 08:27:38 PM PDT 24 Jun 10 09:26:18 PM PDT 24 13888335342 ps
T836 /workspace/coverage/default/47.chip_sw_all_escalation_resets.79378079 Jun 10 08:48:13 PM PDT 24 Jun 10 08:58:23 PM PDT 24 5389633976 ps
T830 /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.740308640 Jun 10 08:51:41 PM PDT 24 Jun 10 08:58:12 PM PDT 24 4364433192 ps
T1193 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1567620249 Jun 10 08:42:55 PM PDT 24 Jun 10 09:01:34 PM PDT 24 8791325714 ps
T1194 /workspace/coverage/default/1.chip_sw_hmac_smoketest.1028535583 Jun 10 08:33:03 PM PDT 24 Jun 10 08:37:58 PM PDT 24 2706185224 ps
T1195 /workspace/coverage/default/0.chip_sw_hmac_enc.488617220 Jun 10 08:20:02 PM PDT 24 Jun 10 08:25:35 PM PDT 24 2705879000 ps
T1196 /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.3044912834 Jun 10 08:45:57 PM PDT 24 Jun 10 08:58:47 PM PDT 24 10209719803 ps
T1197 /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.3798872479 Jun 10 08:41:20 PM PDT 24 Jun 10 08:45:37 PM PDT 24 2537280100 ps
T1198 /workspace/coverage/default/1.chip_sw_hmac_enc_idle.997040927 Jun 10 08:33:15 PM PDT 24 Jun 10 08:38:38 PM PDT 24 2290265304 ps
T1199 /workspace/coverage/default/0.chip_sw_hmac_oneshot.1437127287 Jun 10 08:19:34 PM PDT 24 Jun 10 08:25:36 PM PDT 24 3676251734 ps
T833 /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.1971990669 Jun 10 08:46:27 PM PDT 24 Jun 10 08:51:53 PM PDT 24 3561937152 ps
T1200 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.306705240 Jun 10 08:24:39 PM PDT 24 Jun 10 09:24:26 PM PDT 24 14216913620 ps
T153 /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.816624661 Jun 10 08:26:09 PM PDT 24 Jun 10 11:50:29 PM PDT 24 57174892961 ps
T338 /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.1200781112 Jun 10 08:26:52 PM PDT 24 Jun 10 08:37:12 PM PDT 24 9290756483 ps
T1201 /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.2715443973 Jun 10 08:28:52 PM PDT 24 Jun 10 08:37:55 PM PDT 24 4808537364 ps
T1202 /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.293375663 Jun 10 08:33:02 PM PDT 24 Jun 10 08:41:30 PM PDT 24 3619897960 ps
T767 /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.3063146781 Jun 10 08:48:12 PM PDT 24 Jun 10 08:53:40 PM PDT 24 3660572164 ps
T1203 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2354366612 Jun 10 08:33:37 PM PDT 24 Jun 10 08:35:28 PM PDT 24 2700775706 ps
T51 /workspace/coverage/default/1.chip_sw_spi_device_tpm.1464328166 Jun 10 08:23:02 PM PDT 24 Jun 10 08:29:25 PM PDT 24 3591513749 ps
T200 /workspace/coverage/default/0.chip_sw_usbdev_vbus.719637 Jun 10 08:17:17 PM PDT 24 Jun 10 08:20:30 PM PDT 24 2888795432 ps
T1204 /workspace/coverage/default/1.chip_sw_uart_tx_rx.634161918 Jun 10 08:23:22 PM PDT 24 Jun 10 08:36:13 PM PDT 24 4185129016 ps
T1205 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.127564402 Jun 10 08:22:53 PM PDT 24 Jun 10 08:33:49 PM PDT 24 4533761052 ps
T1206 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.406836012 Jun 10 08:36:43 PM PDT 24 Jun 10 08:48:35 PM PDT 24 5038140204 ps
T1207 /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.2108588420 Jun 10 08:37:51 PM PDT 24 Jun 10 08:48:39 PM PDT 24 9646430925 ps
T799 /workspace/coverage/default/88.chip_sw_all_escalation_resets.3827112044 Jun 10 08:50:52 PM PDT 24 Jun 10 08:59:56 PM PDT 24 4868571930 ps
T1208 /workspace/coverage/default/2.chip_sw_kmac_idle.3430073282 Jun 10 08:38:21 PM PDT 24 Jun 10 08:43:13 PM PDT 24 2433865464 ps
T1209 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.1534592135 Jun 10 08:26:35 PM PDT 24 Jun 10 09:22:41 PM PDT 24 13412981980 ps
T1210 /workspace/coverage/default/1.chip_sw_example_flash.2851873024 Jun 10 08:22:17 PM PDT 24 Jun 10 08:26:09 PM PDT 24 3538944650 ps
T38 /workspace/coverage/default/0.chip_sw_gpio.2172313385 Jun 10 08:18:24 PM PDT 24 Jun 10 08:24:35 PM PDT 24 3659354102 ps
T556 /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.526009359 Jun 10 08:36:27 PM PDT 24 Jun 10 08:49:48 PM PDT 24 5226640840 ps
T1211 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.2957588682 Jun 10 08:18:19 PM PDT 24 Jun 10 09:16:06 PM PDT 24 17728707450 ps
T808 /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.2385767439 Jun 10 08:46:15 PM PDT 24 Jun 10 08:52:51 PM PDT 24 3371696258 ps
T1212 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.2221930352 Jun 10 08:27:28 PM PDT 24 Jun 10 08:34:40 PM PDT 24 3040548638 ps
T1213 /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.291038734 Jun 10 08:20:33 PM PDT 24 Jun 10 08:48:11 PM PDT 24 11762270964 ps
T1214 /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.4198764036 Jun 10 08:43:55 PM PDT 24 Jun 10 08:52:46 PM PDT 24 4397454822 ps
T1215 /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.4137479486 Jun 10 08:25:18 PM PDT 24 Jun 10 08:29:10 PM PDT 24 2424836096 ps
T1216 /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.2058891964 Jun 10 08:17:20 PM PDT 24 Jun 10 08:35:55 PM PDT 24 11697145333 ps
T1217 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.298702009 Jun 10 08:21:32 PM PDT 24 Jun 10 08:54:45 PM PDT 24 26010438956 ps
T1218 /workspace/coverage/default/0.chip_sw_aes_entropy.1001519212 Jun 10 08:20:39 PM PDT 24 Jun 10 08:26:32 PM PDT 24 3055907772 ps
T1219 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.42077585 Jun 10 08:21:33 PM PDT 24 Jun 10 08:59:50 PM PDT 24 22953974184 ps
T1220 /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.3501693525 Jun 10 08:35:03 PM PDT 24 Jun 10 09:04:00 PM PDT 24 12597742180 ps
T730 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.2644511097 Jun 10 08:29:28 PM PDT 24 Jun 10 08:39:13 PM PDT 24 5038234153 ps
T1221 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.2577200889 Jun 10 08:39:17 PM PDT 24 Jun 10 08:48:10 PM PDT 24 3952924998 ps
T1222 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.782404827 Jun 10 08:18:32 PM PDT 24 Jun 10 08:31:02 PM PDT 24 7543860418 ps
T1223 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.3256741012 Jun 10 08:22:23 PM PDT 24 Jun 10 08:27:50 PM PDT 24 3322452430 ps
T1224 /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.3833699655 Jun 10 08:46:15 PM PDT 24 Jun 10 09:32:12 PM PDT 24 13486204494 ps
T1225 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.1691070350 Jun 10 08:38:10 PM PDT 24 Jun 10 08:48:14 PM PDT 24 7762812890 ps
T1226 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.4257034873 Jun 10 08:39:46 PM PDT 24 Jun 10 08:50:53 PM PDT 24 8662565322 ps
T1227 /workspace/coverage/default/0.chip_sw_kmac_app_rom.493170409 Jun 10 08:23:22 PM PDT 24 Jun 10 08:27:25 PM PDT 24 3411564492 ps
T806 /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.3566136593 Jun 10 08:47:10 PM PDT 24 Jun 10 08:55:00 PM PDT 24 3362836342 ps
T141 /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.4146611140 Jun 10 08:27:54 PM PDT 24 Jun 10 08:35:24 PM PDT 24 3408744540 ps
T1228 /workspace/coverage/default/2.chip_sw_all_escalation_resets.3470629536 Jun 10 08:31:49 PM PDT 24 Jun 10 08:45:11 PM PDT 24 5941371328 ps
T1229 /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.1522105199 Jun 10 08:27:14 PM PDT 24 Jun 10 08:42:24 PM PDT 24 5493882668 ps
T366 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.3147032801 Jun 10 08:18:22 PM PDT 24 Jun 10 08:32:04 PM PDT 24 4664689122 ps
T795 /workspace/coverage/default/45.chip_sw_all_escalation_resets.4157413542 Jun 10 08:49:55 PM PDT 24 Jun 10 08:59:24 PM PDT 24 4879079886 ps
T820 /workspace/coverage/default/23.chip_sw_all_escalation_resets.3488050616 Jun 10 08:46:27 PM PDT 24 Jun 10 09:02:13 PM PDT 24 5386888834 ps
T1230 /workspace/coverage/default/2.chip_tap_straps_prod.2021293784 Jun 10 08:38:27 PM PDT 24 Jun 10 08:52:28 PM PDT 24 8657311360 ps
T837 /workspace/coverage/default/14.chip_sw_all_escalation_resets.630342852 Jun 10 08:44:57 PM PDT 24 Jun 10 08:54:03 PM PDT 24 4172008600 ps
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