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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 95.52 93.75 95.49 94.47 97.53 99.64


Total test records in report: 2896
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T904 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.870041603 Jun 11 04:03:30 PM PDT 24 Jun 11 04:16:10 PM PDT 24 9563088705 ps
T199 /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.1614681104 Jun 11 04:26:48 PM PDT 24 Jun 11 04:49:14 PM PDT 24 8779021746 ps
T766 /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.1015914767 Jun 11 04:37:40 PM PDT 24 Jun 11 04:44:01 PM PDT 24 3607016710 ps
T905 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.1642966872 Jun 11 04:00:55 PM PDT 24 Jun 11 04:09:52 PM PDT 24 7177720375 ps
T906 /workspace/coverage/default/2.chip_sw_hmac_oneshot.1388303673 Jun 11 04:23:16 PM PDT 24 Jun 11 04:28:01 PM PDT 24 3573247030 ps
T783 /workspace/coverage/default/37.chip_sw_all_escalation_resets.1761657412 Jun 11 04:29:52 PM PDT 24 Jun 11 04:41:12 PM PDT 24 5715809860 ps
T341 /workspace/coverage/default/99.chip_sw_all_escalation_resets.3259080473 Jun 11 04:34:05 PM PDT 24 Jun 11 04:40:49 PM PDT 24 4832669408 ps
T149 /workspace/coverage/default/2.chip_plic_all_irqs_10.2554443039 Jun 11 04:26:22 PM PDT 24 Jun 11 04:34:24 PM PDT 24 3863899086 ps
T907 /workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.1173857747 Jun 11 04:26:09 PM PDT 24 Jun 11 05:31:31 PM PDT 24 17721548056 ps
T109 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3218026715 Jun 11 04:22:49 PM PDT 24 Jun 11 04:51:11 PM PDT 24 12911045926 ps
T271 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3105512756 Jun 11 04:22:48 PM PDT 24 Jun 11 04:33:33 PM PDT 24 5668625875 ps
T908 /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.2495483095 Jun 11 04:21:09 PM PDT 24 Jun 11 04:42:29 PM PDT 24 9685001310 ps
T104 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.1774877968 Jun 11 04:04:27 PM PDT 24 Jun 11 05:10:51 PM PDT 24 17484677388 ps
T909 /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.639750503 Jun 11 04:09:19 PM PDT 24 Jun 11 04:17:34 PM PDT 24 5001316700 ps
T85 /workspace/coverage/default/92.chip_sw_all_escalation_resets.3286080160 Jun 11 04:34:25 PM PDT 24 Jun 11 04:42:55 PM PDT 24 4344519904 ps
T910 /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.1858405465 Jun 11 04:12:16 PM PDT 24 Jun 11 04:19:29 PM PDT 24 4349742096 ps
T419 /workspace/coverage/default/1.chip_sw_kmac_entropy.3627295607 Jun 11 04:10:08 PM PDT 24 Jun 11 04:14:37 PM PDT 24 3087740750 ps
T911 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.3413315743 Jun 11 04:25:34 PM PDT 24 Jun 11 04:38:20 PM PDT 24 4493459118 ps
T912 /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.1515759741 Jun 11 04:15:41 PM PDT 24 Jun 11 04:19:58 PM PDT 24 2758076536 ps
T78 /workspace/coverage/default/2.chip_jtag_mem_access.1414940604 Jun 11 04:13:27 PM PDT 24 Jun 11 04:38:09 PM PDT 24 14076296675 ps
T371 /workspace/coverage/default/1.chip_sw_edn_boot_mode.3513787099 Jun 11 04:10:32 PM PDT 24 Jun 11 04:20:07 PM PDT 24 2820959410 ps
T913 /workspace/coverage/default/2.chip_sw_flash_crash_alert.2316470359 Jun 11 04:22:46 PM PDT 24 Jun 11 04:36:08 PM PDT 24 5346095304 ps
T914 /workspace/coverage/default/1.chip_sw_flash_ctrl_access.3271641668 Jun 11 04:07:16 PM PDT 24 Jun 11 04:25:49 PM PDT 24 6300267908 ps
T668 /workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.3534651860 Jun 11 04:07:15 PM PDT 24 Jun 11 04:56:13 PM PDT 24 31115738310 ps
T915 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.873645966 Jun 11 04:24:28 PM PDT 24 Jun 11 04:28:18 PM PDT 24 3518024649 ps
T137 /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.468004590 Jun 11 03:58:54 PM PDT 24 Jun 11 08:00:35 PM PDT 24 78151748008 ps
T916 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.3781252330 Jun 11 04:12:51 PM PDT 24 Jun 11 05:05:01 PM PDT 24 14289982944 ps
T138 /workspace/coverage/default/0.chip_sw_usbdev_config_host.3934374075 Jun 11 03:59:54 PM PDT 24 Jun 11 04:33:11 PM PDT 24 7458893808 ps
T917 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.1633130405 Jun 11 04:04:35 PM PDT 24 Jun 11 04:36:53 PM PDT 24 8556737264 ps
T694 /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3011163767 Jun 11 04:31:15 PM PDT 24 Jun 11 04:38:54 PM PDT 24 3239887760 ps
T918 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.3929344557 Jun 11 04:18:43 PM PDT 24 Jun 11 04:32:31 PM PDT 24 9240957676 ps
T919 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.2254731200 Jun 11 04:18:03 PM PDT 24 Jun 11 04:39:33 PM PDT 24 7033836150 ps
T502 /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.981235831 Jun 11 04:01:07 PM PDT 24 Jun 11 04:15:59 PM PDT 24 5001011820 ps
T920 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3856344951 Jun 11 04:21:43 PM PDT 24 Jun 11 04:31:24 PM PDT 24 4139864916 ps
T248 /workspace/coverage/default/70.chip_sw_all_escalation_resets.2818447316 Jun 11 04:34:13 PM PDT 24 Jun 11 04:41:20 PM PDT 24 4207917318 ps
T921 /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.470398753 Jun 11 04:24:55 PM PDT 24 Jun 11 04:32:07 PM PDT 24 6404093391 ps
T150 /workspace/coverage/default/0.chip_plic_all_irqs_10.2028970989 Jun 11 04:02:29 PM PDT 24 Jun 11 04:11:47 PM PDT 24 3867179960 ps
T922 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.1360677156 Jun 11 04:11:10 PM PDT 24 Jun 11 04:35:38 PM PDT 24 8259722828 ps
T923 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2313771044 Jun 11 04:02:41 PM PDT 24 Jun 11 04:11:55 PM PDT 24 3481511940 ps
T260 /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.3618247197 Jun 11 04:11:59 PM PDT 24 Jun 11 04:23:53 PM PDT 24 8616070719 ps
T924 /workspace/coverage/default/1.chip_sw_hmac_oneshot.340117657 Jun 11 04:13:20 PM PDT 24 Jun 11 04:20:04 PM PDT 24 2935007888 ps
T121 /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.1978778407 Jun 11 04:25:43 PM PDT 24 Jun 11 04:35:58 PM PDT 24 5829901272 ps
T925 /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2739110759 Jun 11 04:03:34 PM PDT 24 Jun 11 07:33:45 PM PDT 24 255568898274 ps
T926 /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.199499918 Jun 11 04:20:39 PM PDT 24 Jun 11 04:29:57 PM PDT 24 4567880616 ps
T698 /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.2137097537 Jun 11 04:32:04 PM PDT 24 Jun 11 04:38:19 PM PDT 24 3554676496 ps
T927 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.2975526608 Jun 11 04:01:06 PM PDT 24 Jun 11 04:11:43 PM PDT 24 5507940104 ps
T928 /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.278244358 Jun 11 04:17:49 PM PDT 24 Jun 11 04:25:45 PM PDT 24 5256316298 ps
T929 /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.653596562 Jun 11 04:26:19 PM PDT 24 Jun 11 04:43:42 PM PDT 24 13363818477 ps
T357 /workspace/coverage/default/31.chip_sw_all_escalation_resets.1129908103 Jun 11 04:29:33 PM PDT 24 Jun 11 04:39:37 PM PDT 24 4238978890 ps
T119 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.3146213190 Jun 11 04:21:51 PM PDT 24 Jun 11 04:30:42 PM PDT 24 6004134680 ps
T930 /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.2425085222 Jun 11 04:26:10 PM PDT 24 Jun 11 06:13:24 PM PDT 24 28544645850 ps
T743 /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.239285501 Jun 11 04:38:51 PM PDT 24 Jun 11 04:45:20 PM PDT 24 4348840990 ps
T931 /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.3100173389 Jun 11 04:26:20 PM PDT 24 Jun 11 04:48:06 PM PDT 24 8756946048 ps
T342 /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2190346629 Jun 11 04:08:33 PM PDT 24 Jun 11 04:17:12 PM PDT 24 18146710270 ps
T261 /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.2877681010 Jun 11 04:25:57 PM PDT 24 Jun 11 04:33:29 PM PDT 24 8637295340 ps
T312 /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.1736781500 Jun 11 04:19:39 PM PDT 24 Jun 11 04:52:25 PM PDT 24 13224821698 ps
T143 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.3434312942 Jun 11 04:09:43 PM PDT 24 Jun 11 05:11:20 PM PDT 24 18604036927 ps
T704 /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.964225667 Jun 11 04:31:37 PM PDT 24 Jun 11 04:39:50 PM PDT 24 4436366380 ps
T932 /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.843870873 Jun 11 04:25:19 PM PDT 24 Jun 11 04:28:38 PM PDT 24 2568268788 ps
T933 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.89370694 Jun 11 04:10:50 PM PDT 24 Jun 11 04:16:29 PM PDT 24 3021630552 ps
T324 /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.3389869488 Jun 11 04:00:04 PM PDT 24 Jun 11 04:09:58 PM PDT 24 4641883752 ps
T934 /workspace/coverage/default/0.chip_sw_ast_clk_outputs.394276181 Jun 11 04:03:42 PM PDT 24 Jun 11 04:21:12 PM PDT 24 8311830664 ps
T935 /workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.2511274137 Jun 11 04:10:31 PM PDT 24 Jun 11 04:33:27 PM PDT 24 8340516240 ps
T936 /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.3399234437 Jun 11 04:07:09 PM PDT 24 Jun 11 04:11:36 PM PDT 24 2994667929 ps
T272 /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.3985145427 Jun 11 04:11:42 PM PDT 24 Jun 11 04:19:17 PM PDT 24 3572302808 ps
T35 /workspace/coverage/default/1.chip_sw_gpio.2387709142 Jun 11 04:05:38 PM PDT 24 Jun 11 04:14:00 PM PDT 24 4077897391 ps
T937 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.949848989 Jun 11 04:13:03 PM PDT 24 Jun 11 05:17:04 PM PDT 24 14226005972 ps
T273 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.2247566055 Jun 11 04:03:39 PM PDT 24 Jun 11 04:15:11 PM PDT 24 4771076500 ps
T172 /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.3544671475 Jun 11 04:02:29 PM PDT 24 Jun 11 04:15:19 PM PDT 24 8147468680 ps
T757 /workspace/coverage/default/61.chip_sw_all_escalation_resets.2091589551 Jun 11 04:31:20 PM PDT 24 Jun 11 04:41:10 PM PDT 24 4873067044 ps
T938 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.230766087 Jun 11 04:11:21 PM PDT 24 Jun 11 05:02:50 PM PDT 24 14700806480 ps
T939 /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.4189803035 Jun 11 04:23:46 PM PDT 24 Jun 11 04:34:06 PM PDT 24 5415810748 ps
T940 /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.296886248 Jun 11 04:26:23 PM PDT 24 Jun 11 04:39:15 PM PDT 24 4383140906 ps
T351 /workspace/coverage/default/2.chip_sw_hmac_enc.123151119 Jun 11 04:21:29 PM PDT 24 Jun 11 04:27:56 PM PDT 24 3514040080 ps
T346 /workspace/coverage/default/10.chip_sw_all_escalation_resets.1831997019 Jun 11 04:26:05 PM PDT 24 Jun 11 04:36:25 PM PDT 24 4842155284 ps
T42 /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.4229781347 Jun 11 04:09:08 PM PDT 24 Jun 11 04:13:44 PM PDT 24 3137215524 ps
T347 /workspace/coverage/default/45.chip_sw_all_escalation_resets.1936619577 Jun 11 04:30:57 PM PDT 24 Jun 11 04:40:13 PM PDT 24 5593928900 ps
T941 /workspace/coverage/default/1.chip_tap_straps_dev.2579442511 Jun 11 04:13:49 PM PDT 24 Jun 11 04:17:31 PM PDT 24 3495252680 ps
T942 /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.949687426 Jun 11 04:17:04 PM PDT 24 Jun 11 04:51:17 PM PDT 24 27302737144 ps
T503 /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.3657901601 Jun 11 04:20:37 PM PDT 24 Jun 11 04:35:53 PM PDT 24 5301707832 ps
T640 /workspace/coverage/default/26.chip_sw_all_escalation_resets.1938572859 Jun 11 04:30:39 PM PDT 24 Jun 11 04:41:34 PM PDT 24 5206352566 ps
T775 /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.3138569912 Jun 11 04:28:38 PM PDT 24 Jun 11 04:34:55 PM PDT 24 3827720296 ps
T943 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.2243647158 Jun 11 04:05:46 PM PDT 24 Jun 11 04:22:51 PM PDT 24 8442269784 ps
T657 /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.2434911744 Jun 11 03:59:49 PM PDT 24 Jun 11 04:25:00 PM PDT 24 8731114680 ps
T221 /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.3789926192 Jun 11 04:07:47 PM PDT 24 Jun 11 04:16:17 PM PDT 24 4044416012 ps
T944 /workspace/coverage/default/2.rom_e2e_asm_init_rma.3856422361 Jun 11 04:28:04 PM PDT 24 Jun 11 05:33:22 PM PDT 24 14819119685 ps
T770 /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.2142013599 Jun 11 04:33:41 PM PDT 24 Jun 11 04:40:00 PM PDT 24 3731561656 ps
T721 /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3510892128 Jun 11 04:33:30 PM PDT 24 Jun 11 04:40:41 PM PDT 24 3860931560 ps
T274 /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.3926746134 Jun 11 04:19:35 PM PDT 24 Jun 11 04:28:32 PM PDT 24 4009668250 ps
T275 /workspace/coverage/default/3.chip_sw_data_integrity_escalation.1745544697 Jun 11 04:23:50 PM PDT 24 Jun 11 04:35:02 PM PDT 24 4803176800 ps
T681 /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.688724879 Jun 11 04:35:36 PM PDT 24 Jun 11 04:41:10 PM PDT 24 3251106592 ps
T167 /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.3739353179 Jun 11 04:12:07 PM PDT 24 Jun 11 04:21:20 PM PDT 24 9011356074 ps
T192 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.2961866918 Jun 11 04:09:43 PM PDT 24 Jun 11 04:49:02 PM PDT 24 24307802450 ps
T236 /workspace/coverage/default/1.chip_sw_plic_sw_irq.3302197245 Jun 11 04:12:44 PM PDT 24 Jun 11 04:17:39 PM PDT 24 3068553678 ps
T678 /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.4079476626 Jun 11 04:30:29 PM PDT 24 Jun 11 04:38:08 PM PDT 24 4420041208 ps
T43 /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.2554568027 Jun 11 04:15:41 PM PDT 24 Jun 11 04:20:45 PM PDT 24 2309278840 ps
T21 /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.502540151 Jun 11 04:16:54 PM PDT 24 Jun 11 04:22:49 PM PDT 24 2909345574 ps
T945 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.372110612 Jun 11 04:01:41 PM PDT 24 Jun 11 04:07:24 PM PDT 24 3274804893 ps
T946 /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.3071291468 Jun 11 04:26:18 PM PDT 24 Jun 11 04:34:39 PM PDT 24 5608628220 ps
T186 /workspace/coverage/default/1.chip_jtag_mem_access.2906052111 Jun 11 04:05:10 PM PDT 24 Jun 11 04:29:13 PM PDT 24 14041713608 ps
T947 /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.2026194978 Jun 11 04:11:28 PM PDT 24 Jun 11 04:16:14 PM PDT 24 2536463928 ps
T716 /workspace/coverage/default/88.chip_sw_all_escalation_resets.934182992 Jun 11 04:33:51 PM PDT 24 Jun 11 04:44:02 PM PDT 24 6064304080 ps
T779 /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.2741384351 Jun 11 04:31:26 PM PDT 24 Jun 11 04:38:03 PM PDT 24 3492186960 ps
T161 /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.828762841 Jun 11 04:00:15 PM PDT 24 Jun 11 04:03:07 PM PDT 24 3707081273 ps
T948 /workspace/coverage/default/0.chip_sw_hmac_oneshot.81880609 Jun 11 04:01:09 PM PDT 24 Jun 11 04:07:39 PM PDT 24 3292580740 ps
T949 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.407765294 Jun 11 04:20:36 PM PDT 24 Jun 11 04:32:25 PM PDT 24 5324419804 ps
T677 /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.2843384677 Jun 11 04:29:33 PM PDT 24 Jun 11 04:34:58 PM PDT 24 3832592658 ps
T355 /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2943766336 Jun 11 04:17:12 PM PDT 24 Jun 11 04:28:49 PM PDT 24 7184644740 ps
T950 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.645046122 Jun 11 04:10:03 PM PDT 24 Jun 11 04:40:20 PM PDT 24 8082428292 ps
T702 /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.95824761 Jun 11 04:27:35 PM PDT 24 Jun 11 04:35:00 PM PDT 24 3851595864 ps
T306 /workspace/coverage/default/2.chip_plic_all_irqs_0.3221270196 Jun 11 04:20:55 PM PDT 24 Jun 11 04:37:37 PM PDT 24 6322712424 ps
T951 /workspace/coverage/default/0.chip_sw_aon_timer_irq.2647812022 Jun 11 04:00:31 PM PDT 24 Jun 11 04:08:24 PM PDT 24 4235395204 ps
T952 /workspace/coverage/default/0.chip_sw_aes_idle.3677217989 Jun 11 04:01:08 PM PDT 24 Jun 11 04:05:07 PM PDT 24 2362776576 ps
T953 /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.359823838 Jun 11 04:02:35 PM PDT 24 Jun 11 04:07:18 PM PDT 24 2797119710 ps
T954 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.1079832234 Jun 11 04:21:21 PM PDT 24 Jun 11 05:16:51 PM PDT 24 14446969806 ps
T955 /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.3418163142 Jun 11 04:19:22 PM PDT 24 Jun 11 04:27:16 PM PDT 24 4915269878 ps
T956 /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.2812364992 Jun 11 04:00:29 PM PDT 24 Jun 11 04:15:48 PM PDT 24 6373927632 ps
T328 /workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.3848164758 Jun 11 04:21:18 PM PDT 24 Jun 11 04:28:30 PM PDT 24 3859997768 ps
T957 /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.2623557713 Jun 11 04:27:19 PM PDT 24 Jun 11 05:15:13 PM PDT 24 12726893440 ps
T958 /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3017259056 Jun 11 04:18:48 PM PDT 24 Jun 11 04:26:07 PM PDT 24 6603579162 ps
T420 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.825398727 Jun 11 04:20:28 PM PDT 24 Jun 11 04:35:19 PM PDT 24 6120533314 ps
T959 /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.3723076754 Jun 11 04:05:44 PM PDT 24 Jun 11 04:09:50 PM PDT 24 3164624008 ps
T146 /workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.3917461054 Jun 11 04:16:59 PM PDT 24 Jun 11 07:05:42 PM PDT 24 58190881480 ps
T285 /workspace/coverage/default/53.chip_sw_all_escalation_resets.4163511877 Jun 11 04:31:57 PM PDT 24 Jun 11 04:40:59 PM PDT 24 5060011216 ps
T960 /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.1807680658 Jun 11 04:11:17 PM PDT 24 Jun 11 04:30:28 PM PDT 24 5731951728 ps
T71 /workspace/coverage/default/0.chip_tap_straps_rma.2837380523 Jun 11 04:03:41 PM PDT 24 Jun 11 04:07:28 PM PDT 24 3764803007 ps
T772 /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.2124436349 Jun 11 04:32:15 PM PDT 24 Jun 11 04:38:43 PM PDT 24 3293798610 ps
T706 /workspace/coverage/default/78.chip_sw_all_escalation_resets.4245338454 Jun 11 04:32:36 PM PDT 24 Jun 11 04:43:59 PM PDT 24 5253746352 ps
T776 /workspace/coverage/default/35.chip_sw_all_escalation_resets.3369591783 Jun 11 04:30:07 PM PDT 24 Jun 11 04:40:32 PM PDT 24 6429099540 ps
T122 /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.322033160 Jun 11 04:13:09 PM PDT 24 Jun 11 04:26:33 PM PDT 24 7398601112 ps
T961 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.973863670 Jun 11 04:04:29 PM PDT 24 Jun 11 04:15:20 PM PDT 24 3934876400 ps
T144 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.354011528 Jun 11 04:13:27 PM PDT 24 Jun 11 05:12:42 PM PDT 24 24959551332 ps
T962 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.960405570 Jun 11 04:16:44 PM PDT 24 Jun 11 04:35:43 PM PDT 24 6121023027 ps
T963 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2193970532 Jun 11 04:01:28 PM PDT 24 Jun 11 04:28:36 PM PDT 24 12082737639 ps
T964 /workspace/coverage/default/2.chip_sw_aes_enc.1081728645 Jun 11 04:19:25 PM PDT 24 Jun 11 04:23:38 PM PDT 24 3558943090 ps
T965 /workspace/coverage/default/2.chip_sw_example_manufacturer.1646911630 Jun 11 04:18:29 PM PDT 24 Jun 11 04:23:27 PM PDT 24 2966172824 ps
T966 /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.3381166943 Jun 11 04:05:27 PM PDT 24 Jun 11 04:12:12 PM PDT 24 2557483696 ps
T11 /workspace/coverage/default/0.chip_sw_sleep_pin_wake.4223627002 Jun 11 04:00:49 PM PDT 24 Jun 11 04:04:36 PM PDT 24 2363303352 ps
T392 /workspace/coverage/default/2.chip_sw_hmac_enc_idle.4063990154 Jun 11 04:23:37 PM PDT 24 Jun 11 04:27:40 PM PDT 24 3400121736 ps
T393 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.2111459047 Jun 11 04:19:35 PM PDT 24 Jun 11 04:54:20 PM PDT 24 11928493128 ps
T394 /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.971309332 Jun 11 04:00:43 PM PDT 24 Jun 11 04:08:19 PM PDT 24 3378494680 ps
T395 /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.2013667250 Jun 11 04:22:39 PM PDT 24 Jun 11 04:43:26 PM PDT 24 4989314810 ps
T168 /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.1020943119 Jun 11 04:23:02 PM PDT 24 Jun 11 04:27:12 PM PDT 24 3015706307 ps
T396 /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.405995620 Jun 11 04:17:36 PM PDT 24 Jun 11 05:44:37 PM PDT 24 44781630075 ps
T397 /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.171691329 Jun 11 04:27:24 PM PDT 24 Jun 11 04:34:05 PM PDT 24 3785433056 ps
T151 /workspace/coverage/default/1.chip_plic_all_irqs_10.2908598963 Jun 11 04:13:51 PM PDT 24 Jun 11 04:24:42 PM PDT 24 3939099392 ps
T398 /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.1117329917 Jun 11 04:28:33 PM PDT 24 Jun 11 05:20:55 PM PDT 24 12617576776 ps
T737 /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.3696116258 Jun 11 04:31:40 PM PDT 24 Jun 11 04:38:33 PM PDT 24 3406081962 ps
T760 /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.4070928608 Jun 11 04:31:15 PM PDT 24 Jun 11 04:37:48 PM PDT 24 3534467202 ps
T641 /workspace/coverage/default/14.chip_sw_all_escalation_resets.2194760267 Jun 11 04:28:35 PM PDT 24 Jun 11 04:38:12 PM PDT 24 5420058282 ps
T967 /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.2783297802 Jun 11 04:01:47 PM PDT 24 Jun 11 04:10:52 PM PDT 24 4098198190 ps
T968 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.903562878 Jun 11 04:13:28 PM PDT 24 Jun 11 04:16:49 PM PDT 24 2340649531 ps
T723 /workspace/coverage/default/80.chip_sw_all_escalation_resets.1119679815 Jun 11 04:32:46 PM PDT 24 Jun 11 04:45:04 PM PDT 24 5098485528 ps
T969 /workspace/coverage/default/1.chip_sw_aes_entropy.1271325205 Jun 11 04:09:23 PM PDT 24 Jun 11 04:13:12 PM PDT 24 2615526328 ps
T970 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1102566809 Jun 11 04:20:58 PM PDT 24 Jun 11 04:31:10 PM PDT 24 4168458680 ps
T971 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1132113398 Jun 11 04:17:33 PM PDT 24 Jun 11 04:43:13 PM PDT 24 13355648569 ps
T632 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.1078715526 Jun 11 04:10:53 PM PDT 24 Jun 11 04:12:40 PM PDT 24 2619964704 ps
T739 /workspace/coverage/default/75.chip_sw_all_escalation_resets.3656884572 Jun 11 04:33:14 PM PDT 24 Jun 11 04:44:14 PM PDT 24 5629870440 ps
T699 /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.3236553925 Jun 11 04:29:34 PM PDT 24 Jun 11 04:36:18 PM PDT 24 4034582308 ps
T276 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.1660852802 Jun 11 04:25:39 PM PDT 24 Jun 11 04:34:36 PM PDT 24 4804045804 ps
T188 /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.2246996344 Jun 11 04:15:41 PM PDT 24 Jun 11 08:06:05 PM PDT 24 78046329210 ps
T680 /workspace/coverage/default/0.chip_sw_all_escalation_resets.3054017004 Jun 11 03:59:59 PM PDT 24 Jun 11 04:08:39 PM PDT 24 5426041838 ps
T972 /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.3825901339 Jun 11 04:27:18 PM PDT 24 Jun 11 04:34:51 PM PDT 24 4259519360 ps
T973 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.726627788 Jun 11 04:22:17 PM PDT 24 Jun 11 04:26:41 PM PDT 24 3340021671 ps
T761 /workspace/coverage/default/69.chip_sw_all_escalation_resets.4176624222 Jun 11 04:32:52 PM PDT 24 Jun 11 04:43:11 PM PDT 24 6157622564 ps
T120 /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.3073564974 Jun 11 04:21:07 PM PDT 24 Jun 11 04:33:22 PM PDT 24 7215428780 ps
T974 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.1332788421 Jun 11 04:13:03 PM PDT 24 Jun 11 04:20:42 PM PDT 24 3535447640 ps
T975 /workspace/coverage/default/76.chip_sw_all_escalation_resets.1358300085 Jun 11 04:33:41 PM PDT 24 Jun 11 04:45:48 PM PDT 24 5654344356 ps
T750 /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1923686697 Jun 11 04:27:27 PM PDT 24 Jun 11 04:34:30 PM PDT 24 3467067940 ps
T976 /workspace/coverage/default/2.chip_sw_kmac_entropy.1099604548 Jun 11 04:17:57 PM PDT 24 Jun 11 04:22:22 PM PDT 24 2596244332 ps
T977 /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.1266855520 Jun 11 04:29:57 PM PDT 24 Jun 11 05:06:02 PM PDT 24 13605041980 ps
T978 /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.958234366 Jun 11 04:24:21 PM PDT 24 Jun 11 04:28:07 PM PDT 24 2886199888 ps
T979 /workspace/coverage/default/0.chip_sw_usbdev_vbus.3389274593 Jun 11 04:00:30 PM PDT 24 Jun 11 04:05:59 PM PDT 24 3011637780 ps
T980 /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.430072706 Jun 11 04:24:55 PM PDT 24 Jun 11 04:32:42 PM PDT 24 7469070020 ps
T981 /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.2152403401 Jun 11 04:08:41 PM PDT 24 Jun 11 04:19:54 PM PDT 24 5853828380 ps
T982 /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.1713016347 Jun 11 04:19:48 PM PDT 24 Jun 11 05:17:30 PM PDT 24 14114051908 ps
T206 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.4011102784 Jun 11 04:18:45 PM PDT 24 Jun 11 05:26:48 PM PDT 24 20627059063 ps
T754 /workspace/coverage/default/50.chip_sw_all_escalation_resets.2299387039 Jun 11 04:34:29 PM PDT 24 Jun 11 04:42:59 PM PDT 24 6148987692 ps
T762 /workspace/coverage/default/28.chip_sw_all_escalation_resets.3032022540 Jun 11 04:29:06 PM PDT 24 Jun 11 04:37:33 PM PDT 24 3935349368 ps
T410 /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.1365185581 Jun 11 04:03:08 PM PDT 24 Jun 11 04:13:51 PM PDT 24 10112540801 ps
T983 /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.1416236828 Jun 11 04:29:24 PM PDT 24 Jun 11 04:37:16 PM PDT 24 4348664408 ps
T718 /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.3065092110 Jun 11 04:27:49 PM PDT 24 Jun 11 04:35:08 PM PDT 24 3993983096 ps
T984 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.3007693795 Jun 11 04:00:43 PM PDT 24 Jun 11 04:20:00 PM PDT 24 10051284666 ps
T127 /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.4114095986 Jun 11 04:25:22 PM PDT 24 Jun 11 04:34:32 PM PDT 24 3867761480 ps
T421 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.1152807160 Jun 11 04:11:03 PM PDT 24 Jun 11 04:33:23 PM PDT 24 6482525148 ps
T755 /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.3279601678 Jun 11 04:33:37 PM PDT 24 Jun 11 04:40:26 PM PDT 24 3616841642 ps
T333 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.325556648 Jun 11 04:04:23 PM PDT 24 Jun 11 04:15:52 PM PDT 24 4696544590 ps
T249 /workspace/coverage/default/8.chip_sw_all_escalation_resets.2354696544 Jun 11 04:26:55 PM PDT 24 Jun 11 04:37:40 PM PDT 24 5739827680 ps
T307 /workspace/coverage/default/0.chip_plic_all_irqs_0.1798773163 Jun 11 04:02:02 PM PDT 24 Jun 11 04:23:05 PM PDT 24 6655792518 ps
T985 /workspace/coverage/default/0.chip_sw_csrng_kat_test.2791946166 Jun 11 04:02:22 PM PDT 24 Jun 11 04:06:09 PM PDT 24 2778281460 ps
T986 /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.1775717586 Jun 11 04:27:22 PM PDT 24 Jun 11 05:25:38 PM PDT 24 13848744297 ps
T987 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.3355068427 Jun 11 04:21:34 PM PDT 24 Jun 11 04:28:52 PM PDT 24 2957887080 ps
T988 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3272489213 Jun 11 04:14:12 PM PDT 24 Jun 11 04:28:32 PM PDT 24 4889641360 ps
T293 /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.2484342047 Jun 11 04:02:54 PM PDT 24 Jun 11 04:07:19 PM PDT 24 3388531406 ps
T989 /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.3222943069 Jun 11 04:17:00 PM PDT 24 Jun 11 04:48:18 PM PDT 24 9055592840 ps
T990 /workspace/coverage/default/0.chip_sw_kmac_idle.3470393988 Jun 11 04:02:18 PM PDT 24 Jun 11 04:06:57 PM PDT 24 2765033784 ps
T991 /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.3897021091 Jun 11 04:23:32 PM PDT 24 Jun 11 04:27:51 PM PDT 24 3397651066 ps
T302 /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.3586552629 Jun 11 04:01:46 PM PDT 24 Jun 11 04:10:12 PM PDT 24 6482715160 ps
T683 /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.3132729812 Jun 11 04:32:53 PM PDT 24 Jun 11 04:38:53 PM PDT 24 3930913776 ps
T725 /workspace/coverage/default/38.chip_sw_all_escalation_resets.479341309 Jun 11 04:31:58 PM PDT 24 Jun 11 04:40:54 PM PDT 24 4527901704 ps
T992 /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.2554439735 Jun 11 03:58:59 PM PDT 24 Jun 11 04:11:58 PM PDT 24 6328570552 ps
T993 /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.2549312501 Jun 11 04:08:01 PM PDT 24 Jun 11 04:14:37 PM PDT 24 3265317944 ps
T703 /workspace/coverage/default/51.chip_sw_all_escalation_resets.3859214234 Jun 11 04:30:50 PM PDT 24 Jun 11 04:41:41 PM PDT 24 5472967480 ps
T994 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.279619675 Jun 11 04:22:00 PM PDT 24 Jun 11 04:35:49 PM PDT 24 10444823064 ps
T995 /workspace/coverage/default/1.chip_tap_straps_prod.2259290731 Jun 11 04:15:30 PM PDT 24 Jun 11 04:37:55 PM PDT 24 12443556515 ps
T996 /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.1877551762 Jun 11 04:02:17 PM PDT 24 Jun 11 04:10:31 PM PDT 24 5025383308 ps
T193 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.3895457393 Jun 11 04:18:42 PM PDT 24 Jun 11 04:57:51 PM PDT 24 25822333864 ps
T997 /workspace/coverage/default/1.chip_sw_edn_kat.149034638 Jun 11 04:11:39 PM PDT 24 Jun 11 04:22:34 PM PDT 24 3333767000 ps
T998 /workspace/coverage/default/2.chip_sw_edn_kat.3954885852 Jun 11 04:20:49 PM PDT 24 Jun 11 04:31:48 PM PDT 24 2988651650 ps
T740 /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.202387463 Jun 11 04:33:55 PM PDT 24 Jun 11 04:41:32 PM PDT 24 3928281288 ps
T505 /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.2248179864 Jun 11 04:01:19 PM PDT 24 Jun 11 04:25:05 PM PDT 24 8621576740 ps
T999 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.842374066 Jun 11 04:07:20 PM PDT 24 Jun 11 04:18:30 PM PDT 24 4190884388 ps
T629 /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.2325210395 Jun 11 04:03:36 PM PDT 24 Jun 11 04:14:55 PM PDT 24 5402141558 ps
T1000 /workspace/coverage/default/3.chip_tap_straps_rma.628806790 Jun 11 04:24:27 PM PDT 24 Jun 11 04:27:51 PM PDT 24 3278713629 ps
T1001 /workspace/coverage/default/2.rom_e2e_smoke.1834600618 Jun 11 04:27:43 PM PDT 24 Jun 11 05:28:40 PM PDT 24 14732990240 ps
T1002 /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.433281802 Jun 11 04:00:32 PM PDT 24 Jun 11 04:07:42 PM PDT 24 4603449050 ps
T751 /workspace/coverage/default/20.chip_sw_all_escalation_resets.27757293 Jun 11 04:28:21 PM PDT 24 Jun 11 04:43:15 PM PDT 24 4850262640 ps
T8 /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.3437979218 Jun 11 04:21:47 PM PDT 24 Jun 11 04:28:21 PM PDT 24 4000872894 ps
T402 /workspace/coverage/default/1.chip_sw_otbn_randomness.2232448369 Jun 11 04:09:12 PM PDT 24 Jun 11 04:24:53 PM PDT 24 6023403964 ps
T374 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1830056137 Jun 11 04:10:08 PM PDT 24 Jun 11 05:42:49 PM PDT 24 22658836628 ps
T372 /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.2347899469 Jun 11 04:20:56 PM PDT 24 Jun 11 04:32:21 PM PDT 24 7151511566 ps
T403 /workspace/coverage/default/4.chip_sw_uart_tx_rx.2779999275 Jun 11 04:25:41 PM PDT 24 Jun 11 04:39:57 PM PDT 24 4191717280 ps
T404 /workspace/coverage/default/33.chip_sw_all_escalation_resets.406199531 Jun 11 04:28:46 PM PDT 24 Jun 11 04:39:13 PM PDT 24 4789878570 ps
T405 /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.2543856174 Jun 11 04:27:43 PM PDT 24 Jun 11 04:34:22 PM PDT 24 3324709706 ps
T406 /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.339345414 Jun 11 04:30:42 PM PDT 24 Jun 11 04:38:08 PM PDT 24 4305385256 ps
T407 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.3519068957 Jun 11 04:09:59 PM PDT 24 Jun 11 04:17:00 PM PDT 24 4325815640 ps
T408 /workspace/coverage/default/2.chip_tap_straps_dev.2314573879 Jun 11 04:20:52 PM PDT 24 Jun 11 04:34:36 PM PDT 24 7748751888 ps
T414 /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3671529038 Jun 11 04:33:24 PM PDT 24 Jun 11 04:39:52 PM PDT 24 3943433120 ps
T105 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.42653560 Jun 11 04:16:06 PM PDT 24 Jun 11 04:45:36 PM PDT 24 9750466530 ps
T218 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.3614829179 Jun 11 04:00:51 PM PDT 24 Jun 11 05:50:56 PM PDT 24 47483950436 ps
T194 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.3168877102 Jun 11 04:00:41 PM PDT 24 Jun 11 04:08:24 PM PDT 24 4375439132 ps
T415 /workspace/coverage/default/9.chip_sw_all_escalation_resets.2040039149 Jun 11 04:27:37 PM PDT 24 Jun 11 04:37:04 PM PDT 24 4679107752 ps
T23 /workspace/coverage/default/0.chip_sw_spi_device_pass_through.3874960449 Jun 11 04:00:47 PM PDT 24 Jun 11 04:16:08 PM PDT 24 6739333515 ps
T416 /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.681368187 Jun 11 04:23:00 PM PDT 24 Jun 11 04:32:43 PM PDT 24 5898027241 ps
T1003 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.123446699 Jun 11 04:21:39 PM PDT 24 Jun 11 04:27:11 PM PDT 24 2524839484 ps
T748 /workspace/coverage/default/29.chip_sw_all_escalation_resets.1074103957 Jun 11 04:28:22 PM PDT 24 Jun 11 04:37:43 PM PDT 24 4769822192 ps
T744 /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.3634823220 Jun 11 04:31:54 PM PDT 24 Jun 11 04:38:49 PM PDT 24 4314008800 ps
T1004 /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.638749467 Jun 11 04:01:01 PM PDT 24 Jun 11 04:07:22 PM PDT 24 7330373800 ps
T730 /workspace/coverage/default/58.chip_sw_all_escalation_resets.835991907 Jun 11 04:31:30 PM PDT 24 Jun 11 04:42:03 PM PDT 24 6231325076 ps
T1005 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.1003258009 Jun 11 04:11:32 PM PDT 24 Jun 11 04:24:17 PM PDT 24 8280981542 ps
T1006 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.2315263178 Jun 11 04:25:22 PM PDT 24 Jun 11 04:34:10 PM PDT 24 3748748340 ps
T633 /workspace/coverage/default/1.rom_volatile_raw_unlock.9099428 Jun 11 04:16:09 PM PDT 24 Jun 11 04:18:03 PM PDT 24 2027050266 ps
T154 /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.2010063750 Jun 11 04:16:44 PM PDT 24 Jun 11 04:18:34 PM PDT 24 2243160418 ps
T1007 /workspace/coverage/default/0.chip_sw_rv_timer_irq.1452447023 Jun 11 04:02:14 PM PDT 24 Jun 11 04:07:05 PM PDT 24 2512584292 ps
T1008 /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.4272945049 Jun 11 04:12:03 PM PDT 24 Jun 11 04:51:48 PM PDT 24 29217858322 ps
T745 /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.882890145 Jun 11 04:34:37 PM PDT 24 Jun 11 04:41:28 PM PDT 24 4423808900 ps
T741 /workspace/coverage/default/24.chip_sw_all_escalation_resets.2969120971 Jun 11 04:28:38 PM PDT 24 Jun 11 04:37:50 PM PDT 24 4383319574 ps
T47 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2889096586 Jun 11 04:18:26 PM PDT 24 Jun 11 04:25:52 PM PDT 24 6125270260 ps
T195 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.1422891910 Jun 11 04:17:50 PM PDT 24 Jun 11 04:29:33 PM PDT 24 4550850785 ps
T1009 /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.1190277775 Jun 11 04:04:07 PM PDT 24 Jun 11 04:13:16 PM PDT 24 5252845366 ps
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