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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 95.52 93.75 95.49 94.47 97.53 99.64


Total test records in report: 2896
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T726 /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.3055923091 Jun 11 04:28:38 PM PDT 24 Jun 11 04:35:57 PM PDT 24 3830824960 ps
T36 /workspace/coverage/default/2.chip_sw_gpio.2380463297 Jun 11 04:21:07 PM PDT 24 Jun 11 04:31:34 PM PDT 24 4586873284 ps
T323 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.3128939930 Jun 11 03:58:52 PM PDT 24 Jun 11 04:10:32 PM PDT 24 3803010728 ps
T1010 /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.1515273929 Jun 11 04:11:54 PM PDT 24 Jun 11 04:22:25 PM PDT 24 6400260709 ps
T695 /workspace/coverage/default/60.chip_sw_all_escalation_resets.302465254 Jun 11 04:32:33 PM PDT 24 Jun 11 04:43:55 PM PDT 24 5282748344 ps
T48 /workspace/coverage/default/2.chip_sw_spi_device_tpm.2217997808 Jun 11 04:16:56 PM PDT 24 Jun 11 04:24:10 PM PDT 24 3947258167 ps
T712 /workspace/coverage/default/97.chip_sw_all_escalation_resets.4101108586 Jun 11 04:33:59 PM PDT 24 Jun 11 04:43:12 PM PDT 24 5987933360 ps
T686 /workspace/coverage/default/7.chip_sw_all_escalation_resets.1574291702 Jun 11 04:26:49 PM PDT 24 Jun 11 04:37:35 PM PDT 24 5196161598 ps
T1011 /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.1715281258 Jun 11 04:25:52 PM PDT 24 Jun 11 04:31:40 PM PDT 24 5328687272 ps
T1012 /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.657371689 Jun 11 04:00:38 PM PDT 24 Jun 11 04:31:10 PM PDT 24 10852820568 ps
T1013 /workspace/coverage/default/2.chip_tap_straps_testunlock0.2964910563 Jun 11 04:20:57 PM PDT 24 Jun 11 04:23:19 PM PDT 24 2570155071 ps
T1014 /workspace/coverage/default/0.chip_sw_edn_kat.3794947542 Jun 11 04:02:39 PM PDT 24 Jun 11 04:13:54 PM PDT 24 3113132238 ps
T1015 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.1535696228 Jun 11 04:10:14 PM PDT 24 Jun 11 05:02:51 PM PDT 24 13403267593 ps
T13 /workspace/coverage/default/1.chip_sw_sleep_pin_retention.1522115727 Jun 11 04:06:07 PM PDT 24 Jun 11 04:10:31 PM PDT 24 3525539352 ps
T1016 /workspace/coverage/default/0.chip_sw_otbn_randomness.1551513645 Jun 11 04:01:53 PM PDT 24 Jun 11 04:17:27 PM PDT 24 6395010920 ps
T687 /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.3741632346 Jun 11 04:31:26 PM PDT 24 Jun 11 04:37:00 PM PDT 24 3927021632 ps
T294 /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.2436534474 Jun 11 04:15:20 PM PDT 24 Jun 11 04:19:15 PM PDT 24 2711892593 ps
T24 /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.3732083176 Jun 11 04:01:13 PM PDT 24 Jun 11 04:10:18 PM PDT 24 3837878230 ps
T145 /workspace/coverage/default/1.chip_sw_otbn_smoketest.2660150666 Jun 11 04:15:45 PM PDT 24 Jun 11 04:31:47 PM PDT 24 5587894836 ps
T1017 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1114790302 Jun 11 04:04:09 PM PDT 24 Jun 11 05:18:49 PM PDT 24 25083967909 ps
T727 /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.2688346360 Jun 11 04:33:17 PM PDT 24 Jun 11 04:40:01 PM PDT 24 4426953624 ps
T215 /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.3205643746 Jun 11 04:20:49 PM PDT 24 Jun 11 05:07:51 PM PDT 24 13863038468 ps
T1018 /workspace/coverage/default/1.chip_sw_hmac_multistream.168177107 Jun 11 04:11:12 PM PDT 24 Jun 11 04:32:24 PM PDT 24 6981913190 ps
T634 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2015697998 Jun 11 04:16:52 PM PDT 24 Jun 11 04:18:39 PM PDT 24 2457240509 ps
T250 /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.2086200362 Jun 11 04:07:51 PM PDT 24 Jun 11 04:18:33 PM PDT 24 4799403576 ps
T1019 /workspace/coverage/default/4.chip_tap_straps_testunlock0.3118056920 Jun 11 04:25:17 PM PDT 24 Jun 11 04:29:26 PM PDT 24 3282441218 ps
T710 /workspace/coverage/default/25.chip_sw_all_escalation_resets.97058127 Jun 11 04:28:39 PM PDT 24 Jun 11 04:37:30 PM PDT 24 4925805684 ps
T330 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.4265049167 Jun 11 04:18:25 PM PDT 24 Jun 11 04:29:41 PM PDT 24 3937179065 ps
T124 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1599784200 Jun 11 04:11:24 PM PDT 24 Jun 11 04:17:44 PM PDT 24 5347445048 ps
T1020 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.592085220 Jun 11 04:10:41 PM PDT 24 Jun 11 04:48:09 PM PDT 24 10722313508 ps
T1021 /workspace/coverage/default/1.chip_sw_uart_smoketest.132291220 Jun 11 04:14:46 PM PDT 24 Jun 11 04:19:53 PM PDT 24 3090075100 ps
T1022 /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.216166631 Jun 11 04:17:58 PM PDT 24 Jun 11 04:24:47 PM PDT 24 10407131090 ps
T1023 /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.517524117 Jun 11 04:07:11 PM PDT 24 Jun 11 04:11:48 PM PDT 24 2979540408 ps
T1024 /workspace/coverage/default/2.chip_sw_kmac_smoketest.2713696834 Jun 11 04:23:57 PM PDT 24 Jun 11 04:28:31 PM PDT 24 3637912054 ps
T1025 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.659187440 Jun 11 04:11:07 PM PDT 24 Jun 11 05:45:24 PM PDT 24 22730428317 ps
T422 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.3616024086 Jun 11 04:01:38 PM PDT 24 Jun 11 04:18:27 PM PDT 24 6266549336 ps
T746 /workspace/coverage/default/17.chip_sw_all_escalation_resets.1265334408 Jun 11 04:27:55 PM PDT 24 Jun 11 04:37:50 PM PDT 24 5498472536 ps
T237 /workspace/coverage/default/2.chip_sw_power_sleep_load.2074701317 Jun 11 04:23:08 PM PDT 24 Jun 11 04:29:50 PM PDT 24 4344497150 ps
T1026 /workspace/coverage/default/1.chip_sw_kmac_idle.1349233457 Jun 11 04:15:04 PM PDT 24 Jun 11 04:21:14 PM PDT 24 2512231280 ps
T1027 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.687278777 Jun 11 04:18:14 PM PDT 24 Jun 11 05:14:46 PM PDT 24 44020705365 ps
T719 /workspace/coverage/default/67.chip_sw_all_escalation_resets.525612349 Jun 11 04:33:58 PM PDT 24 Jun 11 04:44:21 PM PDT 24 5823583544 ps
T1028 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.1338810578 Jun 11 04:00:34 PM PDT 24 Jun 11 04:22:03 PM PDT 24 6275925952 ps
T1029 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.4223768512 Jun 11 04:20:16 PM PDT 24 Jun 11 05:09:42 PM PDT 24 17432362078 ps
T1030 /workspace/coverage/default/2.chip_sw_csrng_kat_test.2065205501 Jun 11 04:20:17 PM PDT 24 Jun 11 04:23:53 PM PDT 24 2396730760 ps
T1031 /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.302332853 Jun 11 04:27:00 PM PDT 24 Jun 11 04:40:23 PM PDT 24 12228027112 ps
T1032 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.1501217019 Jun 11 04:18:12 PM PDT 24 Jun 11 05:16:36 PM PDT 24 14070880488 ps
T187 /workspace/coverage/default/0.chip_jtag_mem_access.2058970515 Jun 11 03:55:02 PM PDT 24 Jun 11 04:19:54 PM PDT 24 14351692632 ps
T219 /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.2381699164 Jun 11 04:17:19 PM PDT 24 Jun 11 05:56:00 PM PDT 24 49643384080 ps
T162 /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.4069069124 Jun 11 04:07:29 PM PDT 24 Jun 11 04:12:03 PM PDT 24 3769358829 ps
T1033 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.465902074 Jun 11 04:13:55 PM PDT 24 Jun 11 04:20:29 PM PDT 24 6855352976 ps
T1034 /workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.1496448509 Jun 11 04:01:29 PM PDT 24 Jun 11 05:33:04 PM PDT 24 27866118646 ps
T423 /workspace/coverage/default/0.chip_sw_edn_boot_mode.1049201136 Jun 11 04:03:43 PM PDT 24 Jun 11 04:14:45 PM PDT 24 2783265688 ps
T733 /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.1764989881 Jun 11 04:27:59 PM PDT 24 Jun 11 04:33:07 PM PDT 24 3782255738 ps
T350 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.3279668087 Jun 11 04:01:20 PM PDT 24 Jun 11 04:11:40 PM PDT 24 4174391368 ps
T1035 /workspace/coverage/default/3.chip_tap_straps_dev.3621364104 Jun 11 04:27:09 PM PDT 24 Jun 11 04:30:45 PM PDT 24 3675233124 ps
T1036 /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.3100677050 Jun 11 04:01:48 PM PDT 24 Jun 11 04:11:27 PM PDT 24 5609917942 ps
T1037 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.1985290206 Jun 11 04:18:45 PM PDT 24 Jun 11 04:24:25 PM PDT 24 3230766903 ps
T649 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.2813370152 Jun 11 04:18:11 PM PDT 24 Jun 11 04:22:26 PM PDT 24 2612987280 ps
T1038 /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.4260379517 Jun 11 04:01:37 PM PDT 24 Jun 11 04:07:59 PM PDT 24 4403588000 ps
T1039 /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.530115006 Jun 11 04:26:12 PM PDT 24 Jun 11 04:30:37 PM PDT 24 2697855542 ps
T169 /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.67885958 Jun 11 04:07:01 PM PDT 24 Jun 11 05:37:19 PM PDT 24 44550845720 ps
T68 /workspace/coverage/default/2.chip_tap_straps_rma.3644970897 Jun 11 04:21:22 PM PDT 24 Jun 11 04:37:36 PM PDT 24 9068199797 ps
T1040 /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.804785678 Jun 11 04:30:07 PM PDT 24 Jun 11 04:52:56 PM PDT 24 8262306672 ps
T1041 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.1341010000 Jun 11 04:08:48 PM PDT 24 Jun 11 04:19:33 PM PDT 24 6228131888 ps
T1042 /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.345818239 Jun 11 04:01:46 PM PDT 24 Jun 11 04:20:27 PM PDT 24 5767638982 ps
T1043 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2118193228 Jun 11 04:25:24 PM PDT 24 Jun 11 04:34:42 PM PDT 24 4736315549 ps
T1044 /workspace/coverage/default/1.chip_sw_aes_smoketest.1649203083 Jun 11 04:15:04 PM PDT 24 Jun 11 04:19:58 PM PDT 24 2999254560 ps
T1045 /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.3090154056 Jun 11 04:13:52 PM PDT 24 Jun 11 04:23:45 PM PDT 24 4082968614 ps
T1046 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.2215195183 Jun 11 04:01:39 PM PDT 24 Jun 11 05:06:55 PM PDT 24 20479089351 ps
T635 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.297882830 Jun 11 04:19:44 PM PDT 24 Jun 11 04:21:50 PM PDT 24 2486008714 ps
T86 /workspace/coverage/default/90.chip_sw_all_escalation_resets.2046112133 Jun 11 04:33:31 PM PDT 24 Jun 11 04:42:30 PM PDT 24 6071564120 ps
T286 /workspace/coverage/default/22.chip_sw_all_escalation_resets.4099612778 Jun 11 04:30:32 PM PDT 24 Jun 11 04:46:52 PM PDT 24 6001334512 ps
T1047 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.3006595838 Jun 11 04:02:35 PM PDT 24 Jun 11 04:14:03 PM PDT 24 8792261916 ps
T1048 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.2523192922 Jun 11 04:07:57 PM PDT 24 Jun 11 04:18:35 PM PDT 24 4192674486 ps
T1049 /workspace/coverage/default/2.chip_sw_aes_idle.432392211 Jun 11 04:21:42 PM PDT 24 Jun 11 04:26:58 PM PDT 24 3031958832 ps
T424 /workspace/coverage/default/2.chip_sw_edn_boot_mode.3262439934 Jun 11 04:20:49 PM PDT 24 Jun 11 04:29:24 PM PDT 24 2840199064 ps
T1050 /workspace/coverage/default/1.chip_sw_aes_masking_off.141978417 Jun 11 04:07:51 PM PDT 24 Jun 11 04:11:12 PM PDT 24 2654366515 ps
T128 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.476596931 Jun 11 04:21:51 PM PDT 24 Jun 11 04:30:08 PM PDT 24 5060179802 ps
T277 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.2441553366 Jun 11 04:20:57 PM PDT 24 Jun 11 04:30:46 PM PDT 24 4227994042 ps
T170 /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.611551206 Jun 11 03:58:36 PM PDT 24 Jun 11 05:29:23 PM PDT 24 43138270249 ps
T1051 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.3063862302 Jun 11 04:24:51 PM PDT 24 Jun 11 04:36:14 PM PDT 24 4854629910 ps
T1052 /workspace/coverage/default/1.chip_sw_alert_handler_escalation.1070833103 Jun 11 04:13:16 PM PDT 24 Jun 11 04:21:33 PM PDT 24 4002838748 ps
T773 /workspace/coverage/default/82.chip_sw_all_escalation_resets.2460096381 Jun 11 04:36:51 PM PDT 24 Jun 11 04:46:10 PM PDT 24 4775260844 ps
T1053 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.855852222 Jun 11 04:01:58 PM PDT 24 Jun 11 05:09:45 PM PDT 24 16455567838 ps
T1054 /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.3205480222 Jun 11 04:09:19 PM PDT 24 Jun 11 04:21:16 PM PDT 24 8298663480 ps
T734 /workspace/coverage/default/84.chip_sw_all_escalation_resets.840751994 Jun 11 04:33:45 PM PDT 24 Jun 11 04:42:50 PM PDT 24 5312349852 ps
T738 /workspace/coverage/default/59.chip_sw_all_escalation_resets.3391817831 Jun 11 04:33:35 PM PDT 24 Jun 11 04:45:47 PM PDT 24 4948627904 ps
T1055 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.3108375857 Jun 11 04:28:04 PM PDT 24 Jun 11 05:17:16 PM PDT 24 14432482240 ps
T1056 /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.1034774175 Jun 11 04:05:38 PM PDT 24 Jun 11 04:10:31 PM PDT 24 3069452184 ps
T278 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.1823429919 Jun 11 04:11:49 PM PDT 24 Jun 11 04:20:40 PM PDT 24 4063369904 ps
T1057 /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.3193429645 Jun 11 04:20:58 PM PDT 24 Jun 11 04:24:00 PM PDT 24 2498496640 ps
T1058 /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.2050387368 Jun 11 04:18:22 PM PDT 24 Jun 11 04:23:27 PM PDT 24 3186230328 ps
T1059 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.2467939354 Jun 11 04:16:43 PM PDT 24 Jun 11 04:29:31 PM PDT 24 8947586149 ps
T684 /workspace/coverage/default/66.chip_sw_all_escalation_resets.4134016539 Jun 11 04:31:57 PM PDT 24 Jun 11 04:42:39 PM PDT 24 5607050148 ps
T1060 /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.3665267132 Jun 11 04:27:07 PM PDT 24 Jun 11 04:30:26 PM PDT 24 2720800698 ps
T1061 /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.689173259 Jun 11 04:23:01 PM PDT 24 Jun 11 04:27:39 PM PDT 24 2881410120 ps
T758 /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.4121208526 Jun 11 04:32:29 PM PDT 24 Jun 11 04:40:22 PM PDT 24 3524059480 ps
T1062 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2138093206 Jun 11 04:09:09 PM PDT 24 Jun 11 04:29:26 PM PDT 24 14345354106 ps
T756 /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.368360708 Jun 11 04:32:18 PM PDT 24 Jun 11 04:37:40 PM PDT 24 4119010904 ps
T735 /workspace/coverage/default/74.chip_sw_all_escalation_resets.1205264741 Jun 11 04:34:41 PM PDT 24 Jun 11 04:44:36 PM PDT 24 5478479398 ps
T1063 /workspace/coverage/default/0.chip_sw_kmac_smoketest.2861710713 Jun 11 04:07:03 PM PDT 24 Jun 11 04:12:38 PM PDT 24 3121401820 ps
T765 /workspace/coverage/default/40.chip_sw_all_escalation_resets.2695336706 Jun 11 04:32:37 PM PDT 24 Jun 11 04:43:34 PM PDT 24 5420535962 ps
T1064 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.1036692768 Jun 11 04:04:38 PM PDT 24 Jun 11 04:41:44 PM PDT 24 8500379414 ps
T1065 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.282755828 Jun 11 04:18:14 PM PDT 24 Jun 11 04:27:00 PM PDT 24 4548945464 ps
T1066 /workspace/coverage/default/1.rom_e2e_smoke.1411937943 Jun 11 04:20:33 PM PDT 24 Jun 11 05:12:55 PM PDT 24 14401211784 ps
T1067 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.3832896234 Jun 11 04:17:26 PM PDT 24 Jun 11 04:37:27 PM PDT 24 6993370736 ps
T1068 /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.4256122411 Jun 11 04:12:06 PM PDT 24 Jun 11 04:21:52 PM PDT 24 5260247674 ps
T189 /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.2981111221 Jun 11 04:09:19 PM PDT 24 Jun 11 07:46:11 PM PDT 24 77955886786 ps
T1069 /workspace/coverage/default/2.chip_sw_ast_clk_outputs.1667478368 Jun 11 04:21:15 PM PDT 24 Jun 11 04:40:18 PM PDT 24 7598607410 ps
T1070 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.797145845 Jun 11 04:10:38 PM PDT 24 Jun 11 04:32:30 PM PDT 24 6351981012 ps
T1071 /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.3779166356 Jun 11 04:27:12 PM PDT 24 Jun 11 04:34:50 PM PDT 24 7253227362 ps
T1072 /workspace/coverage/default/1.chip_sw_edn_sw_mode.1265136902 Jun 11 04:11:11 PM PDT 24 Jun 11 04:51:32 PM PDT 24 10906684554 ps
T1073 /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.2464803614 Jun 11 04:19:45 PM PDT 24 Jun 11 05:22:18 PM PDT 24 15044294081 ps
T1074 /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.3926149334 Jun 11 04:09:12 PM PDT 24 Jun 11 04:51:56 PM PDT 24 10558412671 ps
T636 /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.4001518971 Jun 11 04:18:37 PM PDT 24 Jun 11 04:20:44 PM PDT 24 3633082416 ps
T1075 /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.2917053161 Jun 11 04:20:13 PM PDT 24 Jun 11 04:45:40 PM PDT 24 10401116600 ps
T222 /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.316021169 Jun 11 04:18:06 PM PDT 24 Jun 11 05:42:05 PM PDT 24 48809711672 ps
T1076 /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.2781984067 Jun 11 04:00:54 PM PDT 24 Jun 11 04:06:25 PM PDT 24 3604874732 ps
T736 /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2745409523 Jun 11 04:27:17 PM PDT 24 Jun 11 04:34:46 PM PDT 24 3750674560 ps
T1077 /workspace/coverage/default/0.rom_e2e_asm_init_rma.2685804463 Jun 11 04:09:37 PM PDT 24 Jun 11 05:03:48 PM PDT 24 14544099799 ps
T1078 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.394606188 Jun 11 04:00:22 PM PDT 24 Jun 11 04:31:23 PM PDT 24 7827906218 ps
T310 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.683384184 Jun 11 04:17:38 PM PDT 24 Jun 11 04:30:05 PM PDT 24 4261881190 ps
T1079 /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.275712782 Jun 11 04:09:03 PM PDT 24 Jun 11 07:52:36 PM PDT 24 254699166586 ps
T1080 /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.1044399337 Jun 11 04:17:26 PM PDT 24 Jun 11 04:42:30 PM PDT 24 8697483240 ps
T1081 /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.24175880 Jun 11 04:17:20 PM PDT 24 Jun 11 04:26:09 PM PDT 24 4060877400 ps
T334 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.3232950577 Jun 11 04:23:51 PM PDT 24 Jun 11 04:35:41 PM PDT 24 4284748262 ps
T125 /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.1146684785 Jun 11 04:03:21 PM PDT 24 Jun 11 04:18:27 PM PDT 24 9056946426 ps
T95 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1544677207 Jun 11 04:05:52 PM PDT 24 Jun 11 04:13:52 PM PDT 24 7727833758 ps
T1082 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.1324022176 Jun 11 04:10:39 PM PDT 24 Jun 11 04:53:14 PM PDT 24 11515681450 ps
T1083 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.1029818254 Jun 11 04:00:34 PM PDT 24 Jun 11 04:56:12 PM PDT 24 17684740760 ps
T1084 /workspace/coverage/default/1.chip_sw_kmac_app_rom.280538241 Jun 11 04:12:21 PM PDT 24 Jun 11 04:16:49 PM PDT 24 2547476072 ps
T1085 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.1493523998 Jun 11 04:02:08 PM PDT 24 Jun 11 04:42:56 PM PDT 24 11825640881 ps
T1086 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.3947050591 Jun 11 04:08:18 PM PDT 24 Jun 11 05:04:35 PM PDT 24 13920733084 ps
T1087 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.1326261985 Jun 11 04:09:47 PM PDT 24 Jun 11 04:29:43 PM PDT 24 5933871628 ps
T216 /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.1011074621 Jun 11 04:10:45 PM PDT 24 Jun 11 05:02:12 PM PDT 24 11625475040 ps
T1088 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3800775329 Jun 11 04:20:35 PM PDT 24 Jun 11 04:33:47 PM PDT 24 4362041898 ps
T717 /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.3822564109 Jun 11 04:33:07 PM PDT 24 Jun 11 04:38:36 PM PDT 24 4079651110 ps
T679 /workspace/coverage/default/72.chip_sw_all_escalation_resets.535754386 Jun 11 04:33:03 PM PDT 24 Jun 11 04:43:42 PM PDT 24 4916576456 ps
T223 /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.353496048 Jun 11 04:17:21 PM PDT 24 Jun 11 04:27:23 PM PDT 24 5210590531 ps
T1089 /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.2610476839 Jun 11 04:22:01 PM PDT 24 Jun 11 04:29:27 PM PDT 24 5116626725 ps
T1090 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.3184474699 Jun 11 04:12:29 PM PDT 24 Jun 11 05:07:13 PM PDT 24 14507550968 ps
T224 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.1296758045 Jun 11 04:17:49 PM PDT 24 Jun 11 05:41:14 PM PDT 24 48043615820 ps
T688 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.2616141732 Jun 11 04:04:08 PM PDT 24 Jun 11 04:10:51 PM PDT 24 4172448806 ps
T314 /workspace/coverage/default/1.chip_sw_entropy_src_csrng.3101066601 Jun 11 04:11:45 PM PDT 24 Jun 11 04:30:38 PM PDT 24 5585305770 ps
T1091 /workspace/coverage/default/0.chip_sw_kmac_app_rom.433501288 Jun 11 04:02:02 PM PDT 24 Jun 11 04:05:09 PM PDT 24 2245972640 ps
T1092 /workspace/coverage/default/2.rom_keymgr_functest.407413717 Jun 11 04:22:58 PM PDT 24 Jun 11 04:34:26 PM PDT 24 3777511344 ps
T1093 /workspace/coverage/default/1.chip_sw_ast_clk_outputs.4233471016 Jun 11 04:12:38 PM PDT 24 Jun 11 04:28:40 PM PDT 24 7801693608 ps
T1094 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.204835262 Jun 11 04:02:25 PM PDT 24 Jun 11 04:09:50 PM PDT 24 5396568445 ps
T1095 /workspace/coverage/default/0.chip_sw_usbdev_setuprx.3878091564 Jun 11 03:59:57 PM PDT 24 Jun 11 04:09:55 PM PDT 24 4348740392 ps
T325 /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.2492208352 Jun 11 04:16:54 PM PDT 24 Jun 11 04:29:00 PM PDT 24 4221434372 ps
T728 /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.34307874 Jun 11 04:32:14 PM PDT 24 Jun 11 04:40:26 PM PDT 24 4013425262 ps
T311 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.3547624322 Jun 11 04:06:53 PM PDT 24 Jun 11 04:20:00 PM PDT 24 5416207856 ps
T1096 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.2099929224 Jun 11 04:13:34 PM PDT 24 Jun 11 05:08:51 PM PDT 24 13939919276 ps
T356 /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.765475747 Jun 11 04:06:01 PM PDT 24 Jun 11 04:12:24 PM PDT 24 5549572300 ps
T1097 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.1310256207 Jun 11 04:29:28 PM PDT 24 Jun 11 05:44:34 PM PDT 24 14535415628 ps
T1098 /workspace/coverage/default/0.chip_sw_aes_enc.3612101451 Jun 11 04:00:52 PM PDT 24 Jun 11 04:05:51 PM PDT 24 3619294400 ps
T1099 /workspace/coverage/default/1.chip_sw_hmac_enc.2690881689 Jun 11 04:14:27 PM PDT 24 Jun 11 04:19:22 PM PDT 24 3144707296 ps
T358 /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.760181515 Jun 11 04:30:50 PM PDT 24 Jun 11 04:37:14 PM PDT 24 3234535388 ps
T1100 /workspace/coverage/default/2.chip_sw_gpio_smoketest.3486994129 Jun 11 04:23:27 PM PDT 24 Jun 11 04:28:58 PM PDT 24 2593310780 ps
T1101 /workspace/coverage/default/1.chip_sw_hmac_smoketest.1367846964 Jun 11 04:16:03 PM PDT 24 Jun 11 04:22:54 PM PDT 24 3238320394 ps
T1102 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.1821770733 Jun 11 04:12:28 PM PDT 24 Jun 11 05:11:43 PM PDT 24 10564070000 ps
T1103 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.1579578863 Jun 11 04:00:50 PM PDT 24 Jun 11 04:09:38 PM PDT 24 5577170925 ps
T1104 /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.3679184328 Jun 11 04:28:39 PM PDT 24 Jun 11 04:35:18 PM PDT 24 7628972308 ps
T1105 /workspace/coverage/default/0.chip_sw_edn_auto_mode.717405572 Jun 11 04:03:13 PM PDT 24 Jun 11 04:33:29 PM PDT 24 5641786460 ps
T196 /workspace/coverage/default/2.chip_sw_inject_scramble_seed.1530498974 Jun 11 04:16:46 PM PDT 24 Jun 11 07:36:00 PM PDT 24 65384249110 ps
T1106 /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.1301188985 Jun 11 04:21:10 PM PDT 24 Jun 11 05:10:45 PM PDT 24 32502513228 ps
T1107 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3877090191 Jun 11 04:17:36 PM PDT 24 Jun 11 04:38:27 PM PDT 24 7123766540 ps
T731 /workspace/coverage/default/47.chip_sw_all_escalation_resets.4205026526 Jun 11 04:31:24 PM PDT 24 Jun 11 04:46:23 PM PDT 24 5017950000 ps
T1108 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.1269834502 Jun 11 04:10:19 PM PDT 24 Jun 11 05:21:22 PM PDT 24 14872530750 ps
T1109 /workspace/coverage/default/0.chip_sw_hmac_smoketest.2764387188 Jun 11 04:06:43 PM PDT 24 Jun 11 04:12:32 PM PDT 24 3457943160 ps
T1110 /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.777981736 Jun 11 04:35:36 PM PDT 24 Jun 11 04:42:03 PM PDT 24 4141968174 ps
T630 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.1064290554 Jun 11 04:15:21 PM PDT 24 Jun 11 04:26:48 PM PDT 24 4772708499 ps
T155 /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.563987199 Jun 11 03:59:30 PM PDT 24 Jun 11 04:03:35 PM PDT 24 3511514374 ps
T263 /workspace/coverage/default/1.chip_sw_data_integrity_escalation.1390969080 Jun 11 04:05:51 PM PDT 24 Jun 11 04:18:28 PM PDT 24 4907120124 ps
T14 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.2191091651 Jun 11 04:04:25 PM PDT 24 Jun 11 04:33:08 PM PDT 24 22296339592 ps
T1111 /workspace/coverage/default/0.rom_e2e_jtag_inject_dev.2973277676 Jun 11 04:06:23 PM PDT 24 Jun 11 04:54:57 PM PDT 24 44980743327 ps
T352 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.69506749 Jun 11 04:11:00 PM PDT 24 Jun 11 04:17:23 PM PDT 24 3160034284 ps
T713 /workspace/coverage/default/48.chip_sw_all_escalation_resets.3101092190 Jun 11 04:30:11 PM PDT 24 Jun 11 04:38:55 PM PDT 24 5243078552 ps
T375 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.160340549 Jun 11 04:11:13 PM PDT 24 Jun 11 05:39:36 PM PDT 24 22387268300 ps
T650 /workspace/coverage/default/0.chip_sw_plic_sw_irq.2719774120 Jun 11 04:01:08 PM PDT 24 Jun 11 04:05:08 PM PDT 24 2832139044 ps
T1112 /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.2228983303 Jun 11 04:03:06 PM PDT 24 Jun 11 04:10:40 PM PDT 24 3561437478 ps
T742 /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.1189503749 Jun 11 04:31:32 PM PDT 24 Jun 11 04:38:28 PM PDT 24 3975222732 ps
T264 /workspace/coverage/default/0.chip_sw_data_integrity_escalation.4136014551 Jun 11 03:58:26 PM PDT 24 Jun 11 04:12:25 PM PDT 24 6359934276 ps
T705 /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.1418911950 Jun 11 04:31:01 PM PDT 24 Jun 11 04:36:38 PM PDT 24 4147515048 ps
T1113 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.1273113510 Jun 11 04:00:40 PM PDT 24 Jun 11 04:19:56 PM PDT 24 6722946642 ps
T1114 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2478595405 Jun 11 04:16:23 PM PDT 24 Jun 11 04:34:01 PM PDT 24 8794147731 ps
T1115 /workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.1618218106 Jun 11 04:00:09 PM PDT 24 Jun 11 04:27:30 PM PDT 24 8315121640 ps
T1116 /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.456886205 Jun 11 03:59:12 PM PDT 24 Jun 11 04:01:33 PM PDT 24 3470384587 ps
T1117 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.3443934066 Jun 11 04:06:46 PM PDT 24 Jun 11 04:10:47 PM PDT 24 2816931523 ps
T1118 /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.326628747 Jun 11 04:25:22 PM PDT 24 Jun 11 04:33:31 PM PDT 24 3262335072 ps
T217 /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.4108391809 Jun 11 04:10:01 PM PDT 24 Jun 11 05:35:15 PM PDT 24 47720165462 ps
T159 /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.1463291943 Jun 11 03:59:47 PM PDT 24 Jun 11 04:10:05 PM PDT 24 6414661600 ps
T1119 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.4074016222 Jun 11 04:22:25 PM PDT 24 Jun 11 04:27:27 PM PDT 24 3189653364 ps
T1120 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.4207153823 Jun 11 04:08:09 PM PDT 24 Jun 11 04:13:20 PM PDT 24 3515057312 ps
T382 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3473533349 Jun 11 04:14:29 PM PDT 24 Jun 11 04:37:14 PM PDT 24 22203761406 ps
T722 /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.183380378 Jun 11 04:26:47 PM PDT 24 Jun 11 04:32:32 PM PDT 24 3091269588 ps
T1121 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.2671093730 Jun 11 04:10:47 PM PDT 24 Jun 11 04:25:15 PM PDT 24 8789276040 ps
T1122 /workspace/coverage/default/3.chip_sw_uart_tx_rx.1301544078 Jun 11 04:27:18 PM PDT 24 Jun 11 04:35:58 PM PDT 24 4017168050 ps
T308 /workspace/coverage/default/1.chip_plic_all_irqs_0.3388857338 Jun 11 04:14:01 PM PDT 24 Jun 11 04:36:48 PM PDT 24 6330524432 ps
T1123 /workspace/coverage/default/4.chip_tap_straps_dev.1454994248 Jun 11 04:23:49 PM PDT 24 Jun 11 04:26:33 PM PDT 24 2780592907 ps
T1124 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.1920376563 Jun 11 04:00:11 PM PDT 24 Jun 11 04:02:18 PM PDT 24 2755663359 ps
T411 /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.803485287 Jun 11 04:24:55 PM PDT 24 Jun 11 04:31:53 PM PDT 24 3608673552 ps
T1125 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.1406080192 Jun 11 04:02:19 PM PDT 24 Jun 11 04:36:07 PM PDT 24 8343579128 ps
T1126 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4035596340 Jun 11 04:24:40 PM PDT 24 Jun 11 04:32:36 PM PDT 24 3528720063 ps
T37 /workspace/coverage/default/0.chip_sw_gpio.3414968326 Jun 11 04:00:21 PM PDT 24 Jun 11 04:06:13 PM PDT 24 3939088550 ps
T1127 /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.429402534 Jun 11 04:03:57 PM PDT 24 Jun 11 04:11:15 PM PDT 24 5261641540 ps
T1128 /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.1143144734 Jun 11 04:28:17 PM PDT 24 Jun 11 04:51:32 PM PDT 24 8621343892 ps
T1129 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3445593223 Jun 11 04:21:14 PM PDT 24 Jun 11 04:32:43 PM PDT 24 4696050198 ps
T1130 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2034100440 Jun 11 04:22:18 PM PDT 24 Jun 11 04:41:26 PM PDT 24 7252446760 ps
T1131 /workspace/coverage/default/0.chip_sw_usbdev_stream.3592303545 Jun 11 03:58:22 PM PDT 24 Jun 11 05:07:54 PM PDT 24 18757752864 ps
T1132 /workspace/coverage/default/2.chip_sw_example_rom.105116410 Jun 11 04:14:24 PM PDT 24 Jun 11 04:16:29 PM PDT 24 2511361122 ps
T1133 /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.2768550218 Jun 11 04:00:21 PM PDT 24 Jun 11 04:02:32 PM PDT 24 2453324474 ps
T1134 /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.1216355492 Jun 11 04:03:24 PM PDT 24 Jun 11 04:06:25 PM PDT 24 2771794566 ps
T1135 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.1111890668 Jun 11 04:02:30 PM PDT 24 Jun 11 04:16:41 PM PDT 24 6661846330 ps
T709 /workspace/coverage/default/27.chip_sw_all_escalation_resets.3292382398 Jun 11 04:28:50 PM PDT 24 Jun 11 04:37:32 PM PDT 24 6050546720 ps
T696 /workspace/coverage/default/42.chip_sw_all_escalation_resets.1745103619 Jun 11 04:30:55 PM PDT 24 Jun 11 04:40:58 PM PDT 24 5412388296 ps
T1136 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3762393228 Jun 11 04:12:15 PM PDT 24 Jun 11 04:23:06 PM PDT 24 4424359224 ps
T243 /workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.452891073 Jun 11 04:05:04 PM PDT 24 Jun 11 04:45:11 PM PDT 24 14503333131 ps
T156 /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.2938611975 Jun 11 04:07:22 PM PDT 24 Jun 11 04:10:18 PM PDT 24 2642749389 ps
T383 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2599330266 Jun 11 04:21:21 PM PDT 24 Jun 11 04:29:02 PM PDT 24 7743371784 ps
T1137 /workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.4040441815 Jun 11 04:08:52 PM PDT 24 Jun 11 04:13:50 PM PDT 24 2733085742 ps
T1138 /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.1146565108 Jun 11 04:16:52 PM PDT 24 Jun 11 04:25:22 PM PDT 24 5495182300 ps
T1139 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.1876207432 Jun 11 04:10:06 PM PDT 24 Jun 11 05:27:29 PM PDT 24 17838509258 ps
T348 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.1441150886 Jun 11 04:00:35 PM PDT 24 Jun 11 04:10:25 PM PDT 24 4303522240 ps
T1140 /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.2942733398 Jun 11 04:09:19 PM PDT 24 Jun 11 04:25:34 PM PDT 24 5897742708 ps
T1141 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.459982205 Jun 11 04:13:23 PM PDT 24 Jun 11 04:28:40 PM PDT 24 9219024368 ps
T1142 /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.1303365378 Jun 11 04:09:30 PM PDT 24 Jun 11 04:15:42 PM PDT 24 6741876146 ps
T1143 /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.4176279326 Jun 11 04:16:31 PM PDT 24 Jun 11 04:31:44 PM PDT 24 5666849769 ps
T1144 /workspace/coverage/default/0.chip_sw_power_idle_load.3500859613 Jun 11 04:04:53 PM PDT 24 Jun 11 04:17:02 PM PDT 24 4322445080 ps
T1145 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.2747888721 Jun 11 04:04:06 PM PDT 24 Jun 11 04:08:13 PM PDT 24 3108638744 ps
T318 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.3424004691 Jun 11 03:59:48 PM PDT 24 Jun 11 04:10:42 PM PDT 24 4431691440 ps
T1146 /workspace/coverage/default/0.chip_sw_example_concurrency.3246102404 Jun 11 03:59:44 PM PDT 24 Jun 11 04:03:19 PM PDT 24 3202297716 ps
T287 /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.1489048446 Jun 11 04:27:07 PM PDT 24 Jun 11 04:32:56 PM PDT 24 3260815476 ps
T1147 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.821503272 Jun 11 04:10:16 PM PDT 24 Jun 11 04:58:43 PM PDT 24 21114709300 ps
T1148 /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.2034628683 Jun 11 04:05:38 PM PDT 24 Jun 11 04:28:09 PM PDT 24 5897655384 ps
T777 /workspace/coverage/default/87.chip_sw_all_escalation_resets.441650846 Jun 11 04:35:14 PM PDT 24 Jun 11 04:45:33 PM PDT 24 5028313940 ps
T1149 /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.558445090 Jun 11 04:05:21 PM PDT 24 Jun 11 04:10:22 PM PDT 24 2887453008 ps
T1150 /workspace/coverage/default/2.chip_sw_flash_ctrl_access.1115694755 Jun 11 04:17:16 PM PDT 24 Jun 11 04:34:31 PM PDT 24 5310152546 ps
T1151 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.1919367327 Jun 11 04:07:57 PM PDT 24 Jun 11 04:29:32 PM PDT 24 7354944056 ps
T1152 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.3200043951 Jun 11 04:21:25 PM PDT 24 Jun 11 04:36:30 PM PDT 24 5293598472 ps
T1153 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1223906237 Jun 11 03:59:33 PM PDT 24 Jun 11 04:21:35 PM PDT 24 14705217736 ps
T1154 /workspace/coverage/default/0.chip_sw_inject_scramble_seed.772426290 Jun 11 03:59:41 PM PDT 24 Jun 11 07:19:24 PM PDT 24 65953247486 ps
T1155 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3799470965 Jun 11 04:04:38 PM PDT 24 Jun 11 04:12:12 PM PDT 24 4466099186 ps
T386 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2284077580 Jun 11 04:13:50 PM PDT 24 Jun 11 04:23:39 PM PDT 24 7496003980 ps
T1156 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.2496331506 Jun 11 04:13:33 PM PDT 24 Jun 11 05:42:04 PM PDT 24 22747733680 ps
T354 /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3177315928 Jun 11 04:03:01 PM PDT 24 Jun 11 04:10:55 PM PDT 24 3763852824 ps
T1157 /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.3429682686 Jun 11 03:59:40 PM PDT 24 Jun 11 04:07:39 PM PDT 24 4245881350 ps
T359 /workspace/coverage/default/56.chip_sw_all_escalation_resets.643269630 Jun 11 04:30:57 PM PDT 24 Jun 11 04:40:42 PM PDT 24 4493614168 ps
T1158 /workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.3430403306 Jun 11 04:18:32 PM PDT 24 Jun 11 04:41:14 PM PDT 24 7841044800 ps
T9 /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.3115870504 Jun 11 04:16:47 PM PDT 24 Jun 11 04:23:26 PM PDT 24 3267524554 ps
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