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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 95.52 93.75 95.49 94.47 97.53 99.64


Total test records in report: 2896
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T658 /workspace/coverage/default/1.rom_e2e_asm_init_dev.3459986754 Jun 11 04:19:59 PM PDT 24 Jun 11 05:11:08 PM PDT 24 14859239861 ps
T659 /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.4051714751 Jun 11 04:10:51 PM PDT 24 Jun 11 04:50:05 PM PDT 24 11891246308 ps
T660 /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.339777872 Jun 11 04:25:47 PM PDT 24 Jun 11 04:32:08 PM PDT 24 3862049468 ps
T661 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.179784862 Jun 11 04:13:15 PM PDT 24 Jun 11 05:11:06 PM PDT 24 16966344488 ps
T662 /workspace/coverage/default/3.chip_tap_straps_testunlock0.3104329242 Jun 11 04:24:15 PM PDT 24 Jun 11 04:30:58 PM PDT 24 4211220072 ps
T663 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.381787689 Jun 11 04:07:41 PM PDT 24 Jun 11 04:26:20 PM PDT 24 7615895688 ps
T317 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.2830251761 Jun 11 03:58:20 PM PDT 24 Jun 11 04:09:48 PM PDT 24 4849209880 ps
T664 /workspace/coverage/default/2.rom_e2e_shutdown_output.3685293052 Jun 11 04:28:31 PM PDT 24 Jun 11 05:22:44 PM PDT 24 24807318003 ps
T665 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3922629656 Jun 11 04:22:42 PM PDT 24 Jun 11 04:34:31 PM PDT 24 5089567774 ps
T1159 /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.276372142 Jun 11 04:21:26 PM PDT 24 Jun 11 04:27:23 PM PDT 24 3649776508 ps
T1160 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3754786174 Jun 11 04:00:42 PM PDT 24 Jun 11 04:02:24 PM PDT 24 2356467789 ps
T412 /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.2293156308 Jun 11 04:32:37 PM PDT 24 Jun 11 04:40:02 PM PDT 24 3957163992 ps
T1161 /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.316131955 Jun 11 04:03:15 PM PDT 24 Jun 11 04:49:57 PM PDT 24 25553193233 ps
T1162 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.2917701088 Jun 11 04:09:10 PM PDT 24 Jun 11 04:24:51 PM PDT 24 8883821075 ps
T288 /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1041439104 Jun 11 04:31:37 PM PDT 24 Jun 11 04:40:32 PM PDT 24 4118693480 ps
T780 /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.3438872128 Jun 11 04:33:48 PM PDT 24 Jun 11 04:40:02 PM PDT 24 3887941224 ps
T1163 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.635025182 Jun 11 04:06:08 PM PDT 24 Jun 11 04:18:21 PM PDT 24 4447755704 ps
T1164 /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.819172885 Jun 11 04:05:02 PM PDT 24 Jun 11 04:12:10 PM PDT 24 4164234964 ps
T1165 /workspace/coverage/default/2.chip_sw_aes_entropy.9412225 Jun 11 04:19:28 PM PDT 24 Jun 11 04:23:18 PM PDT 24 3330903096 ps
T1166 /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.2249537791 Jun 11 04:28:01 PM PDT 24 Jun 11 05:02:14 PM PDT 24 13533188184 ps
T1167 /workspace/coverage/default/0.chip_sw_gpio_smoketest.3446193870 Jun 11 04:05:21 PM PDT 24 Jun 11 04:09:07 PM PDT 24 3221450530 ps
T1168 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.3443055169 Jun 11 04:18:39 PM PDT 24 Jun 11 05:17:18 PM PDT 24 14377031568 ps
T1169 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.1907364673 Jun 11 04:00:31 PM PDT 24 Jun 11 04:21:25 PM PDT 24 6536496250 ps
T1170 /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.3728599549 Jun 11 04:20:55 PM PDT 24 Jun 11 04:26:00 PM PDT 24 2543795492 ps
T1171 /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.534864071 Jun 11 04:10:51 PM PDT 24 Jun 11 04:56:34 PM PDT 24 32846452779 ps
T1172 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.2752967039 Jun 11 04:16:44 PM PDT 24 Jun 11 04:27:57 PM PDT 24 4318536296 ps
T1173 /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.929801770 Jun 11 04:12:44 PM PDT 24 Jun 11 04:35:32 PM PDT 24 11718647288 ps
T349 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4132061676 Jun 11 04:14:04 PM PDT 24 Jun 11 04:27:29 PM PDT 24 5379764431 ps
T369 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.825599091 Jun 11 04:07:36 PM PDT 24 Jun 11 04:24:25 PM PDT 24 5210704396 ps
T1174 /workspace/coverage/default/1.chip_sw_example_rom.4074987550 Jun 11 04:06:20 PM PDT 24 Jun 11 04:08:46 PM PDT 24 3212135372 ps
T183 /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.1893178174 Jun 11 04:19:53 PM PDT 24 Jun 11 04:27:54 PM PDT 24 4782445474 ps
T763 /workspace/coverage/default/62.chip_sw_all_escalation_resets.2356599338 Jun 11 04:32:28 PM PDT 24 Jun 11 04:42:02 PM PDT 24 4349356234 ps
T1175 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.598891845 Jun 11 04:00:28 PM PDT 24 Jun 11 04:32:09 PM PDT 24 12479458845 ps
T691 /workspace/coverage/default/83.chip_sw_all_escalation_resets.325581307 Jun 11 04:35:07 PM PDT 24 Jun 11 04:42:53 PM PDT 24 5616697880 ps
T1176 /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.3278887190 Jun 11 04:25:34 PM PDT 24 Jun 11 04:39:11 PM PDT 24 11653828583 ps
T1177 /workspace/coverage/default/4.chip_tap_straps_prod.3094941014 Jun 11 04:25:06 PM PDT 24 Jun 11 04:43:52 PM PDT 24 11852710363 ps
T1178 /workspace/coverage/default/2.chip_sw_aon_timer_irq.3525713001 Jun 11 04:19:09 PM PDT 24 Jun 11 04:26:55 PM PDT 24 4161944312 ps
T781 /workspace/coverage/default/81.chip_sw_all_escalation_resets.2583594032 Jun 11 04:37:29 PM PDT 24 Jun 11 04:44:39 PM PDT 24 4124413566 ps
T1179 /workspace/coverage/default/0.chip_sw_flash_crash_alert.3581562647 Jun 11 04:05:52 PM PDT 24 Jun 11 04:16:55 PM PDT 24 5358388260 ps
T1180 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.447527494 Jun 11 04:04:19 PM PDT 24 Jun 11 04:09:36 PM PDT 24 3138096982 ps
T707 /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.1390157813 Jun 11 04:34:41 PM PDT 24 Jun 11 04:41:48 PM PDT 24 3909515656 ps
T767 /workspace/coverage/default/52.chip_sw_all_escalation_resets.3334659763 Jun 11 04:33:26 PM PDT 24 Jun 11 04:42:22 PM PDT 24 4773313668 ps
T1181 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.1082623792 Jun 11 04:00:43 PM PDT 24 Jun 11 04:04:32 PM PDT 24 3028542879 ps
T1182 /workspace/coverage/default/2.chip_sw_example_flash.730794164 Jun 11 04:18:18 PM PDT 24 Jun 11 04:22:05 PM PDT 24 2373303672 ps
T692 /workspace/coverage/default/21.chip_sw_all_escalation_resets.2492264713 Jun 11 04:28:54 PM PDT 24 Jun 11 04:39:56 PM PDT 24 5957112456 ps
T1183 /workspace/coverage/default/5.chip_sw_data_integrity_escalation.1778687667 Jun 11 04:26:08 PM PDT 24 Jun 11 04:37:10 PM PDT 24 5376729992 ps
T1184 /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.659272947 Jun 11 04:00:42 PM PDT 24 Jun 11 04:11:41 PM PDT 24 5526750894 ps
T1185 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.4165316804 Jun 11 04:20:57 PM PDT 24 Jun 11 04:55:27 PM PDT 24 13199737824 ps
T335 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.1046012187 Jun 11 04:16:49 PM PDT 24 Jun 11 04:31:44 PM PDT 24 5095906272 ps
T1186 /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.3045339424 Jun 11 04:19:33 PM PDT 24 Jun 11 04:25:23 PM PDT 24 6528091728 ps
T1187 /workspace/coverage/default/1.chip_sw_flash_crash_alert.1143206127 Jun 11 04:14:19 PM PDT 24 Jun 11 04:24:47 PM PDT 24 5608267384 ps
T399 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.294375271 Jun 11 04:24:06 PM PDT 24 Jun 11 04:52:18 PM PDT 24 23148358232 ps
T1188 /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.2524415580 Jun 11 04:20:36 PM PDT 24 Jun 11 04:31:10 PM PDT 24 5417917696 ps
T759 /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.1471277650 Jun 11 04:28:15 PM PDT 24 Jun 11 04:33:39 PM PDT 24 3643511230 ps
T1189 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.2461211530 Jun 11 04:09:18 PM PDT 24 Jun 11 04:20:53 PM PDT 24 6000557336 ps
T49 /workspace/coverage/default/0.chip_sw_spi_device_tpm.1046844155 Jun 11 04:00:11 PM PDT 24 Jun 11 04:05:16 PM PDT 24 3142342407 ps
T1190 /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.1741453656 Jun 11 04:22:34 PM PDT 24 Jun 11 04:30:11 PM PDT 24 4044572792 ps
T1191 /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.1735760288 Jun 11 04:27:59 PM PDT 24 Jun 11 04:39:21 PM PDT 24 4173238970 ps
T1192 /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.643070702 Jun 11 04:27:27 PM PDT 24 Jun 11 04:51:48 PM PDT 24 8674166232 ps
T320 /workspace/coverage/default/1.chip_plic_all_irqs_20.1796254269 Jun 11 04:13:59 PM PDT 24 Jun 11 04:26:59 PM PDT 24 4980975912 ps
T1193 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.965253482 Jun 11 04:19:02 PM PDT 24 Jun 11 04:28:51 PM PDT 24 5926709056 ps
T1194 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.109512526 Jun 11 04:24:21 PM PDT 24 Jun 11 04:35:12 PM PDT 24 4290580342 ps
T1195 /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.3677349084 Jun 11 04:06:34 PM PDT 24 Jun 11 04:15:57 PM PDT 24 6751915616 ps
T504 /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.4256531528 Jun 11 04:09:04 PM PDT 24 Jun 11 04:22:29 PM PDT 24 4669385512 ps
T689 /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.1193603827 Jun 11 04:31:43 PM PDT 24 Jun 11 04:36:47 PM PDT 24 3869558450 ps
T106 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.2177561842 Jun 11 04:22:54 PM PDT 24 Jun 11 05:27:54 PM PDT 24 16926348276 ps
T1196 /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.1827710512 Jun 11 04:10:41 PM PDT 24 Jun 11 04:18:41 PM PDT 24 5343795608 ps
T1197 /workspace/coverage/default/1.chip_sw_inject_scramble_seed.1969099803 Jun 11 04:06:18 PM PDT 24 Jun 11 07:09:02 PM PDT 24 66248930244 ps
T1198 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.1464937468 Jun 11 04:02:58 PM PDT 24 Jun 11 04:10:49 PM PDT 24 6252369998 ps
T331 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.3722930674 Jun 11 04:06:36 PM PDT 24 Jun 11 04:17:03 PM PDT 24 4149102713 ps
T1199 /workspace/coverage/default/1.rom_e2e_static_critical.1060036462 Jun 11 04:19:23 PM PDT 24 Jun 11 05:31:53 PM PDT 24 16178718120 ps
T1200 /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.1679353819 Jun 11 04:18:04 PM PDT 24 Jun 11 04:21:40 PM PDT 24 2982271478 ps
T184 /workspace/coverage/default/2.chip_sw_spi_device_pass_through.977212843 Jun 11 04:18:37 PM PDT 24 Jun 11 04:30:15 PM PDT 24 6412457080 ps
T1201 /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.696430746 Jun 11 04:02:47 PM PDT 24 Jun 11 04:29:10 PM PDT 24 11129022456 ps
T251 /workspace/coverage/default/91.chip_sw_all_escalation_resets.3115017885 Jun 11 04:39:05 PM PDT 24 Jun 11 04:47:02 PM PDT 24 5726485278 ps
T669 /workspace/coverage/default/0.chip_sw_pattgen_ios.1826084259 Jun 11 03:59:36 PM PDT 24 Jun 11 04:04:06 PM PDT 24 3069498544 ps
T1202 /workspace/coverage/default/0.chip_sw_flash_ctrl_access.3668835903 Jun 11 04:01:14 PM PDT 24 Jun 11 04:21:04 PM PDT 24 4953172032 ps
T1203 /workspace/coverage/default/0.chip_sw_flash_init.1531986364 Jun 11 03:58:06 PM PDT 24 Jun 11 04:38:36 PM PDT 24 19955252567 ps
T1204 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.1293835549 Jun 11 04:15:00 PM PDT 24 Jun 11 04:19:53 PM PDT 24 3124627264 ps
T1205 /workspace/coverage/default/71.chip_sw_all_escalation_resets.974976635 Jun 11 04:33:51 PM PDT 24 Jun 11 04:41:50 PM PDT 24 4861626170 ps
T1206 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.4255924119 Jun 11 04:20:10 PM PDT 24 Jun 11 04:25:02 PM PDT 24 3013302086 ps
T336 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.2680666775 Jun 11 04:01:20 PM PDT 24 Jun 11 04:16:02 PM PDT 24 5335269184 ps
T1207 /workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.2101571746 Jun 11 04:26:40 PM PDT 24 Jun 11 05:21:52 PM PDT 24 16014980200 ps
T1208 /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.3332452621 Jun 11 04:17:12 PM PDT 24 Jun 11 04:22:13 PM PDT 24 3880476864 ps
T1209 /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.361445737 Jun 11 04:18:47 PM PDT 24 Jun 11 04:29:13 PM PDT 24 17955152170 ps
T1210 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.743259117 Jun 11 04:02:34 PM PDT 24 Jun 11 04:12:04 PM PDT 24 4794666195 ps
T1211 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1078675700 Jun 11 04:07:11 PM PDT 24 Jun 11 04:09:20 PM PDT 24 1948982024 ps
T1212 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.1932854824 Jun 11 04:09:15 PM PDT 24 Jun 11 05:37:21 PM PDT 24 21409176401 ps
T1213 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.2141146450 Jun 11 03:59:59 PM PDT 24 Jun 11 05:02:43 PM PDT 24 19553452656 ps
T1214 /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.240448307 Jun 11 04:08:03 PM PDT 24 Jun 11 04:12:50 PM PDT 24 3587966608 ps
T1215 /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.542913975 Jun 11 04:24:37 PM PDT 24 Jun 11 04:30:11 PM PDT 24 3355785360 ps
T131 /workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.1608512911 Jun 11 04:24:16 PM PDT 24 Jun 11 04:57:26 PM PDT 24 17158204799 ps
T1216 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.75884496 Jun 11 04:19:41 PM PDT 24 Jun 11 04:56:28 PM PDT 24 9463588116 ps
T1217 /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.4083323090 Jun 11 04:01:05 PM PDT 24 Jun 11 04:44:31 PM PDT 24 29938080456 ps
T1218 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.2336716090 Jun 11 04:12:37 PM PDT 24 Jun 11 05:07:05 PM PDT 24 13126711992 ps
T1219 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2543410591 Jun 11 04:01:15 PM PDT 24 Jun 11 04:57:31 PM PDT 24 42479458207 ps
T1220 /workspace/coverage/default/2.chip_sw_alert_handler_escalation.675803720 Jun 11 04:18:47 PM PDT 24 Jun 11 04:26:36 PM PDT 24 5218597206 ps
T771 /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.4029169205 Jun 11 04:35:32 PM PDT 24 Jun 11 04:42:46 PM PDT 24 3498253850 ps
T1221 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.2718606757 Jun 11 04:17:51 PM PDT 24 Jun 11 04:29:12 PM PDT 24 7119996625 ps
T1222 /workspace/coverage/default/1.chip_sw_hmac_enc_idle.534954162 Jun 11 04:11:33 PM PDT 24 Jun 11 04:16:48 PM PDT 24 2842257210 ps
T1223 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3761597623 Jun 11 04:17:39 PM PDT 24 Jun 11 04:55:37 PM PDT 24 22473390115 ps
T1224 /workspace/coverage/default/0.chip_sw_csrng_smoketest.3387938291 Jun 11 04:08:00 PM PDT 24 Jun 11 04:11:30 PM PDT 24 2595506276 ps
T778 /workspace/coverage/default/96.chip_sw_all_escalation_resets.1630131807 Jun 11 04:34:16 PM PDT 24 Jun 11 04:41:11 PM PDT 24 4125619480 ps
T1225 /workspace/coverage/default/1.chip_sw_aes_idle.2335011059 Jun 11 04:12:35 PM PDT 24 Jun 11 04:16:55 PM PDT 24 2615615780 ps
T1226 /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.75757760 Jun 11 04:19:11 PM PDT 24 Jun 11 07:31:23 PM PDT 24 256277184720 ps
T714 /workspace/coverage/default/86.chip_sw_all_escalation_resets.1634686356 Jun 11 04:33:15 PM PDT 24 Jun 11 04:40:49 PM PDT 24 5446975176 ps
T1227 /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.213942223 Jun 11 04:08:04 PM PDT 24 Jun 11 04:15:08 PM PDT 24 3736599506 ps
T289 /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.2431005709 Jun 11 04:30:22 PM PDT 24 Jun 11 04:37:42 PM PDT 24 3585392258 ps
T1228 /workspace/coverage/default/57.chip_sw_all_escalation_resets.31251906 Jun 11 04:31:29 PM PDT 24 Jun 11 04:39:26 PM PDT 24 4360934044 ps
T768 /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.2106675560 Jun 11 04:30:42 PM PDT 24 Jun 11 04:38:16 PM PDT 24 3405117266 ps
T319 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.1233158085 Jun 11 04:06:52 PM PDT 24 Jun 11 04:23:06 PM PDT 24 5319291960 ps
T642 /workspace/coverage/default/39.chip_sw_all_escalation_resets.3918791693 Jun 11 04:30:41 PM PDT 24 Jun 11 04:41:38 PM PDT 24 5553554312 ps
T1229 /workspace/coverage/default/2.chip_sw_clkmgr_jitter.3311607697 Jun 11 04:20:00 PM PDT 24 Jun 11 04:23:49 PM PDT 24 2788542898 ps
T303 /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.187834903 Jun 11 04:20:45 PM PDT 24 Jun 11 04:35:41 PM PDT 24 7890652341 ps
T1230 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.931401064 Jun 11 04:20:08 PM PDT 24 Jun 11 04:51:41 PM PDT 24 10221221448 ps
T747 /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.2625110838 Jun 11 04:32:47 PM PDT 24 Jun 11 04:38:42 PM PDT 24 3486855188 ps
T1231 /workspace/coverage/default/0.rom_e2e_jtag_inject_rma.1142898854 Jun 11 04:05:19 PM PDT 24 Jun 11 04:59:23 PM PDT 24 30975808787 ps
T1232 /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.1161860188 Jun 11 04:06:39 PM PDT 24 Jun 11 04:12:09 PM PDT 24 3724716680 ps
T1233 /workspace/coverage/default/1.rom_e2e_asm_init_prod.3868777144 Jun 11 04:18:31 PM PDT 24 Jun 11 05:14:45 PM PDT 24 14191743383 ps
T329 /workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.2667009826 Jun 11 04:13:34 PM PDT 24 Jun 11 04:21:44 PM PDT 24 4526652456 ps
T185 /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.4003845615 Jun 11 04:05:52 PM PDT 24 Jun 11 04:14:07 PM PDT 24 3757800505 ps
T1234 /workspace/coverage/default/0.chip_sw_uart_smoketest.2156421724 Jun 11 04:07:18 PM PDT 24 Jun 11 04:13:00 PM PDT 24 3350809140 ps
T752 /workspace/coverage/default/55.chip_sw_all_escalation_resets.3277448936 Jun 11 04:32:50 PM PDT 24 Jun 11 04:42:02 PM PDT 24 5955835224 ps
T315 /workspace/coverage/default/2.chip_sw_entropy_src_csrng.716795123 Jun 11 04:21:05 PM PDT 24 Jun 11 04:43:42 PM PDT 24 5466775048 ps
T370 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.1767066373 Jun 11 04:17:01 PM PDT 24 Jun 11 04:28:50 PM PDT 24 4826727694 ps
T1235 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.498683879 Jun 11 04:12:26 PM PDT 24 Jun 11 05:04:43 PM PDT 24 14133191439 ps
T413 /workspace/coverage/default/65.chip_sw_all_escalation_resets.412440920 Jun 11 04:31:51 PM PDT 24 Jun 11 04:40:43 PM PDT 24 4491343154 ps
T1236 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.2261883011 Jun 11 04:00:19 PM PDT 24 Jun 11 04:04:27 PM PDT 24 2862717460 ps
T1237 /workspace/coverage/default/2.chip_sw_uart_smoketest.2023145335 Jun 11 04:24:02 PM PDT 24 Jun 11 04:27:23 PM PDT 24 2744184584 ps
T1238 /workspace/coverage/default/4.chip_sw_data_integrity_escalation.2819095815 Jun 11 04:25:06 PM PDT 24 Jun 11 04:36:35 PM PDT 24 4206791976 ps
T1239 /workspace/coverage/default/1.chip_sw_example_manufacturer.3372980611 Jun 11 04:08:21 PM PDT 24 Jun 11 04:11:57 PM PDT 24 2841613104 ps
T506 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2365463984 Jun 11 04:17:43 PM PDT 24 Jun 11 04:27:09 PM PDT 24 5336429412 ps
T1240 /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.1074782684 Jun 11 04:24:26 PM PDT 24 Jun 11 04:27:50 PM PDT 24 2410659350 ps
T708 /workspace/coverage/default/93.chip_sw_all_escalation_resets.521100630 Jun 11 04:35:33 PM PDT 24 Jun 11 04:43:40 PM PDT 24 4487799080 ps
T313 /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.2674411115 Jun 11 04:00:13 PM PDT 24 Jun 11 04:43:37 PM PDT 24 12604627028 ps
T1241 /workspace/coverage/default/2.chip_sw_kmac_app_rom.938026755 Jun 11 04:20:42 PM PDT 24 Jun 11 04:24:06 PM PDT 24 2870340600 ps
T1242 /workspace/coverage/default/1.chip_sival_flash_info_access.90934291 Jun 11 04:05:57 PM PDT 24 Jun 11 04:11:25 PM PDT 24 3086265644 ps
T1243 /workspace/coverage/default/1.chip_sw_example_flash.3036191438 Jun 11 04:08:19 PM PDT 24 Jun 11 04:12:25 PM PDT 24 2232718840 ps
T1244 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3888358864 Jun 11 04:00:36 PM PDT 24 Jun 11 04:33:47 PM PDT 24 21724718120 ps
T1245 /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.1170513695 Jun 11 04:07:13 PM PDT 24 Jun 11 04:24:03 PM PDT 24 6219327227 ps
T1246 /workspace/coverage/default/2.chip_sival_flash_info_access.2756714167 Jun 11 04:16:50 PM PDT 24 Jun 11 04:22:14 PM PDT 24 2569348800 ps
T631 /workspace/coverage/default/0.chip_tap_straps_dev.1902458670 Jun 11 04:03:13 PM PDT 24 Jun 11 04:26:33 PM PDT 24 12208035409 ps
T1247 /workspace/coverage/default/1.rom_e2e_asm_init_rma.2585480081 Jun 11 04:20:22 PM PDT 24 Jun 11 05:17:29 PM PDT 24 14981891965 ps
T60 /workspace/coverage/default/1.chip_jtag_csr_rw.98236872 Jun 11 04:05:29 PM PDT 24 Jun 11 04:43:09 PM PDT 24 16282816610 ps
T1248 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.3269601883 Jun 11 04:00:18 PM PDT 24 Jun 11 04:12:12 PM PDT 24 4380040284 ps
T1249 /workspace/coverage/default/0.rom_e2e_asm_init_dev.1226734789 Jun 11 04:16:31 PM PDT 24 Jun 11 05:25:50 PM PDT 24 14444186860 ps
T1250 /workspace/coverage/default/2.rom_e2e_asm_init_prod.500267099 Jun 11 04:28:10 PM PDT 24 Jun 11 05:22:51 PM PDT 24 14722025296 ps
T214 /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.3803320473 Jun 11 04:19:18 PM PDT 24 Jun 11 04:45:39 PM PDT 24 8779391164 ps
T782 /workspace/coverage/default/32.chip_sw_all_escalation_resets.2104891714 Jun 11 04:28:53 PM PDT 24 Jun 11 04:36:44 PM PDT 24 5596800816 ps
T1251 /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.719696326 Jun 11 04:21:19 PM PDT 24 Jun 11 04:48:18 PM PDT 24 24903576921 ps
T1252 /workspace/coverage/default/0.chip_sw_aes_smoketest.3657573198 Jun 11 04:13:18 PM PDT 24 Jun 11 04:19:03 PM PDT 24 2986921814 ps
T1253 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.2939664933 Jun 11 04:10:18 PM PDT 24 Jun 11 05:10:57 PM PDT 24 14771997312 ps
T1254 /workspace/coverage/default/16.chip_sw_all_escalation_resets.2465827130 Jun 11 04:28:29 PM PDT 24 Jun 11 04:38:01 PM PDT 24 5082455144 ps
T1255 /workspace/coverage/default/0.chip_sw_aes_masking_off.3410882008 Jun 11 04:01:08 PM PDT 24 Jun 11 04:05:18 PM PDT 24 3262854491 ps
T74 /workspace/coverage/default/0.chip_sw_usbdev_pullup.876492266 Jun 11 04:00:36 PM PDT 24 Jun 11 04:05:48 PM PDT 24 2881931680 ps
T1256 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.222481730 Jun 11 04:03:00 PM PDT 24 Jun 11 04:21:34 PM PDT 24 7111501353 ps
T1257 /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.1769124532 Jun 11 04:14:25 PM PDT 24 Jun 11 04:22:12 PM PDT 24 3285286210 ps
T252 /workspace/coverage/default/34.chip_sw_all_escalation_resets.2007810216 Jun 11 04:30:24 PM PDT 24 Jun 11 04:38:51 PM PDT 24 5248542408 ps
T232 /workspace/coverage/default/1.chip_sw_alert_test.383877386 Jun 11 04:10:53 PM PDT 24 Jun 11 04:16:15 PM PDT 24 2488800412 ps
T774 /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.12140710 Jun 11 04:32:54 PM PDT 24 Jun 11 04:38:57 PM PDT 24 3666777052 ps
T1258 /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.57147706 Jun 11 04:19:01 PM PDT 24 Jun 11 04:26:15 PM PDT 24 3679469536 ps
T693 /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.916803752 Jun 11 04:31:39 PM PDT 24 Jun 11 04:37:49 PM PDT 24 3458858088 ps
T1259 /workspace/coverage/default/0.chip_sival_flash_info_access.680334842 Jun 11 04:01:19 PM PDT 24 Jun 11 04:05:59 PM PDT 24 3203536070 ps
T601 /workspace/coverage/default/0.rom_e2e_jtag_debug_rma.1973280898 Jun 11 04:11:25 PM PDT 24 Jun 11 05:02:44 PM PDT 24 13835613375 ps
T147 /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.142354317 Jun 11 03:59:23 PM PDT 24 Jun 11 06:57:49 PM PDT 24 57754144264 ps
T1260 /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.2149452254 Jun 11 04:12:47 PM PDT 24 Jun 11 04:51:01 PM PDT 24 25454856485 ps
T1261 /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.1062470829 Jun 11 04:25:05 PM PDT 24 Jun 11 04:32:26 PM PDT 24 6078263680 ps
T1262 /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.3257352277 Jun 11 04:30:55 PM PDT 24 Jun 11 04:36:47 PM PDT 24 3559732220 ps
T87 /workspace/coverage/default/19.chip_sw_all_escalation_resets.362321626 Jun 11 04:29:19 PM PDT 24 Jun 11 04:39:35 PM PDT 24 5037821920 ps
T1263 /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.758015860 Jun 11 04:31:23 PM PDT 24 Jun 11 04:40:32 PM PDT 24 3859426642 ps
T1264 /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.160105730 Jun 11 04:29:18 PM PDT 24 Jun 11 04:36:44 PM PDT 24 3872605736 ps
T1265 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.2466397612 Jun 11 03:59:48 PM PDT 24 Jun 11 04:19:19 PM PDT 24 7373226784 ps
T1266 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.3856295682 Jun 11 04:10:56 PM PDT 24 Jun 11 05:32:18 PM PDT 24 17441655616 ps
T1267 /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.3206431667 Jun 11 04:14:52 PM PDT 24 Jun 11 04:20:11 PM PDT 24 3701340168 ps
T1268 /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.4189694400 Jun 11 04:06:07 PM PDT 24 Jun 11 04:09:52 PM PDT 24 2930442370 ps
T1269 /workspace/coverage/default/2.chip_sw_kmac_idle.3460955089 Jun 11 04:22:13 PM PDT 24 Jun 11 04:26:25 PM PDT 24 2686221186 ps
T1270 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1019946176 Jun 11 04:09:27 PM PDT 24 Jun 11 04:14:58 PM PDT 24 6737785988 ps
T326 /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.3699189050 Jun 11 04:06:30 PM PDT 24 Jun 11 04:14:43 PM PDT 24 3422420268 ps
T1271 /workspace/coverage/default/0.chip_sw_alert_handler_entropy.3003951289 Jun 11 04:03:18 PM PDT 24 Jun 11 04:09:39 PM PDT 24 3409510649 ps
T1272 /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.319594666 Jun 11 04:01:11 PM PDT 24 Jun 11 04:13:31 PM PDT 24 10202905792 ps
T700 /workspace/coverage/default/89.chip_sw_all_escalation_resets.3951678208 Jun 11 04:39:02 PM PDT 24 Jun 11 04:46:49 PM PDT 24 5197926496 ps
T1273 /workspace/coverage/default/0.rom_e2e_static_critical.68887841 Jun 11 04:10:58 PM PDT 24 Jun 11 05:19:00 PM PDT 24 16535725436 ps
T1274 /workspace/coverage/default/1.chip_sw_power_sleep_load.3066291291 Jun 11 04:14:01 PM PDT 24 Jun 11 04:26:31 PM PDT 24 10587996984 ps
T1275 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.81972978 Jun 11 04:08:13 PM PDT 24 Jun 11 04:44:01 PM PDT 24 22423752382 ps
T1276 /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.4087053867 Jun 11 04:21:33 PM PDT 24 Jun 11 04:25:56 PM PDT 24 2502453736 ps
T1277 /workspace/coverage/default/1.rom_e2e_shutdown_output.1788877359 Jun 11 04:20:20 PM PDT 24 Jun 11 05:05:01 PM PDT 24 23812730412 ps
T1278 /workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.706113502 Jun 11 04:14:03 PM PDT 24 Jun 11 04:20:06 PM PDT 24 3029071176 ps
T1279 /workspace/coverage/default/2.chip_sw_example_concurrency.828744872 Jun 11 04:16:35 PM PDT 24 Jun 11 04:22:04 PM PDT 24 2969681320 ps
T381 /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.643589539 Jun 11 04:02:52 PM PDT 24 Jun 11 04:11:41 PM PDT 24 4810444724 ps
T1280 /workspace/coverage/default/2.chip_sw_alert_handler_entropy.3747231845 Jun 11 04:18:57 PM PDT 24 Jun 11 04:26:21 PM PDT 24 4519713897 ps
T1281 /workspace/coverage/default/0.chip_sw_example_flash.547715280 Jun 11 03:59:17 PM PDT 24 Jun 11 04:04:52 PM PDT 24 3067251968 ps
T44 /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.3524116168 Jun 11 04:00:18 PM PDT 24 Jun 11 04:04:05 PM PDT 24 2478644712 ps
T1282 /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.296801528 Jun 11 04:14:25 PM PDT 24 Jun 11 04:22:38 PM PDT 24 4564750126 ps
T1283 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.965448959 Jun 11 03:59:11 PM PDT 24 Jun 11 04:08:42 PM PDT 24 4078044792 ps
T1284 /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.3684491224 Jun 11 04:18:55 PM PDT 24 Jun 11 04:38:48 PM PDT 24 5831040424 ps
T1285 /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.585601587 Jun 11 04:11:22 PM PDT 24 Jun 11 04:15:09 PM PDT 24 2395322248 ps
T1286 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.1293587641 Jun 11 04:04:47 PM PDT 24 Jun 11 04:23:41 PM PDT 24 6910564026 ps
T1287 /workspace/coverage/default/0.chip_sw_otbn_smoketest.3773856089 Jun 11 04:06:35 PM PDT 24 Jun 11 04:38:48 PM PDT 24 8142136450 ps
T1288 /workspace/coverage/default/0.rom_e2e_asm_init_prod.3416365379 Jun 11 04:09:51 PM PDT 24 Jun 11 05:09:07 PM PDT 24 13692438296 ps
T1289 /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.3934016858 Jun 11 04:18:29 PM PDT 24 Jun 11 04:22:25 PM PDT 24 2561730168 ps
T732 /workspace/coverage/default/2.chip_sw_all_escalation_resets.2080654239 Jun 11 04:17:25 PM PDT 24 Jun 11 04:27:36 PM PDT 24 4181020252 ps
T1290 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.4014957063 Jun 11 04:16:25 PM PDT 24 Jun 11 04:27:34 PM PDT 24 3957807460 ps
T321 /workspace/coverage/default/0.chip_plic_all_irqs_20.3862300246 Jun 11 04:01:36 PM PDT 24 Jun 11 04:14:20 PM PDT 24 4621606508 ps
T1291 /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.665671978 Jun 11 04:19:05 PM PDT 24 Jun 11 04:23:58 PM PDT 24 2585769300 ps
T1292 /workspace/coverage/default/2.chip_sw_flash_init.95633056 Jun 11 04:16:19 PM PDT 24 Jun 11 04:47:27 PM PDT 24 22857252504 ps
T656 /workspace/coverage/default/0.chip_sw_power_sleep_load.3937229731 Jun 11 04:04:58 PM PDT 24 Jun 11 04:13:08 PM PDT 24 4075545316 ps
T1293 /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.3713134372 Jun 11 04:06:07 PM PDT 24 Jun 11 06:57:36 PM PDT 24 58388329552 ps
T1294 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3262271293 Jun 11 04:18:26 PM PDT 24 Jun 11 04:41:31 PM PDT 24 14031544476 ps
T1295 /workspace/coverage/default/0.chip_tap_straps_testunlock0.3599110215 Jun 11 04:01:54 PM PDT 24 Jun 11 04:04:33 PM PDT 24 2760630808 ps
T353 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.3431451640 Jun 11 04:24:38 PM PDT 24 Jun 11 04:29:17 PM PDT 24 2503235796 ps
T290 /workspace/coverage/default/73.chip_sw_all_escalation_resets.4235608806 Jun 11 04:32:01 PM PDT 24 Jun 11 04:41:34 PM PDT 24 4258308620 ps
T1296 /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.3298438356 Jun 11 04:08:02 PM PDT 24 Jun 11 04:30:14 PM PDT 24 7746946323 ps
T1297 /workspace/coverage/default/2.chip_sw_uart_tx_rx.1187910573 Jun 11 04:16:34 PM PDT 24 Jun 11 04:26:48 PM PDT 24 4491317880 ps
T1298 /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.2958924198 Jun 11 04:05:56 PM PDT 24 Jun 11 04:12:18 PM PDT 24 5935357860 ps
T1299 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.1348879390 Jun 11 04:12:29 PM PDT 24 Jun 11 05:40:54 PM PDT 24 21829572616 ps
T1300 /workspace/coverage/default/0.rom_keymgr_functest.447143624 Jun 11 04:13:53 PM PDT 24 Jun 11 04:23:06 PM PDT 24 4325212322 ps
T1301 /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.1609042270 Jun 11 04:07:23 PM PDT 24 Jun 11 04:15:20 PM PDT 24 4116700606 ps
T1302 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3375352238 Jun 11 04:17:36 PM PDT 24 Jun 11 04:29:06 PM PDT 24 4562097820 ps
T1303 /workspace/coverage/default/2.chip_sw_plic_sw_irq.1248023262 Jun 11 04:21:28 PM PDT 24 Jun 11 04:26:20 PM PDT 24 2553590440 ps
T1304 /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.1264621288 Jun 11 04:26:19 PM PDT 24 Jun 11 04:37:50 PM PDT 24 5939549409 ps
T332 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.3180424884 Jun 11 04:07:33 PM PDT 24 Jun 11 04:17:38 PM PDT 24 4149814940 ps
T1305 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.2412250185 Jun 11 04:15:24 PM PDT 24 Jun 11 04:26:34 PM PDT 24 4344774900 ps
T1306 /workspace/coverage/default/1.chip_sw_alert_handler_entropy.1268509907 Jun 11 04:09:21 PM PDT 24 Jun 11 04:14:53 PM PDT 24 3018287843 ps
T1307 /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.4039832102 Jun 11 04:21:08 PM PDT 24 Jun 11 04:30:50 PM PDT 24 3407710014 ps
T715 /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.710346718 Jun 11 04:35:00 PM PDT 24 Jun 11 04:41:25 PM PDT 24 3758399940 ps
T1308 /workspace/coverage/default/2.chip_sw_aes_masking_off.2045449485 Jun 11 04:22:24 PM PDT 24 Jun 11 04:28:38 PM PDT 24 2979350825 ps
T1309 /workspace/coverage/default/2.chip_sw_otbn_smoketest.215751651 Jun 11 04:23:13 PM PDT 24 Jun 11 04:39:22 PM PDT 24 4963026290 ps
T1310 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.817689058 Jun 11 04:08:24 PM PDT 24 Jun 11 05:17:11 PM PDT 24 14768850000 ps
T749 /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.2870444632 Jun 11 04:31:56 PM PDT 24 Jun 11 04:37:24 PM PDT 24 3473745648 ps
T1311 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1022975157 Jun 11 04:21:56 PM PDT 24 Jun 11 05:23:14 PM PDT 24 24749137325 ps
T1312 /workspace/coverage/default/0.rom_e2e_shutdown_output.568124729 Jun 11 04:12:39 PM PDT 24 Jun 11 05:05:05 PM PDT 24 27691087632 ps
T1313 /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.2334971981 Jun 11 04:29:04 PM PDT 24 Jun 11 04:36:51 PM PDT 24 6538285090 ps
T295 /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1971043458 Jun 11 04:03:04 PM PDT 24 Jun 11 04:07:33 PM PDT 24 3267233120 ps
T1314 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.779720297 Jun 11 04:18:34 PM PDT 24 Jun 11 05:15:26 PM PDT 24 18974580312 ps
T1315 /workspace/coverage/default/85.chip_sw_all_escalation_resets.2602857825 Jun 11 04:33:20 PM PDT 24 Jun 11 04:42:08 PM PDT 24 5290233382 ps
T1316 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1270502453 Jun 11 04:13:49 PM PDT 24 Jun 11 04:26:55 PM PDT 24 5117202920 ps
T1317 /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.601640592 Jun 11 04:26:54 PM PDT 24 Jun 11 04:33:20 PM PDT 24 3972478980 ps
T711 /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.2304534209 Jun 11 04:32:36 PM PDT 24 Jun 11 04:39:29 PM PDT 24 3300672792 ps
T1318 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1413024257 Jun 11 04:09:48 PM PDT 24 Jun 11 04:56:40 PM PDT 24 11166948836 ps
T1319 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.1442110958 Jun 11 04:21:38 PM PDT 24 Jun 11 04:31:26 PM PDT 24 6344730820 ps
T1320 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.2431421647 Jun 11 04:24:46 PM PDT 24 Jun 11 04:36:07 PM PDT 24 4889363908 ps
T1321 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.334623089 Jun 11 04:21:31 PM PDT 24 Jun 11 04:35:05 PM PDT 24 5481765750 ps
T1322 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.803658212 Jun 11 04:13:44 PM PDT 24 Jun 11 05:09:45 PM PDT 24 13384364970 ps
T784 /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3702989085 Jun 11 04:33:47 PM PDT 24 Jun 11 04:39:46 PM PDT 24 4036122400 ps
T729 /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3799160314 Jun 11 04:33:53 PM PDT 24 Jun 11 04:41:18 PM PDT 24 4318349296 ps
T1323 /workspace/coverage/default/1.chip_sw_power_idle_load.3115007204 Jun 11 04:17:59 PM PDT 24 Jun 11 04:27:58 PM PDT 24 4842722962 ps
T1324 /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.3833680088 Jun 11 04:13:44 PM PDT 24 Jun 11 04:35:33 PM PDT 24 5882593866 ps
T75 /workspace/coverage/cover_reg_top/71.xbar_same_source.622745584 Jun 11 03:38:13 PM PDT 24 Jun 11 03:38:46 PM PDT 24 419672672 ps
T76 /workspace/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.3620429226 Jun 11 03:35:39 PM PDT 24 Jun 11 04:14:20 PM PDT 24 130185054834 ps
T77 /workspace/coverage/cover_reg_top/47.xbar_smoke_large_delays.3328895298 Jun 11 03:34:45 PM PDT 24 Jun 11 03:36:30 PM PDT 24 9317568482 ps
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