Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1400211	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

32679996

1

T4

5625

T5

111562

T6

4864

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	23405690	1			T4	2391		T5	98806		T6	1797
values[0x0]	9273412	1			T4	3234		T5	12756		T6	3067
values[0x1]	1401105	1			T4	428		T5	4		T6	383

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8550	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

34071657

1

T4

6053

T5

111566

T6

5247

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17026776	1			T4	3027		T5	55783		T6	2624
valid_sources[0x01]	17025726	1			T4	3026		T5	55783		T6	2623
valid_sources[0x02]	414	1			T61	3		T38	28		T39	62
valid_sources[0x03]	321	1			T60	7		T61	2		T38	25
valid_sources[0x04]	497	1			T60	3		T38	41		T39	51
valid_sources[0x05]	403	1			T9	1		T61	1		T38	44
valid_sources[0x06]	347	1			T60	4		T38	24		T39	46
valid_sources[0x07]	382	1			T9	1		T38	35		T39	39
valid_sources[0x08]	417	1			T60	1		T38	32		T39	37
valid_sources[0x09]	283	1			T9	1		T38	21		T39	57
valid_sources[0x0a]	374	1			T9	2		T61	4		T38	20
valid_sources[0x0b]	333	1			T60	4		T9	2		T61	1
valid_sources[0x0c]	335	1			T61	1		T38	26		T39	46
valid_sources[0x0d]	382	1			T9	1		T61	1		T12	39
valid_sources[0x0e]	328	1			T9	1		T38	44		T39	39
valid_sources[0x0f]	276	1			T38	33		T39	45		T239	22
valid_sources[0x10]	366	1			T61	2		T38	25		T39	37
valid_sources[0x11]	385	1			T9	2		T38	45		T39	40
valid_sources[0x12]	431	1			T38	28		T39	52		T237	74
valid_sources[0x13]	363	1			T9	1		T38	20		T39	29
valid_sources[0x14]	422	1			T9	3		T38	20		T39	33
valid_sources[0x15]	318	1			T38	24		T39	32		T237	9
valid_sources[0x16]	390	1			T60	1		T38	25		T39	46
valid_sources[0x17]	420	1			T150	39		T38	23		T39	39
valid_sources[0x18]	338	1			T38	45		T39	35		T239	70
valid_sources[0x19]	358	1			T38	25		T39	34		T237	62
valid_sources[0x1a]	331	1			T38	36		T39	33		T237	9
valid_sources[0x1b]	334	1			T60	1		T9	2		T61	2
valid_sources[0x1c]	296	1			T38	25		T39	32		T239	46
valid_sources[0x1d]	439	1			T61	1		T38	28		T39	51
valid_sources[0x1e]	412	1			T61	1		T116	27		T38	41
valid_sources[0x1f]	354	1			T9	1		T38	42		T39	32
valid_sources[0x20]	424	1			T61	4		T38	29		T39	37

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

23405690

1

T4

2391

T5

98806

T6

1797

values[0x0]

all_enables

biggest_size

9269007

1

T4

3234

T5

12756

T6

3067

values[0x1]

all_enables

biggest_size

5299

1

T60

14

T9

23

T61

15