| SCORE |
LINE |
COND |
TOGGLE |
FSM |
BRANCH |
ASSERT |
GROUP |
|
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
| 39.24 |
39.24 |
45.59 |
45.59 |
44.99 |
44.99 |
23.93 |
23.93 |
|
|
59.35 |
59.35 |
58.92 |
58.92 |
2.63 |
2.63 |
/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.1053882651 |
| 52.27 |
13.03 |
57.93 |
12.33 |
58.51 |
13.52 |
28.13 |
4.20 |
|
|
71.83 |
12.48 |
85.14 |
26.22 |
12.06 |
9.43 |
/workspace/coverage/default/2.chip_jtag_csr_rw.1353314733 |
| 60.76 |
8.49 |
58.08 |
0.15 |
58.69 |
0.18 |
31.81 |
3.67 |
|
|
71.87 |
0.04 |
85.31 |
0.17 |
58.77 |
46.71 |
/workspace/coverage/default/1.chip_sw_alert_test.2215097811 |
| 66.11 |
5.36 |
68.79 |
10.71 |
64.11 |
5.42 |
36.20 |
4.40 |
|
|
74.57 |
2.69 |
89.86 |
4.55 |
63.16 |
4.39 |
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.107457228 |
| 71.39 |
5.28 |
80.54 |
11.75 |
71.98 |
7.87 |
37.69 |
1.49 |
|
|
85.12 |
10.55 |
89.86 |
0.00 |
63.16 |
0.00 |
/workspace/coverage/default/2.chip_plic_all_irqs_0.734804293 |
| 74.93 |
3.53 |
80.54 |
0.00 |
71.99 |
0.01 |
58.31 |
20.62 |
|
|
85.13 |
0.01 |
90.21 |
0.35 |
63.38 |
0.22 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.1671178314 |
| 76.58 |
1.66 |
80.81 |
0.27 |
72.14 |
0.15 |
66.60 |
8.29 |
|
|
85.30 |
0.18 |
90.38 |
0.17 |
64.25 |
0.88 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.3362718793 |
| 78.00 |
1.42 |
82.30 |
1.49 |
73.15 |
1.01 |
71.61 |
5.01 |
|
|
85.95 |
0.65 |
90.73 |
0.35 |
64.25 |
0.00 |
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.335524233 |
| 79.19 |
1.19 |
84.27 |
1.97 |
75.68 |
2.53 |
71.83 |
0.22 |
|
|
88.39 |
2.43 |
90.73 |
0.00 |
64.25 |
0.00 |
/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.1373576097 |
| 80.36 |
1.17 |
86.26 |
1.99 |
77.19 |
1.52 |
73.28 |
1.46 |
|
|
90.44 |
2.05 |
90.73 |
0.00 |
64.25 |
0.00 |
/workspace/coverage/default/2.chip_plic_all_irqs_20.1273307471 |
| 81.32 |
0.95 |
86.59 |
0.33 |
77.48 |
0.29 |
75.29 |
2.00 |
|
|
90.74 |
0.30 |
90.91 |
0.17 |
66.89 |
2.63 |
/workspace/coverage/default/63.chip_sw_all_escalation_resets.3131941705 |
| 82.02 |
0.70 |
86.74 |
0.15 |
77.57 |
0.09 |
75.30 |
0.01 |
|
|
90.85 |
0.11 |
94.76 |
3.85 |
66.89 |
0.00 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.617217562 |
| 82.57 |
0.55 |
87.55 |
0.81 |
78.34 |
0.77 |
75.64 |
0.34 |
|
|
91.73 |
0.88 |
95.28 |
0.52 |
66.89 |
0.00 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3521582568 |
| 83.06 |
0.48 |
87.55 |
0.00 |
78.34 |
0.00 |
78.55 |
2.91 |
|
|
91.73 |
0.00 |
95.28 |
0.00 |
66.89 |
0.00 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.341146098 |
| 83.46 |
0.40 |
88.47 |
0.92 |
78.90 |
0.56 |
79.08 |
0.53 |
|
|
92.15 |
0.42 |
95.28 |
0.00 |
66.89 |
0.00 |
/workspace/coverage/default/1.chip_sw_gpio.1639669541 |
| 83.86 |
0.40 |
89.02 |
0.55 |
79.35 |
0.45 |
79.99 |
0.92 |
|
|
92.62 |
0.46 |
95.28 |
0.00 |
66.89 |
0.00 |
/workspace/coverage/default/0.chip_plic_all_irqs_10.644304353 |
| 84.22 |
0.36 |
89.10 |
0.08 |
79.37 |
0.01 |
81.13 |
1.14 |
|
|
92.62 |
0.01 |
95.98 |
0.70 |
67.11 |
0.22 |
/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.152347801 |
| 84.57 |
0.36 |
89.11 |
0.01 |
79.37 |
0.01 |
83.26 |
2.13 |
|
|
92.62 |
0.00 |
95.98 |
0.00 |
67.11 |
0.00 |
/workspace/coverage/default/2.chip_sw_edn_auto_mode.1889999175 |
| 84.89 |
0.32 |
89.47 |
0.36 |
80.14 |
0.77 |
83.31 |
0.05 |
|
|
93.35 |
0.72 |
95.98 |
0.00 |
67.11 |
0.00 |
/workspace/coverage/default/1.chip_jtag_csr_rw.4210584816 |
| 85.18 |
0.29 |
89.50 |
0.03 |
80.15 |
0.01 |
83.32 |
0.01 |
|
|
93.35 |
0.01 |
96.15 |
0.17 |
68.64 |
1.54 |
/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.2221801429 |
| 85.44 |
0.25 |
89.82 |
0.32 |
80.33 |
0.18 |
84.19 |
0.87 |
|
|
93.51 |
0.15 |
96.15 |
0.00 |
68.64 |
0.00 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.3664844048 |
| 85.64 |
0.20 |
90.13 |
0.31 |
80.58 |
0.26 |
84.52 |
0.33 |
|
|
93.82 |
0.32 |
96.15 |
0.00 |
68.64 |
0.00 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.65693800 |
| 85.84 |
0.20 |
90.67 |
0.54 |
80.69 |
0.11 |
84.71 |
0.19 |
|
|
93.84 |
0.02 |
96.50 |
0.35 |
68.64 |
0.00 |
/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.1233050194 |
| 85.99 |
0.15 |
90.67 |
0.00 |
80.69 |
0.00 |
85.61 |
0.90 |
|
|
93.84 |
0.00 |
96.50 |
0.00 |
68.64 |
0.00 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.205374259 |
| 86.13 |
0.14 |
90.95 |
0.28 |
80.94 |
0.25 |
85.89 |
0.28 |
|
|
93.84 |
0.00 |
96.50 |
0.00 |
68.64 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2692949227 |
| 86.24 |
0.11 |
91.19 |
0.24 |
81.17 |
0.23 |
85.90 |
0.01 |
|
|
94.03 |
0.19 |
96.50 |
0.00 |
68.64 |
0.00 |
/workspace/coverage/default/0.chip_sw_sleep_pin_retention.10534503 |
| 86.33 |
0.09 |
91.21 |
0.02 |
81.24 |
0.07 |
86.17 |
0.27 |
|
|
94.06 |
0.03 |
96.68 |
0.17 |
68.64 |
0.00 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.1329408229 |
| 86.42 |
0.09 |
91.28 |
0.07 |
81.45 |
0.21 |
86.22 |
0.04 |
|
|
94.29 |
0.23 |
96.68 |
0.00 |
68.64 |
0.00 |
/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.571136913 |
| 86.51 |
0.08 |
91.29 |
0.01 |
81.45 |
0.00 |
86.71 |
0.50 |
|
|
94.29 |
0.00 |
96.68 |
0.00 |
68.64 |
0.00 |
/workspace/coverage/default/67.chip_sw_all_escalation_resets.447058406 |
| 86.59 |
0.08 |
91.33 |
0.04 |
81.47 |
0.03 |
86.71 |
0.00 |
|
|
94.32 |
0.03 |
96.85 |
0.17 |
68.86 |
0.22 |
/workspace/coverage/default/24.chip_sw_all_escalation_resets.2071521928 |
| 86.67 |
0.08 |
91.41 |
0.08 |
81.50 |
0.02 |
86.83 |
0.12 |
|
|
94.34 |
0.02 |
96.85 |
0.00 |
69.08 |
0.22 |
/workspace/coverage/default/80.chip_sw_all_escalation_resets.1900647779 |
| 86.74 |
0.07 |
91.42 |
0.01 |
81.53 |
0.03 |
86.83 |
0.00 |
|
|
94.34 |
0.01 |
97.03 |
0.17 |
69.30 |
0.22 |
/workspace/coverage/default/3.chip_sw_all_escalation_resets.1334019453 |
| 86.81 |
0.07 |
91.42 |
0.00 |
81.53 |
0.00 |
87.26 |
0.43 |
|
|
94.34 |
0.00 |
97.03 |
0.00 |
69.30 |
0.00 |
/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.2996635336 |
| 86.88 |
0.07 |
91.42 |
0.01 |
81.54 |
0.01 |
87.27 |
0.01 |
|
|
94.35 |
0.01 |
97.20 |
0.17 |
69.52 |
0.22 |
/workspace/coverage/default/84.chip_sw_all_escalation_resets.316671332 |
| 86.95 |
0.07 |
91.42 |
0.01 |
81.55 |
0.01 |
87.28 |
0.01 |
|
|
94.36 |
0.01 |
97.38 |
0.17 |
69.74 |
0.22 |
/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.3007071698 |
| 87.02 |
0.07 |
91.56 |
0.13 |
81.62 |
0.07 |
87.39 |
0.12 |
|
|
94.43 |
0.07 |
97.38 |
0.00 |
69.74 |
0.00 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.2826293277 |
| 87.08 |
0.06 |
91.56 |
0.00 |
81.62 |
0.00 |
87.55 |
0.16 |
|
|
94.43 |
0.00 |
97.38 |
0.00 |
69.96 |
0.22 |
/workspace/coverage/default/43.chip_sw_all_escalation_resets.1621478813 |
| 87.14 |
0.06 |
91.56 |
0.00 |
81.62 |
0.00 |
87.93 |
0.37 |
|
|
94.43 |
0.00 |
97.38 |
0.00 |
69.96 |
0.00 |
/workspace/coverage/default/2.chip_sw_flash_init.1748694949 |
| 87.20 |
0.06 |
91.56 |
0.00 |
81.78 |
0.16 |
87.93 |
0.00 |
|
|
94.61 |
0.18 |
97.38 |
0.00 |
69.96 |
0.00 |
/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3023554050 |
| 87.25 |
0.05 |
91.56 |
0.00 |
81.85 |
0.07 |
87.93 |
0.00 |
|
|
94.62 |
0.01 |
97.38 |
0.00 |
70.18 |
0.22 |
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.2825504370 |
| 87.30 |
0.04 |
91.56 |
0.00 |
81.85 |
0.00 |
87.97 |
0.05 |
|
|
94.62 |
0.00 |
97.38 |
0.00 |
70.39 |
0.22 |
/workspace/coverage/default/94.chip_sw_all_escalation_resets.3155253028 |
| 87.34 |
0.04 |
91.56 |
0.00 |
81.87 |
0.02 |
87.97 |
0.00 |
|
|
94.64 |
0.02 |
97.38 |
0.00 |
70.61 |
0.22 |
/workspace/coverage/default/7.chip_sw_all_escalation_resets.2003645863 |
| 87.38 |
0.04 |
91.59 |
0.03 |
81.87 |
0.01 |
88.19 |
0.22 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
70.61 |
0.00 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.4148430536 |
| 87.42 |
0.04 |
91.59 |
0.01 |
81.88 |
0.01 |
88.19 |
0.01 |
|
|
94.64 |
0.01 |
97.38 |
0.00 |
70.83 |
0.22 |
/workspace/coverage/default/19.chip_sw_all_escalation_resets.221193861 |
| 87.46 |
0.04 |
91.59 |
0.00 |
81.88 |
0.00 |
88.21 |
0.02 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
71.05 |
0.22 |
/workspace/coverage/default/12.chip_sw_all_escalation_resets.3339095870 |
| 87.50 |
0.04 |
91.59 |
0.00 |
81.88 |
0.00 |
88.44 |
0.23 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
71.05 |
0.00 |
/workspace/coverage/default/1.chip_sw_kmac_entropy.1708004228 |
| 87.54 |
0.04 |
91.59 |
0.00 |
81.88 |
0.00 |
88.45 |
0.01 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
71.27 |
0.22 |
/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.1793788378 |
| 87.57 |
0.04 |
91.59 |
0.00 |
81.88 |
0.00 |
88.46 |
0.01 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
71.49 |
0.22 |
/workspace/coverage/default/89.chip_sw_all_escalation_resets.3274346960 |
| 87.61 |
0.04 |
91.59 |
0.00 |
81.88 |
0.00 |
88.46 |
0.01 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
71.71 |
0.22 |
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.2476558596 |
| 87.65 |
0.04 |
91.59 |
0.00 |
81.89 |
0.01 |
88.46 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
71.93 |
0.22 |
/workspace/coverage/default/10.chip_sw_all_escalation_resets.417689947 |
| 87.69 |
0.04 |
91.59 |
0.00 |
81.89 |
0.01 |
88.46 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
72.15 |
0.22 |
/workspace/coverage/default/17.chip_sw_all_escalation_resets.266823035 |
| 87.72 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.01 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
72.37 |
0.22 |
/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.2845294125 |
| 87.76 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.01 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
72.59 |
0.22 |
/workspace/coverage/default/45.chip_sw_all_escalation_resets.5913495 |
| 87.80 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
72.81 |
0.22 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.1011366064 |
| 87.83 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
73.03 |
0.22 |
/workspace/coverage/default/0.chip_sw_all_escalation_resets.2666797543 |
| 87.87 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
73.25 |
0.22 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.1392681010 |
| 87.91 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
73.46 |
0.22 |
/workspace/coverage/default/1.chip_sw_all_escalation_resets.3979193389 |
| 87.94 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
73.68 |
0.22 |
/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.1836195201 |
| 87.98 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
73.90 |
0.22 |
/workspace/coverage/default/11.chip_sw_all_escalation_resets.227094057 |
| 88.02 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
74.12 |
0.22 |
/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.2614299973 |
| 88.05 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
74.34 |
0.22 |
/workspace/coverage/default/14.chip_sw_all_escalation_resets.370471726 |
| 88.09 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
74.56 |
0.22 |
/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.948070222 |
| 88.13 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
74.78 |
0.22 |
/workspace/coverage/default/15.chip_sw_all_escalation_resets.1824757753 |
| 88.16 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
75.00 |
0.22 |
/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.3189214787 |
| 88.20 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
75.22 |
0.22 |
/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.4147933979 |
| 88.24 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
75.44 |
0.22 |
/workspace/coverage/default/18.chip_sw_all_escalation_resets.3887016208 |
| 88.27 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
75.66 |
0.22 |
/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.4236087461 |
| 88.31 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
75.88 |
0.22 |
/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.702653683 |
| 88.34 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
76.10 |
0.22 |
/workspace/coverage/default/20.chip_sw_all_escalation_resets.124202109 |
| 88.38 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
76.32 |
0.22 |
/workspace/coverage/default/23.chip_sw_all_escalation_resets.3929541245 |
| 88.42 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
76.54 |
0.22 |
/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.2427768478 |
| 88.45 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
76.75 |
0.22 |
/workspace/coverage/default/25.chip_sw_all_escalation_resets.4207435002 |
| 88.49 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
76.97 |
0.22 |
/workspace/coverage/default/26.chip_sw_all_escalation_resets.3734956831 |
| 88.53 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
77.19 |
0.22 |
/workspace/coverage/default/27.chip_sw_all_escalation_resets.428236922 |
| 88.56 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
77.41 |
0.22 |
/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.3115959657 |
| 88.60 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
77.63 |
0.22 |
/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.3024162505 |
| 88.64 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
77.85 |
0.22 |
/workspace/coverage/default/31.chip_sw_all_escalation_resets.3862993682 |
| 88.67 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
78.07 |
0.22 |
/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.3732706229 |
| 88.71 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
78.29 |
0.22 |
/workspace/coverage/default/33.chip_sw_all_escalation_resets.1090546064 |
| 88.75 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
78.51 |
0.22 |
/workspace/coverage/default/34.chip_sw_all_escalation_resets.873950732 |
| 88.78 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
78.73 |
0.22 |
/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.1924739135 |
| 88.82 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
78.95 |
0.22 |
/workspace/coverage/default/37.chip_sw_all_escalation_resets.3855721717 |
| 88.86 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
79.17 |
0.22 |
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.2213519192 |
| 88.89 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
79.39 |
0.22 |
/workspace/coverage/default/39.chip_sw_all_escalation_resets.1407417636 |
| 88.93 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
79.61 |
0.22 |
/workspace/coverage/default/4.chip_sw_all_escalation_resets.2550606098 |
| 88.97 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
79.82 |
0.22 |
/workspace/coverage/default/40.chip_sw_all_escalation_resets.2862688721 |
| 89.00 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
80.04 |
0.22 |
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.1902306188 |
| 89.04 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
80.26 |
0.22 |
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.4188940739 |
| 89.08 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
80.48 |
0.22 |
/workspace/coverage/default/47.chip_sw_all_escalation_resets.807326723 |
| 89.11 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
80.70 |
0.22 |
/workspace/coverage/default/48.chip_sw_all_escalation_resets.841740479 |
| 89.15 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
80.92 |
0.22 |
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.4098376262 |
| 89.19 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
81.14 |
0.22 |
/workspace/coverage/default/49.chip_sw_all_escalation_resets.556110521 |
| 89.22 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
81.36 |
0.22 |
/workspace/coverage/default/5.chip_sw_all_escalation_resets.1402671195 |
| 89.26 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
81.58 |
0.22 |
/workspace/coverage/default/52.chip_sw_all_escalation_resets.3413208831 |
| 89.30 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
81.80 |
0.22 |
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.1626814513 |
| 89.33 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
82.02 |
0.22 |
/workspace/coverage/default/54.chip_sw_all_escalation_resets.1855673189 |
| 89.37 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
82.24 |
0.22 |
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.2265764643 |
| 89.40 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
82.46 |
0.22 |
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.1508109948 |
| 89.44 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
82.68 |
0.22 |
/workspace/coverage/default/59.chip_sw_all_escalation_resets.3112069070 |
| 89.48 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
82.89 |
0.22 |
/workspace/coverage/default/61.chip_sw_all_escalation_resets.1318257593 |
| 89.51 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
83.11 |
0.22 |
/workspace/coverage/default/64.chip_sw_all_escalation_resets.1377720305 |
| 89.55 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
83.33 |
0.22 |
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.1196512145 |
| 89.59 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
83.55 |
0.22 |
/workspace/coverage/default/69.chip_sw_all_escalation_resets.1125875542 |
| 89.62 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
83.77 |
0.22 |
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3627950847 |
| 89.66 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
83.99 |
0.22 |
/workspace/coverage/default/70.chip_sw_all_escalation_resets.2930137318 |
| 89.70 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
84.21 |
0.22 |
/workspace/coverage/default/78.chip_sw_all_escalation_resets.675244550 |
| 89.73 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
84.43 |
0.22 |
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2166937657 |
| 89.77 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
84.65 |
0.22 |
/workspace/coverage/default/79.chip_sw_all_escalation_resets.3330391496 |
| 89.81 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
84.87 |
0.22 |
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.794709132 |
| 89.84 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
85.09 |
0.22 |
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3287448020 |
| 89.88 |
0.04 |
91.59 |
0.00 |
81.89 |
0.00 |
88.47 |
0.00 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
85.31 |
0.22 |
/workspace/coverage/default/9.chip_sw_all_escalation_resets.998341023 |
| 89.91 |
0.03 |
91.59 |
0.00 |
81.89 |
0.00 |
88.66 |
0.20 |
|
|
94.64 |
0.00 |
97.38 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.3843067753 |
| 89.94 |
0.03 |
91.59 |
0.00 |
81.89 |
0.00 |
88.66 |
0.00 |
|
|
94.64 |
0.00 |
97.55 |
0.17 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_data_integrity_escalation.2871024537 |
| 89.97 |
0.03 |
91.65 |
0.06 |
81.94 |
0.05 |
88.67 |
0.01 |
|
|
94.70 |
0.06 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_plic_sw_irq.927227567 |
| 90.00 |
0.03 |
91.68 |
0.03 |
81.99 |
0.05 |
88.74 |
0.06 |
|
|
94.73 |
0.02 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.2607130123 |
| 90.02 |
0.03 |
91.68 |
0.00 |
81.99 |
0.00 |
88.89 |
0.16 |
|
|
94.73 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.1581951420 |
| 90.05 |
0.03 |
91.68 |
0.00 |
81.99 |
0.00 |
89.05 |
0.15 |
|
|
94.73 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.3147311699 |
| 90.07 |
0.02 |
91.68 |
0.00 |
82.13 |
0.15 |
89.05 |
0.00 |
|
|
94.73 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/1.chip_plic_all_irqs_0.1998922770 |
| 90.10 |
0.02 |
91.73 |
0.05 |
82.20 |
0.06 |
89.05 |
0.01 |
|
|
94.74 |
0.02 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/1.chip_sw_sleep_pin_wake.1864887797 |
| 90.12 |
0.02 |
91.80 |
0.07 |
82.20 |
0.00 |
89.10 |
0.05 |
|
|
94.75 |
0.01 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/3.chip_tap_straps_rma.522659319 |
| 90.14 |
0.02 |
91.91 |
0.11 |
82.21 |
0.01 |
89.10 |
0.01 |
|
|
94.76 |
0.01 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.2131075415 |
| 90.16 |
0.02 |
91.92 |
0.01 |
82.24 |
0.03 |
89.17 |
0.06 |
|
|
94.77 |
0.02 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_usbdev_pincfg.3950665566 |
| 90.18 |
0.02 |
91.92 |
0.00 |
82.36 |
0.12 |
89.17 |
0.00 |
|
|
94.77 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_plic_all_irqs_20.911355233 |
| 90.20 |
0.02 |
91.96 |
0.04 |
82.37 |
0.01 |
89.19 |
0.03 |
|
|
94.79 |
0.02 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.4270013388 |
| 90.21 |
0.01 |
91.96 |
0.01 |
82.39 |
0.02 |
89.25 |
0.06 |
|
|
94.79 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1513365123 |
| 90.22 |
0.01 |
92.03 |
0.07 |
82.40 |
0.01 |
89.26 |
0.01 |
|
|
94.79 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1437229912 |
| 90.23 |
0.01 |
92.03 |
0.00 |
82.40 |
0.01 |
89.33 |
0.07 |
|
|
94.79 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_jtag_csr_rw.3635235682 |
| 90.25 |
0.01 |
92.05 |
0.02 |
82.42 |
0.02 |
89.34 |
0.01 |
|
|
94.81 |
0.02 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/21.chip_sw_all_escalation_resets.2180355760 |
| 90.26 |
0.01 |
92.05 |
0.00 |
82.42 |
0.00 |
89.41 |
0.07 |
|
|
94.81 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.1089541668 |
| 90.27 |
0.01 |
92.05 |
0.00 |
82.48 |
0.07 |
89.41 |
0.00 |
|
|
94.81 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_plic_all_irqs_0.130430216 |
| 90.28 |
0.01 |
92.05 |
0.00 |
82.48 |
0.00 |
89.47 |
0.07 |
|
|
94.81 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.1260497 |
| 90.29 |
0.01 |
92.05 |
0.00 |
82.49 |
0.01 |
89.53 |
0.06 |
|
|
94.81 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.4219797813 |
| 90.30 |
0.01 |
92.05 |
0.00 |
82.50 |
0.01 |
89.57 |
0.04 |
|
|
94.81 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.2197657151 |
| 90.31 |
0.01 |
92.08 |
0.02 |
82.51 |
0.01 |
89.58 |
0.01 |
|
|
94.83 |
0.02 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1921701205 |
| 90.32 |
0.01 |
92.10 |
0.02 |
82.52 |
0.01 |
89.59 |
0.01 |
|
|
94.85 |
0.02 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.1958787256 |
| 90.33 |
0.01 |
92.10 |
0.00 |
82.52 |
0.00 |
89.63 |
0.05 |
|
|
94.85 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.226366054 |
| 90.33 |
0.01 |
92.10 |
0.00 |
82.56 |
0.04 |
89.63 |
0.00 |
|
|
94.85 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/1.chip_plic_all_irqs_10.2747512555 |
| 90.34 |
0.01 |
92.10 |
0.00 |
82.60 |
0.04 |
89.63 |
0.00 |
|
|
94.85 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/1.chip_plic_all_irqs_20.3677500910 |
| 90.35 |
0.01 |
92.11 |
0.01 |
82.61 |
0.01 |
89.65 |
0.02 |
|
|
94.85 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.579320929 |
| 90.35 |
0.01 |
92.11 |
0.00 |
82.62 |
0.01 |
89.68 |
0.03 |
|
|
94.85 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.4202767035 |
| 90.36 |
0.01 |
92.14 |
0.03 |
82.63 |
0.01 |
89.68 |
0.00 |
|
|
94.85 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_spi_device_tpm.579493791 |
| 90.37 |
0.01 |
92.14 |
0.00 |
82.63 |
0.00 |
89.72 |
0.04 |
|
|
94.85 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.1819666390 |
| 90.37 |
0.01 |
92.15 |
0.01 |
82.65 |
0.02 |
89.73 |
0.01 |
|
|
94.85 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.1140336103 |
| 90.38 |
0.01 |
92.15 |
0.00 |
82.67 |
0.02 |
89.74 |
0.01 |
|
|
94.85 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1497100534 |
| 90.38 |
0.01 |
92.15 |
0.00 |
82.67 |
0.00 |
89.77 |
0.03 |
|
|
94.85 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1741671826 |
| 90.39 |
0.01 |
92.15 |
0.00 |
82.67 |
0.00 |
89.80 |
0.03 |
|
|
94.85 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.1344927229 |
| 90.39 |
0.01 |
92.15 |
0.01 |
82.68 |
0.01 |
89.80 |
0.01 |
|
|
94.85 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3400191649 |
| 90.39 |
0.01 |
92.15 |
0.00 |
82.68 |
0.00 |
89.82 |
0.01 |
|
|
94.86 |
0.01 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.3892795016 |
| 90.40 |
0.01 |
92.15 |
0.00 |
82.71 |
0.02 |
89.82 |
0.00 |
|
|
94.86 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/2.chip_plic_all_irqs_10.4216156415 |
| 90.40 |
0.01 |
92.15 |
0.00 |
82.71 |
0.00 |
89.84 |
0.02 |
|
|
94.86 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.3550959125 |
| 90.41 |
0.01 |
92.15 |
0.00 |
82.71 |
0.00 |
89.86 |
0.02 |
|
|
94.86 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.2019448681 |
| 90.41 |
0.01 |
92.15 |
0.00 |
82.71 |
0.00 |
89.88 |
0.02 |
|
|
94.86 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.4124613935 |
| 90.41 |
0.01 |
92.16 |
0.01 |
82.71 |
0.01 |
89.88 |
0.01 |
|
|
94.86 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.393675452 |
| 90.41 |
0.01 |
92.16 |
0.01 |
82.72 |
0.01 |
89.89 |
0.01 |
|
|
94.86 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.2709473125 |
| 90.42 |
0.01 |
92.16 |
0.00 |
82.74 |
0.02 |
89.89 |
0.00 |
|
|
94.86 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.1764523956 |
| 90.42 |
0.01 |
92.16 |
0.00 |
82.76 |
0.02 |
89.89 |
0.00 |
|
|
94.86 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.1122108721 |
| 90.42 |
0.01 |
92.16 |
0.00 |
82.76 |
0.00 |
89.91 |
0.02 |
|
|
94.86 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.1789460308 |
| 90.43 |
0.01 |
92.17 |
0.01 |
82.76 |
0.01 |
89.91 |
0.01 |
|
|
94.86 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_pattgen_ios.331721881 |
| 90.43 |
0.01 |
92.18 |
0.01 |
82.76 |
0.01 |
89.91 |
0.00 |
|
|
94.86 |
0.01 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_sleep_pin_wake.4290361273 |
| 90.43 |
0.01 |
92.18 |
0.00 |
82.78 |
0.01 |
89.91 |
0.00 |
|
|
94.86 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_gpio.3029264500 |
| 90.43 |
0.01 |
92.18 |
0.00 |
82.78 |
0.00 |
89.92 |
0.01 |
|
|
94.86 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_jtag_mem_access.1492877793 |
| 90.44 |
0.01 |
92.18 |
0.00 |
82.78 |
0.00 |
89.94 |
0.01 |
|
|
94.86 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.905707214 |
| 90.44 |
0.01 |
92.18 |
0.00 |
82.79 |
0.01 |
89.94 |
0.01 |
|
|
94.86 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/1.chip_sw_entropy_src_csrng.1025521183 |
| 90.44 |
0.01 |
92.18 |
0.00 |
82.79 |
0.00 |
89.95 |
0.01 |
|
|
94.86 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_edn_boot_mode.2849791477 |
| 90.44 |
0.01 |
92.18 |
0.01 |
82.79 |
0.00 |
89.96 |
0.01 |
|
|
94.86 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1214313176 |
| 90.44 |
0.01 |
92.18 |
0.00 |
82.80 |
0.01 |
89.96 |
0.00 |
|
|
94.86 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1940990416 |
| 90.44 |
0.01 |
92.19 |
0.01 |
82.80 |
0.00 |
89.96 |
0.01 |
|
|
94.86 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.3734791585 |
| 90.45 |
0.01 |
92.19 |
0.00 |
82.80 |
0.01 |
89.97 |
0.01 |
|
|
94.86 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/1.chip_sw_power_sleep_load.4173032040 |
| 90.45 |
0.01 |
92.19 |
0.00 |
82.80 |
0.00 |
89.98 |
0.01 |
|
|
94.86 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.2188662696 |
| 90.45 |
0.01 |
92.19 |
0.00 |
82.80 |
0.00 |
89.98 |
0.01 |
|
|
94.86 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.1027445533 |
| 90.45 |
0.01 |
92.19 |
0.00 |
82.80 |
0.00 |
89.99 |
0.01 |
|
|
94.86 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.1317700997 |
| 90.45 |
0.01 |
92.19 |
0.00 |
82.80 |
0.00 |
89.99 |
0.00 |
|
|
94.87 |
0.01 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/1.chip_tap_straps_dev.3124984229 |
| 90.45 |
0.01 |
92.19 |
0.00 |
82.81 |
0.01 |
89.99 |
0.00 |
|
|
94.87 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.1931541403 |
| 90.45 |
0.01 |
92.19 |
0.00 |
82.82 |
0.01 |
89.99 |
0.00 |
|
|
94.87 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/1.chip_sw_sleep_pin_retention.3321047864 |
| 90.46 |
0.01 |
92.19 |
0.00 |
82.83 |
0.01 |
89.99 |
0.00 |
|
|
94.87 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/2.chip_sw_gpio.3168635938 |
| 90.46 |
0.01 |
92.19 |
0.00 |
82.83 |
0.00 |
90.00 |
0.01 |
|
|
94.87 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2895250661 |
| 90.46 |
0.01 |
92.19 |
0.00 |
82.83 |
0.00 |
90.01 |
0.01 |
|
|
94.87 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.rom_e2e_jtag_inject_dev.2043133568 |
| 90.46 |
0.01 |
92.19 |
0.01 |
82.83 |
0.00 |
90.01 |
0.01 |
|
|
94.87 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/2.chip_sw_pattgen_ios.2911519279 |
| 90.46 |
0.01 |
92.19 |
0.00 |
82.83 |
0.00 |
90.01 |
0.01 |
|
|
94.87 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_hmac_enc.3832650444 |
| 90.46 |
0.01 |
92.19 |
0.00 |
82.83 |
0.00 |
90.02 |
0.01 |
|
|
94.87 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2203263357 |
| 90.46 |
0.01 |
92.19 |
0.00 |
82.83 |
0.00 |
90.02 |
0.01 |
|
|
94.87 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.3231334861 |
| 90.46 |
0.01 |
92.19 |
0.00 |
82.83 |
0.00 |
90.03 |
0.01 |
|
|
94.87 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_power_sleep_load.142001579 |
| 90.46 |
0.01 |
92.19 |
0.00 |
82.83 |
0.00 |
90.03 |
0.01 |
|
|
94.87 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1594437398 |
| 90.46 |
0.01 |
92.19 |
0.00 |
82.83 |
0.00 |
90.04 |
0.01 |
|
|
94.87 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.1717396319 |
| 90.46 |
0.01 |
92.19 |
0.00 |
82.83 |
0.00 |
90.04 |
0.01 |
|
|
94.87 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/1.chip_sw_flash_init.2950209471 |
| 90.47 |
0.01 |
92.19 |
0.00 |
82.83 |
0.01 |
90.04 |
0.00 |
|
|
94.87 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.3965250332 |
| 90.47 |
0.01 |
92.19 |
0.00 |
82.83 |
0.01 |
90.04 |
0.00 |
|
|
94.87 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.158150200 |
| 90.47 |
0.01 |
92.19 |
0.00 |
82.83 |
0.00 |
90.05 |
0.01 |
|
|
94.87 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.4155494659 |
| 90.47 |
0.01 |
92.19 |
0.00 |
82.83 |
0.00 |
90.05 |
0.01 |
|
|
94.87 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.1011272035 |
| 90.47 |
0.01 |
92.19 |
0.00 |
82.83 |
0.00 |
90.05 |
0.01 |
|
|
94.87 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.3619087192 |
| 90.47 |
0.01 |
92.19 |
0.00 |
82.83 |
0.00 |
90.05 |
0.01 |
|
|
94.87 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.3808109815 |
| 90.47 |
0.01 |
92.19 |
0.00 |
82.83 |
0.00 |
90.05 |
0.01 |
|
|
94.87 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1498178538 |
| 90.47 |
0.01 |
92.19 |
0.00 |
82.83 |
0.00 |
90.06 |
0.01 |
|
|
94.87 |
0.00 |
97.55 |
0.00 |
85.31 |
0.00 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.4276356887 |
| Name |
| /workspace/coverage/default/0.chip_sival_flash_info_access.1136067912 |
| /workspace/coverage/default/0.chip_sw_aes_enc.2335212978 |
| /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.2432957532 |
| /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.2836740875 |
| /workspace/coverage/default/0.chip_sw_aes_entropy.4041234948 |
| /workspace/coverage/default/0.chip_sw_aes_idle.4123447898 |
| /workspace/coverage/default/0.chip_sw_aes_masking_off.2461908041 |
| /workspace/coverage/default/0.chip_sw_aes_smoketest.3730307777 |
| /workspace/coverage/default/0.chip_sw_alert_handler_entropy.2026251067 |
| /workspace/coverage/default/0.chip_sw_alert_handler_escalation.1756692080 |
| /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.565580685 |
| /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.148362886 |
| /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.3124425901 |
| /workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.1658239581 |
| /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.4242763627 |
| /workspace/coverage/default/0.chip_sw_alert_test.2337945752 |
| /workspace/coverage/default/0.chip_sw_aon_timer_irq.234414111 |
| /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.1742785568 |
| /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.2780536859 |
| /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.3517341981 |
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| /workspace/coverage/default/62.chip_sw_all_escalation_resets.1195704340 |
| /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.1790005502 |
| /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.1722249584 |
| /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.3325206169 |
| /workspace/coverage/default/65.chip_sw_all_escalation_resets.461753576 |
| /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.4059217088 |
| /workspace/coverage/default/66.chip_sw_all_escalation_resets.4093620974 |
| /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1926364830 |
| /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.3309593693 |
| /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2431743322 |
| /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.4050228539 |
| /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.948923804 |
| /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.3656496606 |
| /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.3250913500 |
| /workspace/coverage/default/71.chip_sw_all_escalation_resets.1493998550 |
| /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3495254330 |
| /workspace/coverage/default/72.chip_sw_all_escalation_resets.2498254023 |
| /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.2065340237 |
| /workspace/coverage/default/73.chip_sw_all_escalation_resets.1165127946 |
| /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.3358526934 |
| /workspace/coverage/default/74.chip_sw_all_escalation_resets.2213113126 |
| /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.733215926 |
| /workspace/coverage/default/75.chip_sw_all_escalation_resets.891173287 |
| /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.1197770897 |
| /workspace/coverage/default/76.chip_sw_all_escalation_resets.2954486443 |
| /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.3771327730 |
| /workspace/coverage/default/77.chip_sw_all_escalation_resets.857764935 |
| /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3722540948 |
| /workspace/coverage/default/8.chip_sw_all_escalation_resets.3952845242 |
| /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.2364038002 |
| /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1133534104 |
| /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.2727505043 |
| /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.2206724034 |
| /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.2038661379 |
| /workspace/coverage/default/81.chip_sw_all_escalation_resets.460491950 |
| /workspace/coverage/default/82.chip_sw_all_escalation_resets.2266083865 |
| /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1521879452 |
| /workspace/coverage/default/83.chip_sw_all_escalation_resets.2891441675 |
| /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.3233344041 |
| /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.1208980247 |
| /workspace/coverage/default/85.chip_sw_all_escalation_resets.1259511563 |
| /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.1477661563 |
| /workspace/coverage/default/86.chip_sw_all_escalation_resets.1367522105 |
| /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.4111584989 |
| /workspace/coverage/default/87.chip_sw_all_escalation_resets.1207702744 |
| /workspace/coverage/default/88.chip_sw_all_escalation_resets.1506857850 |
| /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.329637946 |
| /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.1232011098 |
| /workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.2183456767 |
| /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.479561697 |
| /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.651756744 |
| /workspace/coverage/default/90.chip_sw_all_escalation_resets.3984646295 |
| /workspace/coverage/default/91.chip_sw_all_escalation_resets.2404123462 |
| /workspace/coverage/default/92.chip_sw_all_escalation_resets.3947572430 |
| /workspace/coverage/default/93.chip_sw_all_escalation_resets.1849548942 |
| /workspace/coverage/default/95.chip_sw_all_escalation_resets.58196793 |
| /workspace/coverage/default/96.chip_sw_all_escalation_resets.2687239494 |
| /workspace/coverage/default/97.chip_sw_all_escalation_resets.1484425540 |
| /workspace/coverage/default/98.chip_sw_all_escalation_resets.1081749616 |
| /workspace/coverage/default/99.chip_sw_all_escalation_resets.2575788511 |
| /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.1161616707 |
| /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.239407007 |
| /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.2394387384 |
| /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.539994271 |
| /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.3208144006 |
| /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.3522921108 |
| /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.1803871764 |
| /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.104823513 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
| T4 |
/workspace/coverage/default/1.chip_sw_example_flash.3914057812 |
|
|
Jun 13 03:39:42 PM PDT 24 |
Jun 13 03:44:20 PM PDT 24 |
3162935504 ps |
| T5 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.3674823012 |
|
|
Jun 13 03:44:25 PM PDT 24 |
Jun 13 04:50:33 PM PDT 24 |
14938495064 ps |
| T6 |
/workspace/coverage/default/0.chip_sw_usbdev_pullup.3349252042 |
|
|
Jun 13 03:35:21 PM PDT 24 |
Jun 13 03:40:13 PM PDT 24 |
2810391832 ps |
| T54 |
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.335524233 |
|
|
Jun 13 04:07:31 PM PDT 24 |
Jun 13 04:59:18 PM PDT 24 |
14874148818 ps |
| T42 |
/workspace/coverage/default/1.chip_sw_aes_idle.1246768912 |
|
|
Jun 13 03:47:50 PM PDT 24 |
Jun 13 03:52:07 PM PDT 24 |
2813961188 ps |
| T19 |
/workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.2019448681 |
|
|
Jun 13 03:45:59 PM PDT 24 |
Jun 13 03:54:49 PM PDT 24 |
9786199591 ps |
| T20 |
/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.152347801 |
|
|
Jun 13 03:39:35 PM PDT 24 |
Jun 13 06:49:12 PM PDT 24 |
58042289096 ps |
| T41 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.1671178314 |
|
|
Jun 13 03:59:03 PM PDT 24 |
Jun 13 04:35:41 PM PDT 24 |
12834120568 ps |
| T85 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_req.4036597764 |
|
|
Jun 13 03:56:33 PM PDT 24 |
Jun 13 04:05:08 PM PDT 24 |
4177270584 ps |
| T16 |
/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.1053882651 |
|
|
Jun 13 03:41:04 PM PDT 24 |
Jun 13 03:46:15 PM PDT 24 |
3799677486 ps |
| T83 |
/workspace/coverage/default/1.chip_sw_edn_sw_mode.2262053971 |
|
|
Jun 13 03:44:06 PM PDT 24 |
Jun 13 04:15:23 PM PDT 24 |
9205905000 ps |
| T58 |
/workspace/coverage/default/2.chip_tap_straps_dev.4073618284 |
|
|
Jun 13 04:02:35 PM PDT 24 |
Jun 13 04:08:18 PM PDT 24 |
4004041849 ps |
| T17 |
/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.579320929 |
|
|
Jun 13 03:54:00 PM PDT 24 |
Jun 13 04:37:38 PM PDT 24 |
13029561968 ps |
| T59 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2557655608 |
|
|
Jun 13 03:39:20 PM PDT 24 |
Jun 13 03:50:47 PM PDT 24 |
3633205544 ps |
| T18 |
/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.1793788378 |
|
|
Jun 13 04:09:19 PM PDT 24 |
Jun 13 04:16:00 PM PDT 24 |
3565978888 ps |
| T112 |
/workspace/coverage/default/63.chip_sw_all_escalation_resets.3131941705 |
|
|
Jun 13 04:13:31 PM PDT 24 |
Jun 13 04:22:52 PM PDT 24 |
6062378740 ps |
| T131 |
/workspace/coverage/default/94.chip_sw_all_escalation_resets.3155253028 |
|
|
Jun 13 04:17:49 PM PDT 24 |
Jun 13 04:27:27 PM PDT 24 |
5261358716 ps |
| T88 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.65693800 |
|
|
Jun 13 03:59:53 PM PDT 24 |
Jun 13 04:14:12 PM PDT 24 |
9548717664 ps |
| T192 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.487582970 |
|
|
Jun 13 03:54:54 PM PDT 24 |
Jun 13 04:00:03 PM PDT 24 |
2825001919 ps |
| T136 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.558743391 |
|
|
Jun 13 03:39:37 PM PDT 24 |
Jun 13 03:46:25 PM PDT 24 |
3504961892 ps |
| T56 |
/workspace/coverage/default/4.chip_tap_straps_rma.3681290408 |
|
|
Jun 13 04:05:53 PM PDT 24 |
Jun 13 04:16:09 PM PDT 24 |
6641732922 ps |
| T21 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.2203079198 |
|
|
Jun 13 03:54:56 PM PDT 24 |
Jun 13 07:42:15 PM PDT 24 |
77793780701 ps |
| T243 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.4270013388 |
|
|
Jun 13 03:42:34 PM PDT 24 |
Jun 13 04:05:24 PM PDT 24 |
7819615114 ps |
| T101 |
/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.83475595 |
|
|
Jun 13 04:09:45 PM PDT 24 |
Jun 13 04:21:08 PM PDT 24 |
4141905168 ps |
| T66 |
/workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.3704062048 |
|
|
Jun 13 03:43:06 PM PDT 24 |
Jun 13 03:51:07 PM PDT 24 |
6509059720 ps |
| T271 |
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.2476558596 |
|
|
Jun 13 04:08:17 PM PDT 24 |
Jun 13 04:17:08 PM PDT 24 |
3844546624 ps |
| T55 |
/workspace/coverage/default/0.rom_e2e_asm_init_prod_end.3814268030 |
|
|
Jun 13 03:45:45 PM PDT 24 |
Jun 13 04:44:43 PM PDT 24 |
13829269080 ps |
| T28 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.2607130123 |
|
|
Jun 13 03:53:18 PM PDT 24 |
Jun 13 04:05:29 PM PDT 24 |
4339165520 ps |
| T57 |
/workspace/coverage/default/10.chip_sw_lc_ctrl_transition.1937310805 |
|
|
Jun 13 04:07:03 PM PDT 24 |
Jun 13 04:19:06 PM PDT 24 |
11623385988 ps |
| T117 |
/workspace/coverage/default/80.chip_sw_all_escalation_resets.1900647779 |
|
|
Jun 13 04:15:37 PM PDT 24 |
Jun 13 04:25:23 PM PDT 24 |
4815389440 ps |
| T142 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.3647327372 |
|
|
Jun 13 03:55:39 PM PDT 24 |
Jun 13 04:17:55 PM PDT 24 |
8884799630 ps |
| T272 |
/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.1122470516 |
|
|
Jun 13 04:05:39 PM PDT 24 |
Jun 13 04:12:46 PM PDT 24 |
4094049068 ps |
| T223 |
/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.2845294125 |
|
|
Jun 13 04:09:14 PM PDT 24 |
Jun 13 04:15:01 PM PDT 24 |
4375621828 ps |
| T84 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.2585546682 |
|
|
Jun 13 03:59:12 PM PDT 24 |
Jun 13 05:32:12 PM PDT 24 |
24659993760 ps |
| T67 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.134956776 |
|
|
Jun 13 03:57:48 PM PDT 24 |
Jun 13 04:27:44 PM PDT 24 |
19597945472 ps |
| T104 |
/workspace/coverage/default/2.chip_sw_alert_handler_entropy.2109795733 |
|
|
Jun 13 03:57:36 PM PDT 24 |
Jun 13 04:04:58 PM PDT 24 |
3617459158 ps |
| T297 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.3965250332 |
|
|
Jun 13 03:36:48 PM PDT 24 |
Jun 13 03:52:35 PM PDT 24 |
4736723712 ps |
| T123 |
/workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.3904491530 |
|
|
Jun 13 03:45:16 PM PDT 24 |
Jun 13 03:49:32 PM PDT 24 |
3235292106 ps |
| T29 |
/workspace/coverage/default/1.chip_sw_gpio.1639669541 |
|
|
Jun 13 03:41:23 PM PDT 24 |
Jun 13 03:49:43 PM PDT 24 |
3613619576 ps |
| T224 |
/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.2427768478 |
|
|
Jun 13 04:10:23 PM PDT 24 |
Jun 13 04:18:04 PM PDT 24 |
4019653440 ps |
| T193 |
/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.526857529 |
|
|
Jun 13 03:57:55 PM PDT 24 |
Jun 13 04:07:57 PM PDT 24 |
5624293560 ps |
| T105 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.148362886 |
|
|
Jun 13 03:37:40 PM PDT 24 |
Jun 13 04:04:30 PM PDT 24 |
7510383616 ps |
| T132 |
/workspace/coverage/default/46.chip_sw_all_escalation_resets.435535581 |
|
|
Jun 13 04:14:14 PM PDT 24 |
Jun 13 04:26:20 PM PDT 24 |
6278443516 ps |
| T147 |
/workspace/coverage/default/89.chip_sw_all_escalation_resets.3274346960 |
|
|
Jun 13 04:15:33 PM PDT 24 |
Jun 13 04:23:59 PM PDT 24 |
6205950832 ps |
| T1 |
/workspace/coverage/default/0.chip_sw_sleep_pin_retention.10534503 |
|
|
Jun 13 03:37:39 PM PDT 24 |
Jun 13 03:43:48 PM PDT 24 |
3993368856 ps |
| T62 |
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.948923804 |
|
|
Jun 13 04:07:26 PM PDT 24 |
Jun 13 04:19:20 PM PDT 24 |
10071021847 ps |
| T178 |
/workspace/coverage/default/0.chip_sw_example_manufacturer.451306992 |
|
|
Jun 13 03:38:26 PM PDT 24 |
Jun 13 03:42:49 PM PDT 24 |
2926319678 ps |
| T75 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.21439770 |
|
|
Jun 13 04:00:41 PM PDT 24 |
Jun 13 04:15:12 PM PDT 24 |
3969698870 ps |
| T144 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.393938454 |
|
|
Jun 13 03:35:49 PM PDT 24 |
Jun 13 03:55:37 PM PDT 24 |
6483223020 ps |
| T179 |
/workspace/coverage/default/1.chip_sw_otbn_smoketest.2729580546 |
|
|
Jun 13 03:53:35 PM PDT 24 |
Jun 13 04:31:27 PM PDT 24 |
10028141850 ps |
| T145 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.841658411 |
|
|
Jun 13 03:55:16 PM PDT 24 |
Jun 13 04:16:26 PM PDT 24 |
6857070160 ps |
| T137 |
/workspace/coverage/default/2.chip_sw_hmac_enc.1949707560 |
|
|
Jun 13 04:01:15 PM PDT 24 |
Jun 13 04:06:46 PM PDT 24 |
2458962472 ps |
| T180 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.3171233115 |
|
|
Jun 13 03:36:57 PM PDT 24 |
Jun 13 03:47:48 PM PDT 24 |
7576820925 ps |
| T68 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.3664844048 |
|
|
Jun 13 03:58:50 PM PDT 24 |
Jun 13 04:18:54 PM PDT 24 |
11953966580 ps |
| T359 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.156152645 |
|
|
Jun 13 03:46:32 PM PDT 24 |
Jun 13 04:49:20 PM PDT 24 |
43028761352 ps |
| T264 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.1122108721 |
|
|
Jun 13 03:57:26 PM PDT 24 |
Jun 13 04:08:53 PM PDT 24 |
4042737180 ps |
| T102 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.3362718793 |
|
|
Jun 13 03:45:23 PM PDT 24 |
Jun 13 05:17:48 PM PDT 24 |
49893844822 ps |
| T267 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx.3924212230 |
|
|
Jun 13 04:04:44 PM PDT 24 |
Jun 13 04:14:31 PM PDT 24 |
4145372014 ps |
| T376 |
/workspace/coverage/default/45.chip_sw_all_escalation_resets.5913495 |
|
|
Jun 13 04:11:36 PM PDT 24 |
Jun 13 04:20:25 PM PDT 24 |
4844445720 ps |
| T369 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.2358727088 |
|
|
Jun 13 03:55:53 PM PDT 24 |
Jun 13 04:01:29 PM PDT 24 |
2733611064 ps |
| T115 |
/workspace/coverage/default/3.chip_sw_data_integrity_escalation.182306928 |
|
|
Jun 13 04:04:43 PM PDT 24 |
Jun 13 04:18:08 PM PDT 24 |
6201494096 ps |
| T325 |
/workspace/coverage/default/65.chip_sw_all_escalation_resets.461753576 |
|
|
Jun 13 04:18:18 PM PDT 24 |
Jun 13 04:26:30 PM PDT 24 |
5007096606 ps |
| T265 |
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3287448020 |
|
|
Jun 13 04:17:21 PM PDT 24 |
Jun 13 04:23:32 PM PDT 24 |
3180423192 ps |
| T63 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_status.3424485824 |
|
|
Jun 13 03:48:48 PM PDT 24 |
Jun 13 03:54:47 PM PDT 24 |
3093491777 ps |
| T326 |
/workspace/coverage/default/10.chip_sw_all_escalation_resets.417689947 |
|
|
Jun 13 04:08:38 PM PDT 24 |
Jun 13 04:21:56 PM PDT 24 |
5596062120 ps |
| T140 |
/workspace/coverage/default/1.chip_sw_kmac_entropy.1708004228 |
|
|
Jun 13 03:42:05 PM PDT 24 |
Jun 13 03:48:40 PM PDT 24 |
3745522520 ps |
| T283 |
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.1722249584 |
|
|
Jun 13 04:14:27 PM PDT 24 |
Jun 13 04:20:16 PM PDT 24 |
3565094936 ps |
| T327 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.1392681010 |
|
|
Jun 13 03:44:12 PM PDT 24 |
Jun 13 03:50:11 PM PDT 24 |
3730969138 ps |
| T328 |
/workspace/coverage/default/1.chip_sw_rstmgr_smoketest.118701307 |
|
|
Jun 13 03:52:07 PM PDT 24 |
Jun 13 03:56:54 PM PDT 24 |
3220083840 ps |
| T204 |
/workspace/coverage/default/14.chip_sw_lc_ctrl_transition.775830649 |
|
|
Jun 13 04:09:48 PM PDT 24 |
Jun 13 04:17:26 PM PDT 24 |
6551173093 ps |
| T346 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.4020745656 |
|
|
Jun 13 03:41:01 PM PDT 24 |
Jun 13 04:02:40 PM PDT 24 |
8076875826 ps |
| T146 |
/workspace/coverage/default/2.chip_sw_edn_sw_mode.145469934 |
|
|
Jun 13 03:59:48 PM PDT 24 |
Jun 13 04:26:57 PM PDT 24 |
6981206600 ps |
| T51 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.775513663 |
|
|
Jun 13 03:45:27 PM PDT 24 |
Jun 13 05:16:17 PM PDT 24 |
22161318277 ps |
| T25 |
/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.1123199469 |
|
|
Jun 13 03:36:14 PM PDT 24 |
Jun 13 03:40:59 PM PDT 24 |
2475050748 ps |
| T422 |
/workspace/coverage/default/0.rom_e2e_smoke.130690000 |
|
|
Jun 13 03:43:45 PM PDT 24 |
Jun 13 04:41:34 PM PDT 24 |
14506485080 ps |
| T559 |
/workspace/coverage/default/2.chip_sw_example_concurrency.650304786 |
|
|
Jun 13 03:54:04 PM PDT 24 |
Jun 13 03:58:52 PM PDT 24 |
3564779180 ps |
| T184 |
/workspace/coverage/default/19.chip_sw_all_escalation_resets.221193861 |
|
|
Jun 13 04:08:48 PM PDT 24 |
Jun 13 04:19:27 PM PDT 24 |
5582879410 ps |
| T161 |
/workspace/coverage/default/1.chip_tap_straps_dev.3124984229 |
|
|
Jun 13 03:49:40 PM PDT 24 |
Jun 13 04:21:49 PM PDT 24 |
16911402804 ps |
| T560 |
/workspace/coverage/default/0.chip_sw_aon_timer_smoketest.2780536859 |
|
|
Jun 13 03:41:53 PM PDT 24 |
Jun 13 03:45:55 PM PDT 24 |
2729206628 ps |
| T347 |
/workspace/coverage/default/43.chip_sw_all_escalation_resets.1621478813 |
|
|
Jun 13 04:11:58 PM PDT 24 |
Jun 13 04:23:02 PM PDT 24 |
4687036480 ps |
| T236 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.3495322336 |
|
|
Jun 13 04:00:27 PM PDT 24 |
Jun 13 04:09:11 PM PDT 24 |
5556070082 ps |
| T268 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.784341030 |
|
|
Jun 13 04:05:34 PM PDT 24 |
Jun 13 04:16:29 PM PDT 24 |
4356378100 ps |
| T211 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod_end.4165638101 |
|
|
Jun 13 03:59:46 PM PDT 24 |
Jun 13 04:54:44 PM PDT 24 |
13914929112 ps |
| T199 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.205374259 |
|
|
Jun 13 03:38:09 PM PDT 24 |
Jun 13 05:24:03 PM PDT 24 |
47263378324 ps |
| T284 |
/workspace/coverage/default/2.chip_sw_otbn_mem_scramble.437316160 |
|
|
Jun 13 03:58:34 PM PDT 24 |
Jun 13 04:05:18 PM PDT 24 |
3520821880 ps |
| T420 |
/workspace/coverage/default/97.chip_sw_all_escalation_resets.1484425540 |
|
|
Jun 13 04:17:13 PM PDT 24 |
Jun 13 04:26:34 PM PDT 24 |
5507267112 ps |
| T98 |
/workspace/coverage/default/4.chip_tap_straps_testunlock0.3789668958 |
|
|
Jun 13 04:06:04 PM PDT 24 |
Jun 13 04:21:03 PM PDT 24 |
9183149550 ps |
| T464 |
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.2038661379 |
|
|
Jun 13 04:14:53 PM PDT 24 |
Jun 13 04:23:43 PM PDT 24 |
4133039950 ps |
| T561 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.1819666390 |
|
|
Jun 13 03:41:29 PM PDT 24 |
Jun 13 03:50:33 PM PDT 24 |
5310265188 ps |
| T200 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1592315978 |
|
|
Jun 13 03:41:02 PM PDT 24 |
Jun 13 03:42:46 PM PDT 24 |
2454176275 ps |
| T362 |
/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.1924739135 |
|
|
Jun 13 04:11:14 PM PDT 24 |
Jun 13 04:17:16 PM PDT 24 |
4089476748 ps |
| T113 |
/workspace/coverage/default/67.chip_sw_all_escalation_resets.447058406 |
|
|
Jun 13 04:14:00 PM PDT 24 |
Jun 13 04:21:27 PM PDT 24 |
5385421640 ps |
| T69 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1497100534 |
|
|
Jun 13 03:50:10 PM PDT 24 |
Jun 13 04:01:55 PM PDT 24 |
4725243814 ps |
| T164 |
/workspace/coverage/default/84.chip_sw_all_escalation_resets.316671332 |
|
|
Jun 13 04:17:23 PM PDT 24 |
Jun 13 04:26:48 PM PDT 24 |
5507941996 ps |
| T171 |
/workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.1126774501 |
|
|
Jun 13 03:35:56 PM PDT 24 |
Jun 13 03:58:33 PM PDT 24 |
7842460152 ps |
| T141 |
/workspace/coverage/default/0.chip_sw_kmac_smoketest.2913912989 |
|
|
Jun 13 03:39:11 PM PDT 24 |
Jun 13 03:42:52 PM PDT 24 |
2573517036 ps |
| T172 |
/workspace/coverage/default/1.chip_sw_flash_crash_alert.14728349 |
|
|
Jun 13 03:51:15 PM PDT 24 |
Jun 13 04:02:17 PM PDT 24 |
4686834950 ps |
| T173 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.3155130978 |
|
|
Jun 13 03:40:58 PM PDT 24 |
Jun 13 03:51:30 PM PDT 24 |
4205818772 ps |
| T174 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.226366054 |
|
|
Jun 13 03:55:42 PM PDT 24 |
Jun 13 03:57:26 PM PDT 24 |
1965211701 ps |
| T43 |
/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.1233050194 |
|
|
Jun 13 03:54:19 PM PDT 24 |
Jun 13 03:58:43 PM PDT 24 |
2868207042 ps |
| T70 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.2432957532 |
|
|
Jun 13 03:41:20 PM PDT 24 |
Jun 13 03:45:13 PM PDT 24 |
3008056233 ps |
| T175 |
/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.4147933979 |
|
|
Jun 13 04:09:43 PM PDT 24 |
Jun 13 04:16:26 PM PDT 24 |
3933248820 ps |
| T151 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.3320769231 |
|
|
Jun 13 03:59:52 PM PDT 24 |
Jun 13 04:12:57 PM PDT 24 |
4146833760 ps |
| T471 |
/workspace/coverage/default/0.chip_sw_flash_crash_alert.1660590568 |
|
|
Jun 13 03:42:30 PM PDT 24 |
Jun 13 03:53:48 PM PDT 24 |
5083419378 ps |
| T298 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.2400485590 |
|
|
Jun 13 03:45:03 PM PDT 24 |
Jun 13 05:03:40 PM PDT 24 |
15658386242 ps |
| T212 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.1317700997 |
|
|
Jun 13 03:37:32 PM PDT 24 |
Jun 13 03:52:54 PM PDT 24 |
7622904560 ps |
| T30 |
/workspace/coverage/default/0.chip_sw_usbdev_config_host.1981531618 |
|
|
Jun 13 03:36:35 PM PDT 24 |
Jun 13 04:01:03 PM PDT 24 |
8272608998 ps |
| T26 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through.332472435 |
|
|
Jun 13 03:55:02 PM PDT 24 |
Jun 13 04:05:46 PM PDT 24 |
5940533389 ps |
| T562 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.344535170 |
|
|
Jun 13 03:38:39 PM PDT 24 |
Jun 13 05:10:15 PM PDT 24 |
26579653006 ps |
| T294 |
/workspace/coverage/default/2.chip_sw_data_integrity_escalation.1005411525 |
|
|
Jun 13 03:53:13 PM PDT 24 |
Jun 13 04:08:53 PM PDT 24 |
5124619820 ps |
| T71 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1436501216 |
|
|
Jun 13 04:03:37 PM PDT 24 |
Jun 13 04:19:30 PM PDT 24 |
6929832753 ps |
| T364 |
/workspace/coverage/default/50.chip_sw_all_escalation_resets.3342721570 |
|
|
Jun 13 04:12:30 PM PDT 24 |
Jun 13 04:19:26 PM PDT 24 |
4912897486 ps |
| T52 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.3725387396 |
|
|
Jun 13 03:48:53 PM PDT 24 |
Jun 13 05:35:55 PM PDT 24 |
22142954069 ps |
| T188 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.565580685 |
|
|
Jun 13 03:37:47 PM PDT 24 |
Jun 13 04:06:14 PM PDT 24 |
7379738658 ps |
| T80 |
/workspace/coverage/default/1.chip_sw_edn_boot_mode.2011655604 |
|
|
Jun 13 03:44:43 PM PDT 24 |
Jun 13 03:54:27 PM PDT 24 |
3492367290 ps |
| T213 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.3057137639 |
|
|
Jun 13 03:39:28 PM PDT 24 |
Jun 13 03:42:19 PM PDT 24 |
1928541606 ps |
| T338 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.413698829 |
|
|
Jun 13 03:38:17 PM PDT 24 |
Jun 13 03:43:20 PM PDT 24 |
2955032148 ps |
| T124 |
/workspace/coverage/default/0.chip_sw_flash_init.3970534936 |
|
|
Jun 13 03:34:25 PM PDT 24 |
Jun 13 04:01:59 PM PDT 24 |
23245708775 ps |
| T269 |
/workspace/coverage/default/18.chip_sw_uart_rand_baudrate.112877976 |
|
|
Jun 13 04:09:57 PM PDT 24 |
Jun 13 04:35:56 PM PDT 24 |
7550698520 ps |
| T270 |
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.651756744 |
|
|
Jun 13 04:07:45 PM PDT 24 |
Jun 13 04:18:52 PM PDT 24 |
4008588176 ps |
| T339 |
/workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.1689713518 |
|
|
Jun 13 03:56:09 PM PDT 24 |
Jun 13 04:12:46 PM PDT 24 |
10095928650 ps |
| T31 |
/workspace/coverage/default/0.chip_sw_usbdev_setuprx.1667434329 |
|
|
Jun 13 03:37:24 PM PDT 24 |
Jun 13 03:48:35 PM PDT 24 |
4035352384 ps |
| T340 |
/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.370787214 |
|
|
Jun 13 04:10:53 PM PDT 24 |
Jun 13 04:17:12 PM PDT 24 |
3939038926 ps |
| T287 |
/workspace/coverage/default/2.chip_sw_alert_handler_escalation.510662546 |
|
|
Jun 13 03:57:53 PM PDT 24 |
Jun 13 04:04:58 PM PDT 24 |
5037484300 ps |
| T148 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.601141877 |
|
|
Jun 13 03:38:22 PM PDT 24 |
Jun 13 03:47:14 PM PDT 24 |
5720592742 ps |
| T181 |
/workspace/coverage/default/2.chip_plic_all_irqs_20.1273307471 |
|
|
Jun 13 04:01:24 PM PDT 24 |
Jun 13 04:19:25 PM PDT 24 |
4840203660 ps |
| T273 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.2131075415 |
|
|
Jun 13 03:43:15 PM PDT 24 |
Jun 13 03:48:53 PM PDT 24 |
3404842408 ps |
| T563 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.1704489486 |
|
|
Jun 13 03:56:59 PM PDT 24 |
Jun 13 04:19:38 PM PDT 24 |
5791044500 ps |
| T138 |
/workspace/coverage/default/2.chip_sw_hmac_multistream.3859588589 |
|
|
Jun 13 03:58:47 PM PDT 24 |
Jun 13 04:20:59 PM PDT 24 |
6981232888 ps |
| T76 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1741671826 |
|
|
Jun 13 03:39:41 PM PDT 24 |
Jun 13 03:52:03 PM PDT 24 |
4711211418 ps |
| T27 |
/workspace/coverage/default/1.chip_sw_spi_device_pass_through.3526985081 |
|
|
Jun 13 03:41:10 PM PDT 24 |
Jun 13 03:49:50 PM PDT 24 |
5629263414 ps |
| T203 |
/workspace/coverage/default/12.chip_sw_lc_ctrl_transition.394372180 |
|
|
Jun 13 04:08:15 PM PDT 24 |
Jun 13 04:23:42 PM PDT 24 |
12665133443 ps |
| T182 |
/workspace/coverage/default/0.chip_plic_all_irqs_20.911355233 |
|
|
Jun 13 03:39:59 PM PDT 24 |
Jun 13 03:52:20 PM PDT 24 |
4628561208 ps |
| T564 |
/workspace/coverage/default/4.chip_tap_straps_prod.2177452720 |
|
|
Jun 13 04:05:06 PM PDT 24 |
Jun 13 04:15:02 PM PDT 24 |
7134675692 ps |
| T60 |
/workspace/coverage/default/0.chip_jtag_mem_access.1492877793 |
|
|
Jun 13 03:30:05 PM PDT 24 |
Jun 13 03:58:12 PM PDT 24 |
14008357996 ps |
| T565 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.1077545346 |
|
|
Jun 13 03:47:49 PM PDT 24 |
Jun 13 04:02:30 PM PDT 24 |
8639495799 ps |
| T32 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.2826293277 |
|
|
Jun 13 03:36:32 PM PDT 24 |
Jun 13 04:07:21 PM PDT 24 |
23496556290 ps |
| T566 |
/workspace/coverage/default/0.chip_sw_entropy_src_kat_test.1092108299 |
|
|
Jun 13 03:36:01 PM PDT 24 |
Jun 13 03:42:07 PM PDT 24 |
2694406502 ps |
| T309 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.2733596180 |
|
|
Jun 13 03:56:28 PM PDT 24 |
Jun 13 03:58:17 PM PDT 24 |
2248950357 ps |
| T127 |
/workspace/coverage/default/0.chip_sw_kmac_app_rom.537364216 |
|
|
Jun 13 03:36:53 PM PDT 24 |
Jun 13 03:40:12 PM PDT 24 |
3066094552 ps |
| T194 |
/workspace/coverage/default/20.chip_sw_all_escalation_resets.124202109 |
|
|
Jun 13 04:10:44 PM PDT 24 |
Jun 13 04:21:52 PM PDT 24 |
4722031120 ps |
| T386 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3639469175 |
|
|
Jun 13 03:55:59 PM PDT 24 |
Jun 13 04:24:29 PM PDT 24 |
12978005002 ps |
| T398 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.3880119449 |
|
|
Jun 13 03:46:48 PM PDT 24 |
Jun 13 03:58:48 PM PDT 24 |
8031265254 ps |
| T343 |
/workspace/coverage/default/4.chip_tap_straps_dev.3740287515 |
|
|
Jun 13 04:06:29 PM PDT 24 |
Jun 13 04:26:44 PM PDT 24 |
12177002059 ps |
| T152 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.3442063652 |
|
|
Jun 13 03:53:15 PM PDT 24 |
Jun 13 03:58:31 PM PDT 24 |
2814103880 ps |
| T89 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2419425174 |
|
|
Jun 13 04:00:19 PM PDT 24 |
Jun 13 04:11:40 PM PDT 24 |
5102371288 ps |
| T462 |
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.4059217088 |
|
|
Jun 13 04:14:12 PM PDT 24 |
Jun 13 04:23:22 PM PDT 24 |
4480975068 ps |
| T567 |
/workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.3758489339 |
|
|
Jun 13 03:40:51 PM PDT 24 |
Jun 13 03:50:26 PM PDT 24 |
4846022064 ps |
| T103 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.3550176091 |
|
|
Jun 13 03:41:02 PM PDT 24 |
Jun 13 07:58:36 PM PDT 24 |
77781803065 ps |
| T414 |
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.1196512145 |
|
|
Jun 13 04:14:49 PM PDT 24 |
Jun 13 04:21:03 PM PDT 24 |
3979691556 ps |
| T473 |
/workspace/coverage/default/85.chip_sw_all_escalation_resets.1259511563 |
|
|
Jun 13 04:15:24 PM PDT 24 |
Jun 13 04:24:11 PM PDT 24 |
5736755240 ps |
| T81 |
/workspace/coverage/default/2.chip_sw_edn_auto_mode.1889999175 |
|
|
Jun 13 03:59:02 PM PDT 24 |
Jun 13 04:19:58 PM PDT 24 |
4885531352 ps |
| T568 |
/workspace/coverage/default/2.chip_sw_entropy_src_smoketest.999355102 |
|
|
Jun 13 04:03:37 PM PDT 24 |
Jun 13 04:13:11 PM PDT 24 |
3825097520 ps |
| T569 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.4176268230 |
|
|
Jun 13 04:05:04 PM PDT 24 |
Jun 13 04:17:16 PM PDT 24 |
4608065108 ps |
| T139 |
/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.1425832610 |
|
|
Jun 13 03:41:19 PM PDT 24 |
Jun 13 03:45:34 PM PDT 24 |
3559217345 ps |
| T419 |
/workspace/coverage/default/1.chip_sw_aes_masking_off.2853845278 |
|
|
Jun 13 03:48:48 PM PDT 24 |
Jun 13 03:53:24 PM PDT 24 |
2579220504 ps |
| T53 |
/workspace/coverage/default/2.rom_e2e_shutdown_output.59635681 |
|
|
Jun 13 04:06:52 PM PDT 24 |
Jun 13 04:52:28 PM PDT 24 |
23082853282 ps |
| T189 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.121237835 |
|
|
Jun 13 04:01:56 PM PDT 24 |
Jun 13 04:07:05 PM PDT 24 |
3208443019 ps |
| T474 |
/workspace/coverage/default/37.chip_sw_all_escalation_resets.3855721717 |
|
|
Jun 13 04:10:41 PM PDT 24 |
Jun 13 04:22:09 PM PDT 24 |
5463921328 ps |
| T128 |
/workspace/coverage/default/1.chip_sw_kmac_app_rom.256412332 |
|
|
Jun 13 03:46:56 PM PDT 24 |
Jun 13 03:51:33 PM PDT 24 |
2511239304 ps |
| T219 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.2709473125 |
|
|
Jun 13 03:44:27 PM PDT 24 |
Jun 13 03:59:27 PM PDT 24 |
4647085762 ps |
| T570 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.2351865541 |
|
|
Jun 13 03:40:41 PM PDT 24 |
Jun 13 03:53:10 PM PDT 24 |
8063664812 ps |
| T310 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.2197657151 |
|
|
Jun 13 03:43:46 PM PDT 24 |
Jun 13 04:34:45 PM PDT 24 |
13384662291 ps |
| T8 |
/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.905707214 |
|
|
Jun 13 03:42:06 PM PDT 24 |
Jun 13 03:47:28 PM PDT 24 |
3411986810 ps |
| T95 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1003282327 |
|
|
Jun 13 03:53:58 PM PDT 24 |
Jun 13 04:03:51 PM PDT 24 |
6717581408 ps |
| T201 |
/workspace/coverage/default/2.chip_sw_flash_init.1748694949 |
|
|
Jun 13 03:54:49 PM PDT 24 |
Jun 13 04:30:11 PM PDT 24 |
21665091629 ps |
| T447 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.373193812 |
|
|
Jun 13 03:45:02 PM PDT 24 |
Jun 13 04:11:18 PM PDT 24 |
12195643120 ps |
| T448 |
/workspace/coverage/default/0.chip_sw_example_flash.2881275981 |
|
|
Jun 13 03:37:23 PM PDT 24 |
Jun 13 03:41:21 PM PDT 24 |
3103959880 ps |
| T449 |
/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.925706735 |
|
|
Jun 13 04:14:48 PM PDT 24 |
Jun 13 04:22:34 PM PDT 24 |
3859827036 ps |
| T214 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.3955749802 |
|
|
Jun 13 03:54:48 PM PDT 24 |
Jun 13 03:58:35 PM PDT 24 |
3155478965 ps |
| T133 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_peri.2266300053 |
|
|
Jun 13 03:59:26 PM PDT 24 |
Jun 13 04:24:28 PM PDT 24 |
11264081264 ps |
| T114 |
/workspace/coverage/default/7.chip_sw_all_escalation_resets.2003645863 |
|
|
Jun 13 04:07:54 PM PDT 24 |
Jun 13 04:17:53 PM PDT 24 |
4979269228 ps |
| T143 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.3737447307 |
|
|
Jun 13 03:37:21 PM PDT 24 |
Jun 13 03:43:25 PM PDT 24 |
3080742371 ps |
| T303 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.54181082 |
|
|
Jun 13 03:55:39 PM PDT 24 |
Jun 13 04:16:19 PM PDT 24 |
8280556682 ps |
| T304 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.817006825 |
|
|
Jun 13 03:41:42 PM PDT 24 |
Jun 13 04:03:11 PM PDT 24 |
8365115920 ps |
| T305 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.580770080 |
|
|
Jun 13 03:49:11 PM PDT 24 |
Jun 13 03:58:34 PM PDT 24 |
4050941776 ps |
| T306 |
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.3690324746 |
|
|
Jun 13 04:07:19 PM PDT 24 |
Jun 13 05:28:32 PM PDT 24 |
21152097826 ps |
| T307 |
/workspace/coverage/default/29.chip_sw_all_escalation_resets.2094574062 |
|
|
Jun 13 04:11:23 PM PDT 24 |
Jun 13 04:21:04 PM PDT 24 |
5023885550 ps |
| T82 |
/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.2996635336 |
|
|
Jun 13 03:59:05 PM PDT 24 |
Jun 13 04:10:11 PM PDT 24 |
7021774995 ps |
| T153 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.1329408229 |
|
|
Jun 13 03:37:39 PM PDT 24 |
Jun 13 03:43:30 PM PDT 24 |
4550521558 ps |
| T308 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1513365123 |
|
|
Jun 13 03:37:27 PM PDT 24 |
Jun 13 04:05:06 PM PDT 24 |
13305525808 ps |
| T125 |
/workspace/coverage/default/1.chip_sw_alert_test.2215097811 |
|
|
Jun 13 03:44:45 PM PDT 24 |
Jun 13 03:48:50 PM PDT 24 |
3606429986 ps |
| T342 |
/workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.3374840067 |
|
|
Jun 13 03:53:26 PM PDT 24 |
Jun 13 04:13:24 PM PDT 24 |
9018455398 ps |
| T478 |
/workspace/coverage/default/73.chip_sw_all_escalation_resets.1165127946 |
|
|
Jun 13 04:15:50 PM PDT 24 |
Jun 13 04:25:50 PM PDT 24 |
6357189500 ps |
| T571 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.647575320 |
|
|
Jun 13 03:41:46 PM PDT 24 |
Jun 13 03:46:30 PM PDT 24 |
2502444966 ps |
| T72 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.2478069591 |
|
|
Jun 13 03:45:50 PM PDT 24 |
Jun 13 04:01:53 PM PDT 24 |
6569058037 ps |
| T160 |
/workspace/coverage/default/2.chip_tap_straps_rma.1392517638 |
|
|
Jun 13 04:01:58 PM PDT 24 |
Jun 13 04:08:50 PM PDT 24 |
5493249337 ps |
| T572 |
/workspace/coverage/default/1.chip_sw_hmac_enc.1599378937 |
|
|
Jun 13 03:47:42 PM PDT 24 |
Jun 13 03:52:56 PM PDT 24 |
2653674440 ps |
| T258 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.2188662696 |
|
|
Jun 13 03:42:32 PM PDT 24 |
Jun 13 03:50:34 PM PDT 24 |
5229661128 ps |
| T573 |
/workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.1572941345 |
|
|
Jun 13 04:09:37 PM PDT 24 |
Jun 13 04:13:52 PM PDT 24 |
2650896968 ps |
| T468 |
/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.1851008815 |
|
|
Jun 13 04:10:54 PM PDT 24 |
Jun 13 04:17:10 PM PDT 24 |
3570956814 ps |
| T190 |
/workspace/coverage/default/2.chip_sw_otbn_smoketest.2274220409 |
|
|
Jun 13 04:03:55 PM PDT 24 |
Jun 13 04:29:29 PM PDT 24 |
8375826664 ps |
| T574 |
/workspace/coverage/default/2.chip_sw_uart_smoketest.2438847763 |
|
|
Jun 13 04:04:07 PM PDT 24 |
Jun 13 04:08:52 PM PDT 24 |
2268385380 ps |
| T370 |
/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.1931541403 |
|
|
Jun 13 03:42:17 PM PDT 24 |
Jun 13 03:50:01 PM PDT 24 |
4444997080 ps |
| T575 |
/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.602561538 |
|
|
Jun 13 04:03:59 PM PDT 24 |
Jun 13 04:09:10 PM PDT 24 |
3437219840 ps |
| T472 |
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.1054334213 |
|
|
Jun 13 04:18:02 PM PDT 24 |
Jun 13 04:23:35 PM PDT 24 |
4158543384 ps |
| T576 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.151943364 |
|
|
Jun 13 03:58:01 PM PDT 24 |
Jun 13 04:43:20 PM PDT 24 |
28672634276 ps |
| T577 |
/workspace/coverage/default/1.chip_sw_kmac_smoketest.2614018171 |
|
|
Jun 13 03:53:41 PM PDT 24 |
Jun 13 03:59:38 PM PDT 24 |
3533350558 ps |
| T578 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3113468052 |
|
|
Jun 13 04:01:42 PM PDT 24 |
Jun 13 04:16:32 PM PDT 24 |
4708056290 ps |
| T185 |
/workspace/coverage/default/2.chip_plic_all_irqs_0.734804293 |
|
|
Jun 13 03:59:30 PM PDT 24 |
Jun 13 04:16:00 PM PDT 24 |
6545079576 ps |
| T579 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter.3234568 |
|
|
Jun 13 04:02:17 PM PDT 24 |
Jun 13 04:06:56 PM PDT 24 |
2834625617 ps |
| T167 |
/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.903271056 |
|
|
Jun 13 04:12:04 PM PDT 24 |
Jun 13 04:19:00 PM PDT 24 |
3933509800 ps |
| T377 |
/workspace/coverage/default/55.chip_sw_all_escalation_resets.230219369 |
|
|
Jun 13 04:15:50 PM PDT 24 |
Jun 13 04:28:18 PM PDT 24 |
6112495000 ps |
| T580 |
/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.3250638580 |
|
|
Jun 13 04:11:00 PM PDT 24 |
Jun 13 04:22:08 PM PDT 24 |
4498253672 ps |
| T496 |
/workspace/coverage/default/92.chip_sw_all_escalation_resets.3947572430 |
|
|
Jun 13 04:17:12 PM PDT 24 |
Jun 13 04:29:50 PM PDT 24 |
5165636280 ps |
| T33 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.3628283852 |
|
|
Jun 13 03:58:04 PM PDT 24 |
Jun 13 04:51:08 PM PDT 24 |
20323191345 ps |
| T149 |
/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.3112303976 |
|
|
Jun 13 03:37:31 PM PDT 24 |
Jun 13 03:47:06 PM PDT 24 |
6034152902 ps |
| T581 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.544339789 |
|
|
Jun 13 03:40:22 PM PDT 24 |
Jun 13 04:02:12 PM PDT 24 |
5187580746 ps |
| T582 |
/workspace/coverage/default/0.chip_sw_hmac_enc_idle.1627817259 |
|
|
Jun 13 03:37:01 PM PDT 24 |
Jun 13 03:41:52 PM PDT 24 |
3160425662 ps |
| T311 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.1360170125 |
|
|
Jun 13 03:38:52 PM PDT 24 |
Jun 13 03:40:49 PM PDT 24 |
2629708563 ps |
| T529 |
/workspace/coverage/default/30.chip_sw_all_escalation_resets.3696898610 |
|
|
Jun 13 04:10:57 PM PDT 24 |
Jun 13 04:21:55 PM PDT 24 |
5945100132 ps |
| T583 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access.1010997115 |
|
|
Jun 13 03:54:53 PM PDT 24 |
Jun 13 04:13:06 PM PDT 24 |
5184826800 ps |
| T584 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2904378098 |
|
|
Jun 13 03:39:52 PM PDT 24 |
Jun 13 03:50:03 PM PDT 24 |
3681931610 ps |
| T396 |
/workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.1568688495 |
|
|
Jun 13 03:40:06 PM PDT 24 |
Jun 13 04:09:33 PM PDT 24 |
12746081380 ps |
| T348 |
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.1508109948 |
|
|
Jun 13 04:13:30 PM PDT 24 |
Jun 13 04:21:15 PM PDT 24 |
3648114024 ps |
| T585 |
/workspace/coverage/default/2.rom_e2e_static_critical.608586413 |
|
|
Jun 13 04:08:04 PM PDT 24 |
Jun 13 05:02:23 PM PDT 24 |
16910587490 ps |
| T378 |
/workspace/coverage/default/35.chip_sw_all_escalation_resets.4142845627 |
|
|
Jun 13 04:10:26 PM PDT 24 |
Jun 13 04:21:09 PM PDT 24 |
4842608566 ps |
| T246 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.1541635172 |
|
|
Jun 13 03:36:24 PM PDT 24 |
Jun 13 07:39:58 PM PDT 24 |
77788338002 ps |
| T406 |
/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.1348103030 |
|
|
Jun 13 03:49:57 PM PDT 24 |
Jun 13 03:53:45 PM PDT 24 |
3316909837 ps |
| T407 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1353662024 |
|
|
Jun 13 04:01:48 PM PDT 24 |
Jun 13 04:08:39 PM PDT 24 |
3259479338 ps |
| T408 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.1816354856 |
|
|
Jun 13 03:43:34 PM PDT 24 |
Jun 13 04:02:44 PM PDT 24 |
5179376344 ps |
| T409 |
/workspace/coverage/default/95.chip_sw_all_escalation_resets.58196793 |
|
|
Jun 13 04:18:33 PM PDT 24 |
Jun 13 04:26:56 PM PDT 24 |
5198850376 ps |
| T195 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.3231334861 |
|
|
Jun 13 03:36:02 PM PDT 24 |
Jun 13 03:37:49 PM PDT 24 |
1952981615 ps |
| T399 |
/workspace/coverage/default/24.chip_sw_all_escalation_resets.2071521928 |
|
|
Jun 13 04:11:03 PM PDT 24 |
Jun 13 04:20:59 PM PDT 24 |
4038355096 ps |
| T410 |
/workspace/coverage/default/90.chip_sw_all_escalation_resets.3984646295 |
|
|
Jun 13 04:16:33 PM PDT 24 |
Jun 13 04:26:56 PM PDT 24 |
5795846710 ps |
| T34 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.3688840728 |
|
|
Jun 13 03:42:31 PM PDT 24 |
Jun 13 03:48:19 PM PDT 24 |
3888523188 ps |
| T349 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation.3969764765 |
|
|
Jun 13 03:59:50 PM PDT 24 |
Jun 13 04:33:48 PM PDT 24 |
9873872232 ps |
| T586 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.1771788609 |
|
|
Jun 13 03:39:07 PM PDT 24 |
Jun 13 03:46:53 PM PDT 24 |
4822600056 ps |
| T323 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.52310434 |
|
|
Jun 13 03:48:24 PM PDT 24 |
Jun 13 04:03:41 PM PDT 24 |
9026613784 ps |
| T220 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.1273197601 |
|
|
Jun 13 03:37:01 PM PDT 24 |
Jun 13 03:53:46 PM PDT 24 |
5439119480 ps |
| T587 |
/workspace/coverage/default/2.chip_sw_kmac_idle.3045945203 |
|
|
Jun 13 03:59:58 PM PDT 24 |
Jun 13 04:04:58 PM PDT 24 |
3390658226 ps |
| T588 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.3374689223 |
|
|
Jun 13 03:45:46 PM PDT 24 |
Jun 13 04:18:01 PM PDT 24 |
7171790794 ps |
| T466 |
/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.100509147 |
|
|
Jun 13 04:01:33 PM PDT 24 |
Jun 13 04:10:17 PM PDT 24 |
3939387792 ps |
| T589 |
/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.3202146165 |
|
|
Jun 13 03:39:36 PM PDT 24 |
Jun 13 03:50:04 PM PDT 24 |
3972887240 ps |
| T382 |
/workspace/coverage/default/4.chip_sw_all_escalation_resets.2550606098 |
|
|
Jun 13 04:06:53 PM PDT 24 |
Jun 13 04:17:10 PM PDT 24 |
4638071270 ps |
| T134 |
/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.605360091 |
|
|
Jun 13 03:56:11 PM PDT 24 |
Jun 13 04:26:09 PM PDT 24 |
14095266444 ps |
| T590 |
/workspace/coverage/default/1.rom_e2e_static_critical.11505235 |
|
|
Jun 13 03:56:10 PM PDT 24 |
Jun 13 05:00:07 PM PDT 24 |
16209327464 ps |
| T534 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.35894015 |
|
|
Jun 13 04:00:59 PM PDT 24 |
Jun 13 04:10:38 PM PDT 24 |
3411646790 ps |
| T591 |
/workspace/coverage/default/2.chip_sw_aes_idle.1169577606 |
|
|
Jun 13 03:57:27 PM PDT 24 |
Jun 13 04:01:50 PM PDT 24 |
3048847220 ps |
| T202 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.1969184117 |
|
|
Jun 13 03:40:53 PM PDT 24 |
Jun 13 05:13:19 PM PDT 24 |
47521010490 ps |
| T77 |
/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2727704109 |
|
|
Jun 13 03:57:29 PM PDT 24 |
Jun 13 04:05:52 PM PDT 24 |
19171253200 ps |
| T90 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.1191892398 |
|
|
Jun 13 03:39:55 PM PDT 24 |
Jun 13 03:54:51 PM PDT 24 |
8875479224 ps |
| T530 |
/workspace/coverage/default/81.chip_sw_all_escalation_resets.460491950 |
|
|
Jun 13 04:14:59 PM PDT 24 |
Jun 13 04:24:50 PM PDT 24 |
5824538096 ps |
| T96 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.655338652 |
|
|
Jun 13 03:49:54 PM PDT 24 |
Jun 13 04:00:26 PM PDT 24 |
6108439804 ps |
| T109 |
/workspace/coverage/default/0.chip_plic_all_irqs_10.644304353 |
|
|
Jun 13 03:40:01 PM PDT 24 |
Jun 13 03:52:04 PM PDT 24 |
4143861786 ps |
| T592 |
/workspace/coverage/default/1.rom_e2e_asm_init_rma.710260979 |
|
|
Jun 13 03:57:45 PM PDT 24 |
Jun 13 05:05:19 PM PDT 24 |
14971755663 ps |
| T593 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3153010052 |
|
|
Jun 13 04:00:51 PM PDT 24 |
Jun 13 04:12:00 PM PDT 24 |
4102534192 ps |
| T296 |
/workspace/coverage/default/1.chip_sw_rv_timer_smoketest.2997705595 |
|
|
Jun 13 03:53:07 PM PDT 24 |
Jun 13 03:57:23 PM PDT 24 |
2923619520 ps |
| T594 |
/workspace/coverage/default/12.chip_sw_uart_rand_baudrate.1480956545 |
|
|
Jun 13 04:08:13 PM PDT 24 |
Jun 13 04:34:04 PM PDT 24 |
8553196720 ps |
| T595 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.1513830494 |
|
|
Jun 13 03:56:21 PM PDT 24 |
Jun 13 04:03:30 PM PDT 24 |
6650362580 ps |