Design Module List
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Total Module Definition Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.16 94.58 73.21 86.13 95.06 91.82


Total modules in report: 109
modlist.html | modlist1.html
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_mubi4_dec 0.00 0.00
pinmux_wkup 64.07 68.42 69.23 54.55
prim_packer_fifo 68.93 100.00 90.00 85.71 0.00
rv_plic_gateway 69.17 100.00 20.00 87.50
padring 76.20 98.18 54.21
ast 79.12 79.12
spi_device 79.17 79.17
xbar_main 80.76 80.76
pinmux 81.22 78.50 86.63 66.10 82.86 92.00
usbdev 82.35 82.35
top_earlgrey 83.02 90.68 58.36 100.00
entropy_src 83.08 83.08
tlul_err 83.23 96.15 74.29 62.50 100.00
spi_host 83.24 83.24
hmac 83.54 83.54
otp_ctrl 83.63 83.63
i2c 84.09 84.09
prim_generic_clock_mux2 85.19 100.00 55.56 100.00
flash_ctrl 85.89 85.89
rv_plic_reg_top 86.88 90.13 60.26 97.12 100.00
rv_dm 87.21 87.21
rv_core_ibex 88.05 96.47 89.29 86.30 100.00 68.18
prim_reg_cdc_arb 88.49 94.00 86.05 73.91 100.00
prim_reg_cdc_arb 86.96 73.91 100.00
prim_reg_cdc_arb ( parameter DataWidth=11,ResetVal=0,DstWrReq=1 + DataWidth=4,ResetVal=9,DstWrReq=1 + DataWidth=1,ResetVal=0,DstWrReq=1 + DataWidth=28,ResetVal=0,DstWrReq=1 + DataWidth=9,ResetVal=0,DstWrReq=1 + DataWidth=5,ResetVal=0,DstWrReq=1 + DataWidth=8,ResetVal=0,DstWrReq=1 + DataWidth=32,ResetVal=0,DstWrReq=1 ) 80.05 88.00 72.09
prim_reg_cdc_arb ( parameter DataWidth=2,ResetVal=0,DstWrReq=0 + DataWidth=20,ResetVal,DstWrReq=0 + DataWidth=18,ResetVal=118010,DstWrReq=0 + DataWidth=16,ResetVal,DstWrReq=0 + DataWidth=1,ResetVal=0,DstWrReq=0 + DataWidth=12,ResetVal=0,DstWrReq=0 + DataWidth=8,ResetVal,DstWrReq=0 + DataWidth=14,ResetVal=0,DstWrReq=0 + DataWidth=17,ResetVal=2000,DstWrReq=0 + DataWidth=7,ResetVal=0,DstWrReq=0 + DataWidth=5,ResetVal=0,DstWrReq=0 + DataWidth=32,ResetVal,DstWrReq=0 + DataWidth=4,ResetVal=0,DstWrReq=0 + DataWidth=9,ResetVal=0,DstWrReq=0 + DataWidth=6,ResetVal=0,DstWrReq=0 + DataWidth=13,ResetVal=0,DstWrReq=0 ) 100.00 100.00 100.00
prim_generic_pad_wrapper 88.89 88.89 83.33 83.33 100.00
prim_generic_pad_wrapper 100.00 100.00
prim_generic_pad_wrapper ( parameter PadType=0,ScanRole=0 ) 100.00 100.00 100.00 100.00
prim_generic_pad_wrapper ( parameter PadType=3,ScanRole=0 ) 100.00 100.00 100.00 100.00
prim_generic_pad_wrapper ( parameter PadType=4,ScanRole=0 ) 55.56 66.67 50.00 50.00
rv_timer 89.04 89.04
keymgr 89.25 89.25
rv_plic 89.31 99.65 66.67 90.22 100.00 90.00
tlul_adapter_host 89.63 93.28 75.79 89.44 100.00
tlul_adapter_host 100.00 100.00
tlul_adapter_host ( parameter MAX_REQS=2,EnableDataIntgGen=1,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 + MAX_REQS=2,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 ) 89.34 95.65 82.35 90.00
tlul_adapter_host ( parameter MAX_REQS=8,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=4,g_multiple_reqs.ReqNumW=3 ) 83.01 90.91 69.23 88.89
xbar_peri 89.80 89.80
lc_ctrl 89.88 89.88
pattgen 90.00 90.00
pwm 90.20 90.20
uart 90.26 90.26
sysrst_ctrl 90.42 90.42
aon_timer 90.45 90.45
adc_ctrl 90.74 90.74
prim_max_tree 91.58 89.27 77.06 100.00 100.00
tlul_rsp_intg_gen 91.67 83.33 100.00
tlul_rsp_intg_gen 100.00 100.00
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=0,EnableDataIntgGen=0 ) 66.67 66.67
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=1,EnableDataIntgGen=1 ) 100.00 100.00
prim_sync_reqack 91.67 100.00 66.67 100.00 100.00
rv_core_ibex_cfg_reg_top 91.67 99.44 70.10 97.14 100.00
tlul_err_resp 91.75 95.24 80.00 100.00
chip_earlgrey_asic 91.90 80.00 100.00 95.71
rstmgr 92.31 92.31
pinmux_reg_top 92.35 99.57 69.82 100.00 100.00
sensor_ctrl_reg_top 92.41 100.00 69.65 100.00 100.00
sensor_ctrl 92.83 94.59 90.00 79.58 100.00 100.00
tlul_socket_1n 93.04 91.07 86.36 94.74 100.00
pwrmgr 93.07 93.07
tlul_rsp_intg_chk 93.33 100.00 80.00 100.00
sram_ctrl 93.73 93.73
ibex_top 93.83 93.83
gpio 94.07 94.07
tlul_adapter_reg 94.24 97.37 79.59 100.00 100.00
rom_ctrl 94.69 94.69
clkmgr 95.10 95.10
edn 95.29 95.29
prim_edn_req 96.15 100.00 84.62 100.00 100.00
prim_generic_usb_diff_rx 96.30 100.00 88.89 100.00
prim_arbiter_fixed 96.55 100.00 93.33 100.00 92.86
aes 96.90 96.90
csrng 96.93 96.93
usbdev_aon_wake 96.98 100.00 93.18 94.74 100.00
otbn 97.23 97.23
prim_reg_cdc 97.25 100.00 89.01 100.00 100.00
prim_reg_cdc 100.00 100.00 100.00 100.00
prim_reg_cdc ( parameter DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=0,TxnWidth=3 + DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=1,TxnWidth=3 ) 92.31 92.31
prim_reg_cdc ( parameter DataWidth=2,ResetVal=0,BitMask=3,DstWrReq=0,TxnWidth=3 + DataWidth=11,ResetVal=0,BitMask=1793,DstWrReq=1,TxnWidth=3 + DataWidth=4,ResetVal=9,BitMask=15,DstWrReq=1,TxnWidth=3 + DataWidth=20,ResetVal,BitMask=1048575,DstWrReq=0,TxnWidth=3 + DataWidth=18,ResetVal=118010,BitMask=262143,DstWrReq=0,TxnWidth=3 + DataWidth=16,ResetVal,BitMask=65535,DstWrReq=0,TxnWidth=3 + DataWidth=12,ResetVal=0,BitMask=4095,DstWrReq=0,TxnWidth=3 + DataWidth=8,ResetVal,BitMask=255,DstWrReq=0,TxnWidth=3 + DataWidth=14,ResetVal=0,BitMask=16383,DstWrReq=0,TxnWidth=3 + DataWidth=17,ResetVal=2000,BitMask=131071,DstWrReq=0,TxnWidth=3 + DataWidth=7,ResetVal=0,BitMask=119,DstWrReq=0,TxnWidth=3 + DataWidth=5,ResetVal=0,BitMask=31,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal,BitMask,DstWrReq=0,TxnWidth=3 + DataWidth=4,ResetVal=0,BitMask=15,DstWrReq=0,TxnWidth=3 + DataWidth=28,ResetVal=0,BitMask=268374015,DstWrReq=1,TxnWidth=3 + DataWidth=9,ResetVal=0,BitMask=511,DstWrReq=0,TxnWidth=3 + DataWidth=9,ResetVal=0,BitMask=511,DstWrReq=1,TxnWidth=3 + DataWidth=5,ResetVal=0,BitMask=31,DstWrReq=1,TxnWidth=3 + DataWidth=6,ResetVal=0,BitMask=63,DstWrReq=0,TxnWidth=3 + DataWidth=8,ResetVal=0,BitMask=255,DstWrReq=1,TxnWidth=3 + DataWidth=13,ResetVal=0,BitMask=8191,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=1,TxnWidth=3 ) 85.71 85.71
alert_handler 97.38 97.38
kmac 98.28 98.28
pinmux_strap_sampling 99.83 99.34 100.00 100.00 100.00
prim_lc_sync 100.00 100.00 100.00
prim_lc_sync 100.00 100.00
prim_lc_sync ( parameter NumCopies=1,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 ) 100.00 100.00
prim_lc_sync ( parameter NumCopies=2,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 ) 100.00 100.00
prim_lc_sync ( parameter NumCopies=3,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 ) 100.00 100.00
prim_lc_sync ( parameter NumCopies=4,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 ) 100.00 100.00
prim_lc_sender 100.00 100.00
tlul_data_integ_dec 100.00 100.00
tlul_cmd_intg_chk 100.00 100.00 100.00
prim_alert_sender 100.00 100.00
tlul_cmd_intg_gen 100.00 100.00 100.00
tlul_fifo_sync 100.00 100.00 100.00
prim_edge_detector 100.00 100.00 100.00 100.00
clk_ctrl_and_main_pd_sva_if 100.00 100.00
prim_subreg 100.00 100.00 100.00 100.00
prim_subreg 100.00 100.00 100.00
prim_subreg ( parameter DW=1,SwAccess=1,RESVAL,Mubi=0 + DW=1,SwAccess=3,RESVAL,Mubi=0 + DW=1,SwAccess=0,RESVAL,Mubi=0 + DW=1,SwAccess=4,RESVAL=0,Mubi=0 + DW=1,SwAccess=5,RESVAL,Mubi=0 ) 100.00 100.00
prim_subreg ( parameter DW=2,SwAccess=0,RESVAL,Mubi=0 + DW=2,SwAccess=1,RESVAL=0,Mubi=0 + DW=2,SwAccess=3,RESVAL=0,Mubi=0 ) 100.00 100.00
prim_subreg ( parameter DW=3,SwAccess=0,RESVAL,Mubi=0 + DW=3,SwAccess=1,RESVAL,Mubi=0 + DW=3,SwAccess=3,RESVAL=0,Mubi=0 ) 100.00 100.00
prim_subreg ( parameter DW=32,SwAccess=1,RESVAL,Mubi=0 + DW=32,SwAccess=0,RESVAL,Mubi + DW=32,SwAccess=3,RESVAL=0,Mubi=0 ) 100.00 100.00
prim_subreg ( parameter DW=4,SwAccess=0,RESVAL,Mubi + DW=4,SwAccess=1,RESVAL=0,Mubi=0 + DW=4,SwAccess=3,RESVAL=9,Mubi=1 + DW=4,SwAccess=4,RESVAL=9,Mubi=1 ) 100.00 100.00
prim_subreg ( parameter DW=6,SwAccess=0,RESVAL,Mubi=0 + DW=6,SwAccess=1,RESVAL=0,Mubi=0 ) 100.00 100.00
prim_subreg ( parameter DW=7,SwAccess=0,RESVAL,Mubi=0 ) 100.00 100.00
prim_subreg ( parameter DW=8,SwAccess=0,RESVAL,Mubi=0 + DW=8,SwAccess=1,RESVAL,Mubi=0 + DW=8,SwAccess=3,RESVAL=0,Mubi=0 ) 100.00 100.00
prim_filter 100.00 100.00 100.00 100.00
pinmux_jtag_breakout 100.00 100.00 100.00
prim_lc_or_hardened 100.00 100.00 100.00 100.00
prim_generic_buf 100.00 100.00
prim_intr_hw 100.00 100.00 100.00 100.00 100.00
prim_pulse_sync 100.00 100.00 100.00 100.00 100.00
prim_fifo_sync 100.00 100.00 100.00
prim_subreg_arb 100.00 100.00 100.00 100.00
prim_subreg_arb 100.00 100.00
prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 + DW=32,SwAccess=3,Mubi=0 + DW=3,SwAccess=3,Mubi=0 + DW=10,SwAccess=3,Mubi=0 + DW=5,SwAccess=3,Mubi=0 + DW=8,SwAccess=3,Mubi=0 + DW=2,SwAccess=3,Mubi=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=1,SwAccess=4,Mubi=0 ) 100.00 100.00 100.00
prim_subreg_arb ( parameter DW=1,SwAccess=5,Mubi=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=1,SwAccess=5,Mubi=0 + DW=16,SwAccess=5,Mubi=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=2,SwAccess=0,Mubi=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=3,SwAccess=0,Mubi=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=32,SwAccess=0,Mubi=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=32,SwAccess=0,Mubi=0 + DW=1,SwAccess=0,Mubi=0 + DW=2,SwAccess=0,Mubi=0 + DW=16,SwAccess=0,Mubi=0 + DW=8,SwAccess=0,Mubi=0 + DW=3,SwAccess=0,Mubi=0 + DW=24,SwAccess=0,Mubi=0 + DW=10,SwAccess=0,Mubi=0 + DW=4,SwAccess=0,Mubi=1 + DW=12,SwAccess=0,Mubi=0 + DW=13,SwAccess=0,Mubi=0 + DW=9,SwAccess=0,Mubi=0 + DW=30,SwAccess=0,Mubi=0 + DW=7,SwAccess=0,Mubi=0 + DW=20,SwAccess=0,Mubi=0 + DW=31,SwAccess=0,Mubi=0 + DW=6,SwAccess=0,Mubi=0 + DW=11,SwAccess=0,Mubi=0 + DW=5,SwAccess=0,Mubi=0 + DW=27,SwAccess=0,Mubi=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=32,SwAccess=1,Mubi=0 + DW=1,SwAccess=1,Mubi=0 + DW=5,SwAccess=1,Mubi=0 + DW=9,SwAccess=1,Mubi=0 + DW=8,SwAccess=1,Mubi=0 + DW=3,SwAccess=1,Mubi=0 + DW=6,SwAccess=1,Mubi=0 + DW=4,SwAccess=1,Mubi=0 + DW=2,SwAccess=1,Mubi=0 + DW=10,SwAccess=1,Mubi=0 + DW=20,SwAccess=1,Mubi=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=4,SwAccess=0,Mubi=1 ) 100.00 100.00
prim_subreg_arb ( parameter DW=4,SwAccess=4,Mubi=1 ) 100.00 100.00 100.00
prim_subreg_arb ( parameter DW=6,SwAccess=0,Mubi=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=7,SwAccess=0,Mubi=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=8,SwAccess=0,Mubi=0 ) 100.00 100.00
prim_subreg_ext 100.00 100.00
prim_secded_inv_39_32_enc 100.00 100.00
prim_esc_receiver 100.00 100.00
prim_secded_inv_64_57_enc 100.00 100.00
prim_sync_reqack_data 100.00 100.00 100.00
rv_core_addr_trans 100.00 100.00 100.00 100.00
prim_generic_flop 100.00 100.00 100.00
rv_plic_target 100.00 100.00 100.00 100.00
prim_mubi4_sync 100.00 100.00
prim_generic_clock_buf 100.00 100.00
pinmux_jtag_buf
prim_usb_diff_rx
prim_clock_buf
tlul_data_integ_enc
prim_reg_we_check
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