Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : rstmgr
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.31 92.31

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rstmgr_0.1/rtl/rstmgr.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_rstmgr_aon 92.31 92.31



Module Instance : tb.dut.top_earlgrey.u_rstmgr_aon

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.31 92.31


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.31 92.31


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.62 90.68 87.17 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : rstmgr
TotalCoveredPercent
Totals 59 51 86.44
Total Bits 390 360 92.31
Total Bits 0->1 195 180 92.31
Total Bits 1->0 195 180 92.31

Ports 59 51 86.44
Port Bits 390 360 92.31
Port Bits 0->1 195 180 92.31
Port Bits 1->0 195 180 92.31

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T19,T20,T41 Yes T4,T5,T6 INPUT
clk_aon_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk_io_div4_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk_main_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk_io_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk_io_div2_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk_usb_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk_por_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_por_ni Yes Yes T19,T20,T21 Yes T4,T5,T6 INPUT
por_n_i[1:0] Yes Yes T19,T20,T21 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[2:1] No No No INPUT
tl_i.a_user.instr_type[3] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[1:0] No No No INPUT
tl_i.a_address[6:2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[15:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[16] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[21:17] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[22] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[29:23] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T20,*T60,*T9 Yes T20,T60,T9 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T38,T39,T40 Yes T38,T39,T40 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[0] Yes Yes *T60,*T9,*T61 Yes T60,T9,T61 INPUT
tl_i.a_opcode[1] No No No INPUT
tl_i.a_opcode[2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_o.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_o.d_error No No No OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_o.d_user.rsp_intg[1:0] Yes Yes T5,T54,T19 Yes T4,T5,T6 OUTPUT
tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
tl_o.d_user.rsp_intg[5:4] Yes Yes T19,T20,T41 Yes T4,T5,T6 OUTPUT
tl_o.d_user.rsp_intg[6] No No No OUTPUT
tl_o.d_data[31:0] Yes Yes T5,T54,T19 Yes T4,T5,T6 OUTPUT
tl_o.d_sink No No No OUTPUT
tl_o.d_source[1:0] Yes Yes *T9,*T12,*T5 Yes T9,T12,T4 OUTPUT
tl_o.d_source[5:2] No No No OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[0] No No No OUTPUT
tl_o.d_size[1] Yes Yes T19,T20,T41 Yes T4,T5,T6 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T104,T68,T376 Yes T104,T68,T376 INPUT
alert_rx_i[0].ping_n Yes Yes T104,T68,T165 Yes T104,T68,T165 INPUT
alert_rx_i[0].ping_p Yes Yes T104,T68,T165 Yes T104,T68,T165 INPUT
alert_rx_i[1].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[1].ack_p Yes Yes T104,T68,T125 Yes T104,T68,T125 INPUT
alert_rx_i[1].ping_n Yes Yes T104,T68,T395 Yes T104,T68,T165 INPUT
alert_rx_i[1].ping_p Yes Yes T104,T68,T165 Yes T104,T68,T395 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T104,T68,T376 Yes T104,T68,T376 OUTPUT
alert_tx_o[1].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[1].alert_p Yes Yes T104,T68,T125 Yes T104,T68,T125 OUTPUT
pwr_i.reset_cause[1:0] Yes Yes T4,T5,T6 Yes T19,T20,T41 INPUT
pwr_i.rstreqs[4:0] Yes Yes T243,T67,T180 Yes T243,T67,T180 INPUT
pwr_i.rst_sys_req[1:0] Yes Yes T4,T5,T6 Yes T19,T20,T41 INPUT
pwr_i.rst_lc_req[1:0] Yes Yes T4,T5,T6 Yes T19,T20,T41 INPUT
pwr_o.rst_sys_src_n[1:0] Yes Yes T19,T20,T41 Yes T4,T5,T6 OUTPUT
pwr_o.rst_lc_src_n[1:0] Yes Yes T19,T20,T41 Yes T4,T5,T6 OUTPUT
sw_rst_req_o[3:0] Yes Yes T41,T85,T88 Yes T41,T85,T88 OUTPUT
alert_dump_i.class_esc_cnt[3:0][31:0] Unreachable Unreachable Unreachable INPUT
alert_dump_i.class_accum_cnt[3:0][15:0] Unreachable Unreachable Unreachable INPUT
alert_dump_i.loc_alert_cause[6:0] Unreachable Unreachable Unreachable INPUT
alert_dump_i.alert_cause[64:0] Unreachable Unreachable Unreachable INPUT
cpu_dump_i.current.exception_addr[31:0] Unreachable Unreachable Unreachable INPUT
cpu_dump_i.current.exception_pc[31:0] Unreachable Unreachable Unreachable INPUT
cpu_dump_i.current.last_data_addr[31:0] Unreachable Unreachable Unreachable INPUT
cpu_dump_i.current.next_pc[31:0] Unreachable Unreachable Unreachable INPUT
cpu_dump_i.current.current_pc[31:0] Unreachable Unreachable Unreachable INPUT
cpu_dump_i.prev_exception_addr[31:0] Unreachable Unreachable Unreachable INPUT
cpu_dump_i.prev_exception_pc[31:0] Unreachable Unreachable Unreachable INPUT
cpu_dump_i.prev_valid Unreachable Unreachable Unreachable INPUT
scan_rst_ni Unreachable Unreachable Unreachable INPUT
scanmode_i[3:0] Unreachable Unreachable Unreachable INPUT
resets_o.rst_i2c2_n[1:0] Unreachable Unreachable Unreachable OUTPUT
resets_o.rst_i2c1_n[1:0] Unreachable Unreachable Unreachable OUTPUT
resets_o.rst_i2c0_n[1:0] Unreachable Unreachable Unreachable OUTPUT
resets_o.rst_usb_aon_n[1:0] Unreachable Unreachable Unreachable OUTPUT
resets_o.rst_usb_n[1:0] Unreachable Unreachable Unreachable OUTPUT
resets_o.rst_spi_host1_n[1:0] Unreachable Unreachable Unreachable OUTPUT
resets_o.rst_spi_host0_n[1:0] Unreachable Unreachable Unreachable OUTPUT
resets_o.rst_spi_device_n[1:0] Unreachable Unreachable Unreachable OUTPUT
resets_o.rst_sys_io_div4_n[1:0] Unreachable Unreachable Unreachable OUTPUT
resets_o.rst_sys_n[1:0] Unreachable Unreachable Unreachable OUTPUT
resets_o.rst_lc_usb_n[1:0] Yes Yes T19,T20,T41 Yes T4,T5,T6 OUTPUT
resets_o.rst_lc_io_div4_n[1:0] Yes Yes T19,T20,T41 Yes T4,T5,T6 OUTPUT
resets_o.rst_lc_io_div4_shadowed_n[1:0] Yes Yes T19,T20,T41 Yes T4,T5,T6 OUTPUT
resets_o.rst_lc_io_div2_n[1:0] Yes Yes T19,T20,T41 Yes T4,T5,T6 OUTPUT
resets_o.rst_lc_io_n[1:0] Yes Yes T19,T20,T41 Yes T4,T5,T6 OUTPUT
resets_o.rst_lc_aon_n[1:0] Unreachable Unreachable Unreachable OUTPUT
resets_o.rst_lc_n[1:0] Yes Yes T19,T20,T41 Yes T4,T5,T6 OUTPUT
resets_o.rst_lc_shadowed_n[1:0] Yes Yes T19,T20,T41 Yes T4,T5,T6 OUTPUT
resets_o.rst_por_usb_n[1:0] Unreachable Unreachable Unreachable OUTPUT
resets_o.rst_por_io_div4_n[1:0] Unreachable Unreachable Unreachable OUTPUT
resets_o.rst_por_io_div2_n[1:0] Unreachable Unreachable Unreachable OUTPUT
resets_o.rst_por_io_n[1:0] Unreachable Unreachable Unreachable OUTPUT
resets_o.rst_por_n[1:0] Unreachable Unreachable Unreachable OUTPUT
resets_o.rst_por_aon_n[1:0] Yes Yes T19,T20,T21 Yes T4,T5,T6 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%