Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : adc_ctrl
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.74 90.74

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_adc_ctrl_aon 90.74 90.74



Module Instance : tb.dut.top_earlgrey.u_adc_ctrl_aon

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.74 90.74


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.74 90.74


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.62 90.68 87.17 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : adc_ctrl
TotalCoveredPercent
Totals 37 29 78.38
Total Bits 324 294 90.74
Total Bits 0->1 162 147 90.74
Total Bits 1->0 162 147 90.74

Ports 37 29 78.38
Port Bits 324 294 90.74
Port Bits 0->1 162 147 90.74
Port Bits 1->0 162 147 90.74

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk_aon_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T19,T20,T41 Yes T4,T5,T6 INPUT
rst_aon_ni Yes Yes T19,T20,T41 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T8,T185,T77 Yes T8,T185,T77 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[2:1] No No No INPUT
tl_i.a_user.instr_type[3] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T8,T185,T77 Yes T8,T185,T77 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[1:0] No No No INPUT
tl_i.a_address[6:2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[17:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[18] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[21:19] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[22] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[29:23] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T20,*T60,*T9 Yes T20,T60,T9 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T38,T39,T40 Yes T38,T39,T40 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[0] Yes Yes *T60,*T9,*T61 Yes T60,T9,T61 INPUT
tl_i.a_opcode[1] No No No INPUT
tl_i.a_opcode[2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_valid Yes Yes T8,T125,T185 Yes T8,T125,T185 INPUT
tl_o.a_ready Yes Yes T8,T125,T185 Yes T8,T125,T185 OUTPUT
tl_o.d_error No No No OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T185,T77,T7 Yes T8,T185,T77 OUTPUT
tl_o.d_user.rsp_intg[1:0] Yes Yes T8,T185,T77 Yes T8,T125,T185 OUTPUT
tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
tl_o.d_user.rsp_intg[5:4] Yes Yes T8,T281,*T61 Yes T8,T125,T185 OUTPUT
tl_o.d_user.rsp_intg[6] No No No OUTPUT
tl_o.d_data[31:0] Yes Yes T8,T77,T281 Yes T8,T125,T185 OUTPUT
tl_o.d_sink No No No OUTPUT
tl_o.d_source[1:0] Yes Yes *T61,*T185,*T77 Yes T61,T8,T185 OUTPUT
tl_o.d_source[5:2] No No No OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[0] No No No OUTPUT
tl_o.d_size[1] Yes Yes T8,T281,T61 Yes T8,T125,T185 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T185,*T77,*T78 Yes T8,T185,T77 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T8,T125,T185 Yes T8,T125,T185 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T104,T68,T364 Yes T104,T68,T364 INPUT
alert_rx_i[0].ping_n Yes Yes T104,T68,T165 Yes T104,T68,T165 INPUT
alert_rx_i[0].ping_p Yes Yes T104,T68,T165 Yes T104,T68,T165 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T104,T68,T364 Yes T104,T68,T364 OUTPUT
adc_o.pd Yes Yes T77,T78,T7 Yes T77,T78,T7 OUTPUT
adc_o.channel_sel[1:0] Yes Yes T77,T78,T7 Yes T77,T78,T7 OUTPUT
adc_i.data_valid Yes Yes T77,T78,T7 Yes T77,T78,T7 INPUT
adc_i.data[9:0] Yes Yes T77,T7,T79 Yes T77,T7,T79 INPUT
intr_match_pending_o Yes Yes T185,T77,T79 Yes T185,T77,T79 OUTPUT
wkup_req_o Yes Yes T7,T79,T86 Yes T77,T7,T79 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%