Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	495165569	58554655	0	0
DepthKnown_A	495165569	495060158	0	0
RvalidKnown_A	495165569	495060158	0	0
WreadyKnown_A	495165569	495060158	0	0
gen_passthru_fifo.paramCheckPass	1002	1002	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	58554655	0	0
T4	91079	9550	0	0
T5	124600	136338	0	0
T6	97881	10896	0	0
T16	131328	9347	0	0
T19	260880	10237	0	0
T20	546848	361257	0	0
T41	945757	133279	0	0
T42	72475	8375	0	0
T54	125836	137552	0	0
T85	162295	16445	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	495060158	0	0
T4	91079	91021	0	0
T5	124600	124594	0	0
T6	97881	97819	0	0
T16	131328	131266	0	0
T19	260880	260760	0	0
T20	546848	546831	0	0
T41	945757	945655	0	0
T42	72475	72420	0	0
T54	125836	125830	0	0
T85	162295	162189	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	495060158	0	0
T4	91079	91021	0	0
T5	124600	124594	0	0
T6	97881	97819	0	0
T16	131328	131266	0	0
T19	260880	260760	0	0
T20	546848	546831	0	0
T41	945757	945655	0	0
T42	72475	72420	0	0
T54	125836	125830	0	0
T85	162295	162189	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	495060158	0	0
T4	91079	91021	0	0
T5	124600	124594	0	0
T6	97881	97819	0	0
T16	131328	131266	0	0
T19	260880	260760	0	0
T20	546848	546831	0	0
T41	945757	945655	0	0
T42	72475	72420	0	0
T54	125836	125830	0	0
T85	162295	162189	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1002	1002	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T41	1	1	0	0
T42	1	1	0	0
T54	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	495165569	44118528	0	0
DepthKnown_A	495165569	495060158	0	0
RvalidKnown_A	495165569	495060158	0	0
WreadyKnown_A	495165569	495060158	0	0
gen_passthru_fifo.paramCheckPass	1002	1002	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	44118528	0	0
T4	91079	7936	0	0
T5	124600	118757	0	0
T6	97881	8518	0	0
T16	131328	6386	0	0
T19	260880	8360	0	0
T20	546848	357102	0	0
T41	945757	126504	0	0
T42	72475	5882	0	0
T54	125836	119602	0	0
T85	162295	13189	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	495060158	0	0
T4	91079	91021	0	0
T5	124600	124594	0	0
T6	97881	97819	0	0
T16	131328	131266	0	0
T19	260880	260760	0	0
T20	546848	546831	0	0
T41	945757	945655	0	0
T42	72475	72420	0	0
T54	125836	125830	0	0
T85	162295	162189	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	495060158	0	0
T4	91079	91021	0	0
T5	124600	124594	0	0
T6	97881	97819	0	0
T16	131328	131266	0	0
T19	260880	260760	0	0
T20	546848	546831	0	0
T41	945757	945655	0	0
T42	72475	72420	0	0
T54	125836	125830	0	0
T85	162295	162189	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	495060158	0	0
T4	91079	91021	0	0
T5	124600	124594	0	0
T6	97881	97819	0	0
T16	131328	131266	0	0
T19	260880	260760	0	0
T20	546848	546831	0	0
T41	945757	945655	0	0
T42	72475	72420	0	0
T54	125836	125830	0	0
T85	162295	162189	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1002	1002	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T41	1	1	0	0
T42	1	1	0	0
T54	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	495165569	40917652	0	0
DepthKnown_A	495165569	495060158	0	0
RvalidKnown_A	495165569	495060158	0	0
WreadyKnown_A	495165569	495060158	0	0
gen_passthru_fifo.paramCheckPass	1002	1002	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	40917652	0	0
T4	91079	6164	0	0
T5	124600	187313	0	0
T6	97881	5378	0	0
T16	131328	5179	0	0
T19	260880	6357	0	0
T20	546848	379595	0	0
T41	945757	121117	0	0
T42	72475	4047	0	0
T54	125836	193923	0	0
T85	162295	10358	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	495060158	0	0
T4	91079	91021	0	0
T5	124600	124594	0	0
T6	97881	97819	0	0
T16	131328	131266	0	0
T19	260880	260760	0	0
T20	546848	546831	0	0
T41	945757	945655	0	0
T42	72475	72420	0	0
T54	125836	125830	0	0
T85	162295	162189	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	495060158	0	0
T4	91079	91021	0	0
T5	124600	124594	0	0
T6	97881	97819	0	0
T16	131328	131266	0	0
T19	260880	260760	0	0
T20	546848	546831	0	0
T41	945757	945655	0	0
T42	72475	72420	0	0
T54	125836	125830	0	0
T85	162295	162189	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	495060158	0	0
T4	91079	91021	0	0
T5	124600	124594	0	0
T6	97881	97819	0	0
T16	131328	131266	0	0
T19	260880	260760	0	0
T20	546848	546831	0	0
T41	945757	945655	0	0
T42	72475	72420	0	0
T54	125836	125830	0	0
T85	162295	162189	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1002	1002	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T41	1	1	0	0
T42	1	1	0	0
T54	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	495165569	34112399	0	0
DepthKnown_A	495165569	495060158	0	0
RvalidKnown_A	495165569	495060158	0	0
WreadyKnown_A	495165569	495060158	0	0
gen_passthru_fifo.paramCheckPass	1002	1002	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	34112399	0	0
T4	91079	6053	0	0
T5	124600	111566	0	0
T6	97881	5247	0	0
T16	131328	4968	0	0
T19	260880	6240	0	0
T20	546848	378864	0	0
T41	945757	120716	0	0
T42	72475	3920	0	0
T54	125836	113388	0	0
T85	162295	10133	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	495060158	0	0
T4	91079	91021	0	0
T5	124600	124594	0	0
T6	97881	97819	0	0
T16	131328	131266	0	0
T19	260880	260760	0	0
T20	546848	546831	0	0
T41	945757	945655	0	0
T42	72475	72420	0	0
T54	125836	125830	0	0
T85	162295	162189	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	495060158	0	0
T4	91079	91021	0	0
T5	124600	124594	0	0
T6	97881	97819	0	0
T16	131328	131266	0	0
T19	260880	260760	0	0
T20	546848	546831	0	0
T41	945757	945655	0	0
T42	72475	72420	0	0
T54	125836	125830	0	0
T85	162295	162189	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	495060158	0	0
T4	91079	91021	0	0
T5	124600	124594	0	0
T6	97881	97819	0	0
T16	131328	131266	0	0
T19	260880	260760	0	0
T20	546848	546831	0	0
T41	945757	945655	0	0
T42	72475	72420	0	0
T54	125836	125830	0	0
T85	162295	162189	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1002	1002	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T41	1	1	0	0
T42	1	1	0	0
T54	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	495165569	64848	0	0
DepthKnown_A	495165569	495060158	0	0
RvalidKnown_A	495165569	495060158	0	0
WreadyKnown_A	495165569	495060158	0	0
gen_passthru_fifo.paramCheckPass	1002	1002	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	64848	0	0
T4	91079	13	0	0
T5	124600	34	0	0
T6	97881	13	0	0
T16	131328	17	0	0
T19	260880	15	0	0
T20	546848	27	0	0
T41	945757	39	0	0
T42	72475	13	0	0
T54	125836	34	0	0
T85	162295	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	495060158	0	0
T4	91079	91021	0	0
T5	124600	124594	0	0
T6	97881	97819	0	0
T16	131328	131266	0	0
T19	260880	260760	0	0
T20	546848	546831	0	0
T41	945757	945655	0	0
T42	72475	72420	0	0
T54	125836	125830	0	0
T85	162295	162189	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	495060158	0	0
T4	91079	91021	0	0
T5	124600	124594	0	0
T6	97881	97819	0	0
T16	131328	131266	0	0
T19	260880	260760	0	0
T20	546848	546831	0	0
T41	945757	945655	0	0
T42	72475	72420	0	0
T54	125836	125830	0	0
T85	162295	162189	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	495060158	0	0
T4	91079	91021	0	0
T5	124600	124594	0	0
T6	97881	97819	0	0
T16	131328	131266	0	0
T19	260880	260760	0	0
T20	546848	546831	0	0
T41	945757	945655	0	0
T42	72475	72420	0	0
T54	125836	125830	0	0
T85	162295	162189	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1002	1002	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T41	1	1	0	0
T42	1	1	0	0
T54	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	495165569	64848	0	0
DepthKnown_A	495165569	495060158	0	0
RvalidKnown_A	495165569	495060158	0	0
WreadyKnown_A	495165569	495060158	0	0
gen_passthru_fifo.paramCheckPass	1002	1002	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	64848	0	0
T4	91079	13	0	0
T5	124600	34	0	0
T6	97881	13	0	0
T16	131328	17	0	0
T19	260880	15	0	0
T20	546848	27	0	0
T41	945757	39	0	0
T42	72475	13	0	0
T54	125836	34	0	0
T85	162295	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	495060158	0	0
T4	91079	91021	0	0
T5	124600	124594	0	0
T6	97881	97819	0	0
T16	131328	131266	0	0
T19	260880	260760	0	0
T20	546848	546831	0	0
T41	945757	945655	0	0
T42	72475	72420	0	0
T54	125836	125830	0	0
T85	162295	162189	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	495060158	0	0
T4	91079	91021	0	0
T5	124600	124594	0	0
T6	97881	97819	0	0
T16	131328	131266	0	0
T19	260880	260760	0	0
T20	546848	546831	0	0
T41	945757	945655	0	0
T42	72475	72420	0	0
T54	125836	125830	0	0
T85	162295	162189	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	495060158	0	0
T4	91079	91021	0	0
T5	124600	124594	0	0
T6	97881	97819	0	0
T16	131328	131266	0	0
T19	260880	260760	0	0
T20	546848	546831	0	0
T41	945757	945655	0	0
T42	72475	72420	0	0
T54	125836	125830	0	0
T85	162295	162189	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1002	1002	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T41	1	1	0	0
T42	1	1	0	0
T54	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	495165569	51202	0	0
DepthKnown_A	495165569	495060158	0	0
RvalidKnown_A	495165569	495060158	0	0
WreadyKnown_A	495165569	495060158	0	0
gen_passthru_fifo.paramCheckPass	1002	1002	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	51202	0	0
T4	91079	12	0	0
T5	124600	5	0	0
T6	97881	12	0	0
T16	131328	14	0	0
T19	260880	14	0	0
T20	546848	25	0	0
T41	945757	37	0	0
T42	72475	12	0	0
T54	125836	5	0	0
T85	162295	24	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	495060158	0	0
T4	91079	91021	0	0
T5	124600	124594	0	0
T6	97881	97819	0	0
T16	131328	131266	0	0
T19	260880	260760	0	0
T20	546848	546831	0	0
T41	945757	945655	0	0
T42	72475	72420	0	0
T54	125836	125830	0	0
T85	162295	162189	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	495060158	0	0
T4	91079	91021	0	0
T5	124600	124594	0	0
T6	97881	97819	0	0
T16	131328	131266	0	0
T19	260880	260760	0	0
T20	546848	546831	0	0
T41	945757	945655	0	0
T42	72475	72420	0	0
T54	125836	125830	0	0
T85	162295	162189	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	495060158	0	0
T4	91079	91021	0	0
T5	124600	124594	0	0
T6	97881	97819	0	0
T16	131328	131266	0	0
T19	260880	260760	0	0
T20	546848	546831	0	0
T41	945757	945655	0	0
T42	72475	72420	0	0
T54	125836	125830	0	0
T85	162295	162189	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1002	1002	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T41	1	1	0	0
T42	1	1	0	0
T54	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	495165569	51202	0	0
DepthKnown_A	495165569	495060158	0	0
RvalidKnown_A	495165569	495060158	0	0
WreadyKnown_A	495165569	495060158	0	0
gen_passthru_fifo.paramCheckPass	1002	1002	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	51202	0	0
T4	91079	12	0	0
T5	124600	5	0	0
T6	97881	12	0	0
T16	131328	14	0	0
T19	260880	14	0	0
T20	546848	25	0	0
T41	945757	37	0	0
T42	72475	12	0	0
T54	125836	5	0	0
T85	162295	24	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	495060158	0	0
T4	91079	91021	0	0
T5	124600	124594	0	0
T6	97881	97819	0	0
T16	131328	131266	0	0
T19	260880	260760	0	0
T20	546848	546831	0	0
T41	945757	945655	0	0
T42	72475	72420	0	0
T54	125836	125830	0	0
T85	162295	162189	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	495060158	0	0
T4	91079	91021	0	0
T5	124600	124594	0	0
T6	97881	97819	0	0
T16	131328	131266	0	0
T19	260880	260760	0	0
T20	546848	546831	0	0
T41	945757	945655	0	0
T42	72475	72420	0	0
T54	125836	125830	0	0
T85	162295	162189	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	495060158	0	0
T4	91079	91021	0	0
T5	124600	124594	0	0
T6	97881	97819	0	0
T16	131328	131266	0	0
T19	260880	260760	0	0
T20	546848	546831	0	0
T41	945757	945655	0	0
T42	72475	72420	0	0
T54	125836	125830	0	0
T85	162295	162189	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1002	1002	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T41	1	1	0	0
T42	1	1	0	0
T54	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	495165569	13646	0	0
DepthKnown_A	495165569	495060158	0	0
RvalidKnown_A	495165569	495060158	0	0
WreadyKnown_A	495165569	495060158	0	0
gen_passthru_fifo.paramCheckPass	1002	1002	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	13646	0	0
T4	91079	1	0	0
T5	124600	29	0	0
T6	97881	1	0	0
T16	131328	3	0	0
T19	260880	1	0	0
T20	546848	2	0	0
T41	945757	2	0	0
T42	72475	1	0	0
T54	125836	29	0	0
T85	162295	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	495060158	0	0
T4	91079	91021	0	0
T5	124600	124594	0	0
T6	97881	97819	0	0
T16	131328	131266	0	0
T19	260880	260760	0	0
T20	546848	546831	0	0
T41	945757	945655	0	0
T42	72475	72420	0	0
T54	125836	125830	0	0
T85	162295	162189	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	495060158	0	0
T4	91079	91021	0	0
T5	124600	124594	0	0
T6	97881	97819	0	0
T16	131328	131266	0	0
T19	260880	260760	0	0
T20	546848	546831	0	0
T41	945757	945655	0	0
T42	72475	72420	0	0
T54	125836	125830	0	0
T85	162295	162189	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	495060158	0	0
T4	91079	91021	0	0
T5	124600	124594	0	0
T6	97881	97819	0	0
T16	131328	131266	0	0
T19	260880	260760	0	0
T20	546848	546831	0	0
T41	945757	945655	0	0
T42	72475	72420	0	0
T54	125836	125830	0	0
T85	162295	162189	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1002	1002	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T41	1	1	0	0
T42	1	1	0	0
T54	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	495165569	13646	0	0
DepthKnown_A	495165569	495060158	0	0
RvalidKnown_A	495165569	495060158	0	0
WreadyKnown_A	495165569	495060158	0	0
gen_passthru_fifo.paramCheckPass	1002	1002	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	13646	0	0
T4	91079	1	0	0
T5	124600	29	0	0
T6	97881	1	0	0
T16	131328	3	0	0
T19	260880	1	0	0
T20	546848	2	0	0
T41	945757	2	0	0
T42	72475	1	0	0
T54	125836	29	0	0
T85	162295	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	495060158	0	0
T4	91079	91021	0	0
T5	124600	124594	0	0
T6	97881	97819	0	0
T16	131328	131266	0	0
T19	260880	260760	0	0
T20	546848	546831	0	0
T41	945757	945655	0	0
T42	72475	72420	0	0
T54	125836	125830	0	0
T85	162295	162189	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	495060158	0	0
T4	91079	91021	0	0
T5	124600	124594	0	0
T6	97881	97819	0	0
T16	131328	131266	0	0
T19	260880	260760	0	0
T20	546848	546831	0	0
T41	945757	945655	0	0
T42	72475	72420	0	0
T54	125836	125830	0	0
T85	162295	162189	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	495060158	0	0
T4	91079	91021	0	0
T5	124600	124594	0	0
T6	97881	97819	0	0
T16	131328	131266	0	0
T19	260880	260760	0	0
T20	546848	546831	0	0
T41	945757	945655	0	0
T42	72475	72420	0	0
T54	125836	125830	0	0
T85	162295	162189	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1002	1002	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T41	1	1	0	0
T42	1	1	0	0
T54	1	1	0	0
T85	1	1	0	0