Unified Coverage Report :: Module :: aon_timer

Module : aon_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.45			90.45

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_aon_timer_aon	90.45			90.45

---

Module Instance : tb.dut.top_earlgrey.u_aon_timer_aon

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.45			90.45

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.45			90.45

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.62	90.68		87.17			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : aon_timer

	Total	Covered	Percent
Totals	38	30	78.95
Total Bits	314	284	90.45
Total Bits 0->1	157	142	90.45
Total Bits 1->0	157	142	90.45

Ports	38	30	78.95
Port Bits	314	284	90.45
Port Bits 0->1	157	142	90.45
Port Bits 1->0	157	142	90.45

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_aon_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T19,T20,T41	Yes	T4,T5,T6	INPUT
rst_aon_ni	Yes	Yes	T19,T20,T41	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T5,T54,T18	Yes	T5,T54,T18	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T5,T54,T18	Yes	T5,T54,T18	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[18:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[21:19]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[22]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:23]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T20,*T60,*T9	Yes	T20,T60,T9	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T38,T39,T40	Yes	T38,T39,T40	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T60,*T9,*T61	Yes	T60,T9,T61	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_valid	Yes	Yes	T5,T54,T18	Yes	T5,T54,T18	INPUT
tl_o.a_ready	Yes	Yes	T5,T54,T18	Yes	T5,T54,T18	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T18,T112,T131	Yes	T18,T112,T131	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T5,T54,T18	Yes	T5,T54,T18	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T112,T131,T136	Yes	T5,T54,T18	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T5,T54,T18	Yes	T5,T54,T18	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T61,*T5,*T54	Yes	T61,T357,T155	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T112,T131,T136	Yes	T5,T54,T18	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T5,*T54,*T18	Yes	T5,T54,T18	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T5,T54,T18	Yes	T5,T54,T18	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T104,T68,T125	Yes	T104,T68,T125	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T104,T68,T165	Yes	T104,T68,T165	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T104,T68,T165	Yes	T104,T68,T165	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T104,T68,T125	Yes	T104,T68,T125	OUTPUT
lc_escalate_en_i[3:0]	Yes	Yes	T112,T131,T117	Yes	T112,T131,T117	INPUT
intr_wkup_timer_expired_o	Yes	Yes	T18,T271,T272	Yes	T18,T66,T271	OUTPUT
intr_wdog_timer_bark_o	Yes	Yes	T243,T67,T297	Yes	T243,T67,T297	OUTPUT
nmi_wdog_timer_bark_o	Yes	Yes	T243,T67,T297	Yes	T243,T67,T297	OUTPUT
wkup_req_o	Yes	Yes	T18,T243,T271	Yes	T18,T243,T66	OUTPUT
aon_timer_rst_req_o	Yes	Yes	T136,T243,T67	Yes	T136,T243,T67	OUTPUT
sleep_mode_i	Yes	Yes	T4,T5,T6	Yes	T19,T20,T18	INPUT

*Tests covering at least one bit in the range