Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.26			90.26

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart1	89.54			89.54
tb.dut.top_earlgrey.u_uart2	89.54			89.54
tb.dut.top_earlgrey.u_uart3	89.61			89.61
tb.dut.top_earlgrey.u_uart0	90.13			90.13

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.54			89.54

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.54			89.54

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.62	90.68		87.17			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.54			89.54

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.54			89.54

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.62	90.68		87.17			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.61			89.61

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.61			89.61

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.62	90.68		87.17			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.13			90.13

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.13			90.13

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.62	90.68		87.17			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	40	32	80.00
Total Bits	308	278	90.26
Total Bits 0->1	154	139	90.26
Total Bits 1->0	154	139	90.26

Ports	40	32	80.00
Port Bits	308	278	90.26
Port Bits 0->1	154	139	90.26
Port Bits 1->0	154	139	90.26

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T19,T20,T41	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T5,T54,T17	Yes	T5,T54,T17	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T5,T54,T17	Yes	T5,T54,T17	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T20,*T60,*T9	Yes	T20,T60,T9	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T38,T39,T40	Yes	T38,T39,T40	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T60,*T9,*T61	Yes	T60,T9,T61	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_valid	Yes	Yes	T5,T54,T17	Yes	T5,T54,T17	INPUT
tl_o.a_ready	Yes	Yes	T5,T54,T17	Yes	T5,T54,T17	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T17,T21,T101	Yes	T17,T21,T101	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T17,T21,T101	Yes	T5,T54,T17	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T51,T52,T53	Yes	T5,T54,T17	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T17,T21,T101	Yes	T5,T54,T17	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T119,*T120,*T357	Yes	T119,T120,T357	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T51,T52,T53	Yes	T5,T54,T17	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T17,*T21,*T101	Yes	T17,T21,T101	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T5,T54,T17	Yes	T5,T54,T17	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T104,T224,T68	Yes	T104,T224,T68	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T104,T224,T68	Yes	T104,T68,T221	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T104,T68,T221	Yes	T104,T224,T68	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T104,T224,T68	Yes	T104,T224,T68	OUTPUT
cio_rx_i	Yes	Yes	T19,T20,T41	Yes	T4,T6,T42	INPUT
cio_tx_o	Yes	Yes	T17,T21,T267	Yes	T17,T21,T267	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T17,T21,T101	Yes	T17,T21,T101	OUTPUT
intr_tx_empty_o	Yes	Yes	T17,T21,T101	Yes	T17,T21,T101	OUTPUT
intr_rx_watermark_o	Yes	Yes	T17,T21,T101	Yes	T17,T21,T101	OUTPUT
intr_tx_done_o	Yes	Yes	T17,T21,T101	Yes	T17,T21,T101	OUTPUT
intr_rx_overflow_o	Yes	Yes	T17,T21,T101	Yes	T17,T21,T101	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T181,T182,T183	Yes	T181,T182,T183	OUTPUT
intr_rx_break_err_o	Yes	Yes	T181,T182,T183	Yes	T181,T182,T183	OUTPUT
intr_rx_timeout_o	Yes	Yes	T181,T182,T183	Yes	T181,T182,T183	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T181,T182,T183	Yes	T181,T182,T183	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	40	32	80.00
Total Bits	306	274	89.54
Total Bits 0->1	153	137	89.54
Total Bits 1->0	153	137	89.54

Ports	40	32	80.00
Port Bits	306	274	89.54
Port Bits 0->1	153	137	89.54
Port Bits 1->0	153	137	89.54

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T19,T20,T41	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T173,T181,T182	Yes	T173,T181,T182	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T173,T181,T182	Yes	T173,T181,T182	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T20,*T60,*T9	Yes	T20,T60,T9	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T38,T39,T40	Yes	T38,T39,T40	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T60,*T9,*T61	Yes	T60,T9,T61	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_valid	Yes	Yes	T173,T181,T182	Yes	T173,T181,T182	INPUT
tl_o.a_ready	Yes	Yes	T173,T181,T182	Yes	T173,T181,T182	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T173,T181,T182	Yes	T173,T181,T182	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T173,T181,T182	Yes	T173,T181,T182	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T134,*T221,*T222	Yes	T173,T181,T182	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T173,T181,T182	Yes	T173,T181,T182	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[1]	Yes	Yes	*T173,*T181,*T182	Yes	T173,T181,T182	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T134,T221,T222	Yes	T173,T181,T182	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T173,*T181,*T182	Yes	T173,T181,T182	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T173,T181,T182	Yes	T173,T181,T182	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T104,T224,T68	Yes	T104,T224,T68	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T104,T224,T68	Yes	T104,T68,T165	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T104,T68,T165	Yes	T104,T224,T68	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T104,T224,T68	Yes	T104,T224,T68	OUTPUT
cio_rx_i	Yes	Yes	T173,T43,T341	Yes	T25,T173,T43	INPUT
cio_tx_o	Yes	Yes	T173,T341,T363	Yes	T173,T341,T363	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T173,T181,T182	Yes	T173,T181,T182	OUTPUT
intr_tx_empty_o	Yes	Yes	T173,T181,T182	Yes	T173,T181,T182	OUTPUT
intr_rx_watermark_o	Yes	Yes	T173,T181,T182	Yes	T173,T181,T182	OUTPUT
intr_tx_done_o	Yes	Yes	T173,T181,T182	Yes	T173,T181,T182	OUTPUT
intr_rx_overflow_o	Yes	Yes	T173,T181,T182	Yes	T173,T181,T182	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T181,T182,T183	Yes	T181,T182,T183	OUTPUT
intr_rx_break_err_o	Yes	Yes	T181,T182,T183	Yes	T181,T182,T183	OUTPUT
intr_rx_timeout_o	Yes	Yes	T181,T182,T183	Yes	T181,T182,T183	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T181,T182,T183	Yes	T181,T182,T183	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	40	32	80.00
Total Bits	306	274	89.54
Total Bits 0->1	153	137	89.54
Total Bits 1->0	153	137	89.54

Ports	40	32	80.00
Port Bits	306	274	89.54
Port Bits 0->1	153	137	89.54
Port Bits 1->0	153	137	89.54

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T19,T20,T41	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T17,T101,T268	Yes	T17,T101,T268	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T17,T101,T268	Yes	T17,T101,T268	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T20,*T60,*T9	Yes	T20,T60,T9	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T38,T39,T40	Yes	T38,T39,T40	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T60,*T9,*T61	Yes	T60,T9,T61	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_valid	Yes	Yes	T17,T101,T268	Yes	T17,T101,T268	INPUT
tl_o.a_ready	Yes	Yes	T17,T101,T268	Yes	T17,T101,T268	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T17,T101,T268	Yes	T17,T101,T268	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T17,T101,T268	Yes	T17,T101,T268	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T134,*T221,*T222	Yes	T17,T101,T268	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T17,T101,T268	Yes	T17,T101,T268	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[1]	Yes	Yes	*T17,*T101,*T268	Yes	T17,T101,T268	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T134,T221,T222	Yes	T17,T101,T268	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T17,*T101,*T268	Yes	T17,T101,T268	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T17,T101,T268	Yes	T17,T101,T268	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T104,T68,T125	Yes	T104,T68,T125	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T104,T68,T165	Yes	T104,T68,T165	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T104,T68,T165	Yes	T104,T68,T165	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T104,T68,T125	Yes	T104,T68,T125	OUTPUT
cio_rx_i	Yes	Yes	T17,T101,T268	Yes	T17,T101,T268	INPUT
cio_tx_o	Yes	Yes	T17,T101,T268	Yes	T17,T101,T268	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T17,T101,T268	Yes	T17,T101,T268	OUTPUT
intr_tx_empty_o	Yes	Yes	T17,T101,T268	Yes	T17,T101,T268	OUTPUT
intr_rx_watermark_o	Yes	Yes	T17,T101,T268	Yes	T17,T101,T268	OUTPUT
intr_tx_done_o	Yes	Yes	T17,T101,T268	Yes	T17,T101,T268	OUTPUT
intr_rx_overflow_o	Yes	Yes	T17,T101,T268	Yes	T17,T101,T268	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T181,T182,T183	Yes	T181,T182,T183	OUTPUT
intr_rx_break_err_o	Yes	Yes	T181,T182,T183	Yes	T181,T182,T183	OUTPUT
intr_rx_timeout_o	Yes	Yes	T181,T182,T183	Yes	T181,T182,T183	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T181,T182,T183	Yes	T181,T182,T183	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	40	32	80.00
Total Bits	308	276	89.61
Total Bits 0->1	154	138	89.61
Total Bits 1->0	154	138	89.61

Ports	40	32	80.00
Port Bits	308	276	89.61
Port Bits 0->1	154	138	89.61
Port Bits 1->0	154	138	89.61

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T19,T20,T41	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T28,T269,T270	Yes	T28,T269,T270	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T28,T269,T270	Yes	T28,T269,T270	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T20,*T60,*T9	Yes	T20,T60,T9	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T38,T39,T40	Yes	T38,T39,T40	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T60,*T9,*T61	Yes	T60,T9,T61	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_valid	Yes	Yes	T28,T269,T270	Yes	T28,T269,T270	INPUT
tl_o.a_ready	Yes	Yes	T28,T269,T270	Yes	T28,T269,T270	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T28,T269,T270	Yes	T28,T269,T270	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T28,T269,T270	Yes	T28,T269,T270	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T134,*T221,*T222	Yes	T28,T269,T270	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T28,T269,T270	Yes	T28,T269,T270	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[1]	Yes	Yes	*T28,*T269,*T270	Yes	T28,T269,T270	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T134,T221,T222	Yes	T28,T269,T270	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T28,*T269,*T270	Yes	T28,T269,T270	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T28,T269,T270	Yes	T28,T269,T270	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T104,T68,T125	Yes	T104,T68,T125	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T104,T68,T165	Yes	T104,T68,T165	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T104,T68,T165	Yes	T104,T68,T165	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T104,T68,T125	Yes	T104,T68,T125	OUTPUT
cio_rx_i	Yes	Yes	T28,T269,T270	Yes	T28,T269,T270	INPUT
cio_tx_o	Yes	Yes	T28,T269,T270	Yes	T28,T269,T270	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T28,T269,T270	Yes	T28,T269,T270	OUTPUT
intr_tx_empty_o	Yes	Yes	T28,T269,T270	Yes	T28,T269,T270	OUTPUT
intr_rx_watermark_o	Yes	Yes	T28,T269,T270	Yes	T28,T269,T270	OUTPUT
intr_tx_done_o	Yes	Yes	T28,T269,T270	Yes	T28,T269,T270	OUTPUT
intr_rx_overflow_o	Yes	Yes	T28,T269,T270	Yes	T28,T269,T270	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T181,T182,T183	Yes	T181,T182,T183	OUTPUT
intr_rx_break_err_o	Yes	Yes	T181,T182,T183	Yes	T181,T182,T183	OUTPUT
intr_rx_timeout_o	Yes	Yes	T181,T182,T183	Yes	T181,T182,T183	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T181,T182,T183	Yes	T181,T182,T183	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	40	32	80.00
Total Bits	304	274	90.13
Total Bits 0->1	152	137	90.13
Total Bits 1->0	152	137	90.13

Ports	40	32	80.00
Port Bits	304	274	90.13
Port Bits 0->1	152	137	90.13
Port Bits 1->0	152	137	90.13

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T19,T20,T41	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T5,T54,T21	Yes	T5,T54,T21	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T5,T54,T21	Yes	T5,T54,T21	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T20,*T60,*T9	Yes	T20,T60,T9	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T38,T39,T40	Yes	T38,T39,T40	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T60,*T9,*T61	Yes	T60,T9,T61	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_valid	Yes	Yes	T5,T54,T21	Yes	T5,T54,T21	INPUT
tl_o.a_ready	Yes	Yes	T5,T54,T21	Yes	T5,T54,T21	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T21,T267,T51	Yes	T21,T267,T51	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T21,T267,T51	Yes	T5,T54,T21	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T51,T52,T53	Yes	T5,T54,T21	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T21,T267,T51	Yes	T5,T54,T21	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T119,*T120,*T357	Yes	T119,T120,T357	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T51,T52,T53	Yes	T5,T54,T21	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T21,*T267,*T51	Yes	T21,T267,T51	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T5,T54,T21	Yes	T5,T54,T21	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T104,T68,T175	Yes	T104,T68,T175	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T104,T68,T221	Yes	T104,T68,T221	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T104,T68,T221	Yes	T104,T68,T221	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T104,T68,T175	Yes	T104,T68,T175	OUTPUT
cio_rx_i	Yes	Yes	T19,T20,T41	Yes	T4,T6,T42	INPUT
cio_tx_o	Yes	Yes	T21,T267,T51	Yes	T21,T267,T51	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T21,T267,T181	Yes	T21,T267,T181	OUTPUT
intr_tx_empty_o	Yes	Yes	T21,T267,T181	Yes	T21,T267,T181	OUTPUT
intr_rx_watermark_o	Yes	Yes	T21,T267,T181	Yes	T21,T267,T181	OUTPUT
intr_tx_done_o	Yes	Yes	T21,T267,T181	Yes	T21,T267,T181	OUTPUT
intr_rx_overflow_o	Yes	Yes	T21,T267,T181	Yes	T21,T267,T181	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T181,T182,T183	Yes	T181,T182,T183	OUTPUT
intr_rx_break_err_o	Yes	Yes	T181,T182,T183	Yes	T181,T182,T183	OUTPUT
intr_rx_timeout_o	Yes	Yes	T181,T182,T183	Yes	T181,T182,T183	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T181,T182,T183	Yes	T181,T182,T183	OUTPUT

*Tests covering at least one bit in the range