Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : xbar_main
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.76 80.76

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_xbar_main 80.76 80.76


Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.76 80.76


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.76 80.76


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.62 90.68 87.17 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : xbar_main
TotalCoveredPercent
Totals 550 300 54.55
Total Bits 6824 5511 80.76
Total Bits 0->1 3412 2756 80.77
Total Bits 1->0 3412 2755 80.74

Ports 550 300 54.55
Port Bits 6824 5511 80.76
Port Bits 0->1 3412 2756 80.77
Port Bits 1->0 3412 2755 80.74

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_main_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk_fixed_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk_usb_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk_spi_host0_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk_spi_host1_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_main_ni Yes Yes T19,T20,T41 Yes T4,T5,T6 INPUT
rst_fixed_ni Yes Yes T19,T20,T41 Yes T4,T5,T6 INPUT
rst_usb_ni Yes Yes T19,T20,T41 Yes T4,T5,T6 INPUT
rst_spi_host0_ni Yes Yes T19,T20,T41 Yes T4,T5,T6 INPUT
rst_spi_host1_ni Yes Yes T19,T20,T41 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__corei_i.d_ready No No No INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0] No No No INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0] No No No INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__corei_i.a_data[31:0] No No No INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0] No No No INPUT
tl_rv_core_ibex__corei_i.a_address[31:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__corei_i.a_source[2:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__corei_i.a_source[5:3] No No No INPUT
tl_rv_core_ibex__corei_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__corei_i.a_size[1:0] No No No INPUT
tl_rv_core_ibex__corei_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0] No No No INPUT
tl_rv_core_ibex__corei_i.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__corei_o.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__corei_o.d_error Yes Yes T112,T113,T114 Yes T112,T113,T114 OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[5:0] Yes Yes *T112,*T115,*T113 Yes T112,T115,T113 OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6] No No No OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__corei_o.d_sink No No No OUTPUT
tl_rv_core_ibex__corei_o.d_source[2:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:3] No No No OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__corei_o.d_size[0] No No No OUTPUT
tl_rv_core_ibex__corei_o.d_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__corei_o.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cored_i.d_ready Yes Yes T60,T9,T61 Yes T60,T9,T61 INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0] Yes Yes T9,T12,T116 Yes T9,T12,T116 INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cored_i.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cored_i.a_address[31:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cored_i.a_source[5:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cored_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cored_i.a_size[1:0] Yes Yes T9,T12,T116 Yes T9,T12,T116 INPUT
tl_rv_core_ibex__cored_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cored_i.a_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cored_i.a_opcode[1] No No No INPUT
tl_rv_core_ibex__cored_i.a_opcode[2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cored_i.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cored_o.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cored_o.d_error Yes Yes T112,T117,T67 Yes T112,T117,T67 OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[5:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6] No No No OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cored_o.d_sink No No No OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0] Yes Yes T38,T39,T40 Yes T38,T39,T40 OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cored_o.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_dm__sba_i.d_ready Yes Yes T19,T20,T85 Yes T4,T6,T54 INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0] Yes Yes T20,T58,T56 Yes T20,T58,T56 INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0] Yes Yes T19,T20,T85 Yes T4,T6,T54 INPUT
tl_rv_dm__sba_i.a_user.instr_type[0] Yes Yes *T19,*T20,*T85 Yes T4,T6,T54 INPUT
tl_rv_dm__sba_i.a_user.instr_type[2:1] No No No INPUT
tl_rv_dm__sba_i.a_user.instr_type[3] Yes Yes T19,T20,T85 Yes T4,T6,T54 INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__sba_i.a_data[31:0] Yes Yes T20,T58,T56 Yes T20,T58,T56 INPUT
tl_rv_dm__sba_i.a_mask[3:0] Yes Yes T19,T20,T85 Yes T4,T6,T54 INPUT
tl_rv_dm__sba_i.a_address[31:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__sba_i.a_source[5:0] No No No INPUT
tl_rv_dm__sba_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__sba_i.a_size[0] No No No INPUT
tl_rv_dm__sba_i.a_size[1] Yes Yes T19,T20,T85 Yes T4,T6,T54 INPUT
tl_rv_dm__sba_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__sba_i.a_opcode[1:0] No No No INPUT
tl_rv_dm__sba_i.a_opcode[2] Yes Yes T19,T20,T85 Yes T4,T6,T54 INPUT
tl_rv_dm__sba_i.a_valid Yes Yes T20,T58,T56 Yes T20,T58,T56 INPUT
tl_rv_dm__sba_o.a_ready Yes Yes T19,T20,T41 Yes T4,T5,T6 OUTPUT
tl_rv_dm__sba_o.d_error No No No OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0] Yes Yes T20,T58,T56 Yes T20,T58,T56 OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[1:0] Yes Yes T20,T58,T56 Yes T20,T58,T56 OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[2] No No No OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[5:3] Yes Yes T20,T58,T56 Yes T20,T58,T56 OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6] No No No OUTPUT
tl_rv_dm__sba_o.d_data[31:0] Yes Yes T58,T56,T98 Yes T58,T56,T98 OUTPUT
tl_rv_dm__sba_o.d_sink No No No OUTPUT
tl_rv_dm__sba_o.d_source[5:0] No No No OUTPUT
tl_rv_dm__sba_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__sba_o.d_size[0] No No No OUTPUT
tl_rv_dm__sba_o.d_size[1] Yes Yes T20,T58,T56 Yes T20,T58,T56 OUTPUT
tl_rv_dm__sba_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__sba_o.d_opcode[0] Yes Yes *T20,*T58,*T56 Yes T20,T58,T56 OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__sba_o.d_valid Yes Yes T20,T58,T56 Yes T20,T58,T56 OUTPUT
tl_rv_dm__regs_o.d_ready Yes Yes T19,T20,T41 Yes T4,T5,T6 OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0] Yes Yes T9,T12 Yes T9,T12 OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[0] Yes Yes *T9,*T12 Yes T9,T12 OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[1] No No No OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:2] Yes Yes T9,T12 Yes T9,T12 OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[0] Yes Yes *T9,*T12 Yes T9,T12 OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[2:1] No No No OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3] Yes Yes T9,T12 Yes T9,T12 OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__regs_o.a_data[31:0] Yes Yes T9,T12 Yes T9,T12 OUTPUT
tl_rv_dm__regs_o.a_mask[3:0] Yes Yes T9,T12 Yes T9,T12 OUTPUT
tl_rv_dm__regs_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__regs_o.a_source[0] Yes Yes *T9,*T12 Yes T9,T12 OUTPUT
tl_rv_dm__regs_o.a_source[5:1] No No No OUTPUT
tl_rv_dm__regs_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__regs_o.a_size[0] No No No OUTPUT
tl_rv_dm__regs_o.a_size[1] Yes Yes T9,T12 Yes T9,T12 OUTPUT
tl_rv_dm__regs_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__regs_o.a_opcode[1:0] No No No OUTPUT
tl_rv_dm__regs_o.a_opcode[2] Yes Yes T9,T12 Yes T9,T12 OUTPUT
tl_rv_dm__regs_o.a_valid Yes Yes T9,T12 Yes T9,T12 OUTPUT
tl_rv_dm__regs_i.a_ready Yes Yes T9,T12 Yes T9,T12 INPUT
tl_rv_dm__regs_i.d_error No No No INPUT
tl_rv_dm__regs_i.d_user.data_intg[4:0] Yes Yes *T9,*T12 Yes T9,T12 INPUT
tl_rv_dm__regs_i.d_user.data_intg[5] No No No INPUT
tl_rv_dm__regs_i.d_user.data_intg[6] Yes Yes T12 Yes T12 INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[1:0] Yes Yes T9,T12 Yes T9,T12 INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[3:2] No No No INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[5:4] Yes Yes T9,T12 Yes T9,T12 INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6] No No No INPUT
tl_rv_dm__regs_i.d_data[31:0] Yes Yes T9,T12 Yes T9,T12 INPUT
tl_rv_dm__regs_i.d_sink No No No INPUT
tl_rv_dm__regs_i.d_source[0] Yes Yes *T9,*T12 Yes T9,T12 INPUT
tl_rv_dm__regs_i.d_source[5:1] No No No INPUT
tl_rv_dm__regs_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__regs_i.d_size[0] No No No INPUT
tl_rv_dm__regs_i.d_size[1] Yes Yes T9,T12 Yes T9,T12 INPUT
tl_rv_dm__regs_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__regs_i.d_opcode[0] Yes Yes *T9,*T12 Yes T9,T12 INPUT
tl_rv_dm__regs_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__regs_i.d_valid Yes Yes T9,T12 Yes T9,T12 INPUT
tl_rv_dm__mem_o.d_ready Yes Yes T19,T20,T41 Yes T4,T5,T6 OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0] Yes Yes T118,T9,T119 Yes T118,T9,T119 OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0] Yes Yes T118,T9,T119 Yes T118,T9,T119 OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0] Yes Yes T118,T9,T119 Yes T118,T9,T119 OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__mem_o.a_data[31:0] Yes Yes T118,T9,T119 Yes T118,T9,T119 OUTPUT
tl_rv_dm__mem_o.a_mask[3:0] Yes Yes T118,T9,T119 Yes T118,T9,T119 OUTPUT
tl_rv_dm__mem_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__mem_o.a_source[4:0] Yes Yes *T118,*T119,*T120 Yes T118,T119,T120 OUTPUT
tl_rv_dm__mem_o.a_source[5] No No No OUTPUT
tl_rv_dm__mem_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__mem_o.a_size[0] No No No OUTPUT
tl_rv_dm__mem_o.a_size[1] Yes Yes T118,T9,T119 Yes T118,T9,T119 OUTPUT
tl_rv_dm__mem_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__mem_o.a_opcode[1:0] No No No OUTPUT
tl_rv_dm__mem_o.a_opcode[2] Yes Yes T118,T9,T119 Yes T118,T9,T119 OUTPUT
tl_rv_dm__mem_o.a_valid Yes Yes T118,T9,T119 Yes T118,T9,T119 OUTPUT
tl_rv_dm__mem_i.a_ready Yes Yes T4,T6,T54 Yes T4,T6,T54 INPUT
tl_rv_dm__mem_i.d_error Yes Yes T4,T6,T54 Yes T19,T20,T85 INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0] Yes Yes T118,T119,T120 Yes T118,T119,T120 INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[2:0] Yes Yes *T118,*T9,*T119 Yes T118,T9,T119 INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[3] No No No INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[5:4] Yes Yes *T9,*T121,*T122 Yes T118,T9,T119 INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6] No No No INPUT
tl_rv_dm__mem_i.d_data[31:0] Yes Yes T4,T6,T54 Yes T19,T20,T85 INPUT
tl_rv_dm__mem_i.d_sink No No No INPUT
tl_rv_dm__mem_i.d_source[4:0] Yes Yes *T118,*T119,*T120 Yes T118,T119,T120 INPUT
tl_rv_dm__mem_i.d_source[5] No No No INPUT
tl_rv_dm__mem_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__mem_i.d_size[0] No No No INPUT
tl_rv_dm__mem_i.d_size[1] Yes Yes T9,T121,T122 Yes T118,T9,T119 INPUT
tl_rv_dm__mem_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__mem_i.d_opcode[0] Yes Yes *T4,*T6,*T54 Yes T19,T20,T85 INPUT
tl_rv_dm__mem_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__mem_i.d_valid Yes Yes T118,T9,T119 Yes T118,T9,T119 INPUT
tl_rom_ctrl__rom_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0] Yes Yes T5,T54,T20 Yes T5,T54,T20 OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0] Yes Yes T123,T124,T60 Yes T123,T124,T60 OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__rom_o.a_source[4:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_rom_ctrl__rom_o.a_source[5] No No No OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__rom_o.a_size[0] No No No OUTPUT
tl_rom_ctrl__rom_o.a_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__rom_o.a_opcode[1:0] No No No OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rom_ctrl__rom_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rom_ctrl__rom_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rom_ctrl__rom_i.d_error No No No INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[1:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[3:2] No No No INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[4] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:5] No No No INPUT
tl_rom_ctrl__rom_i.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rom_ctrl__rom_i.d_sink No No No INPUT
tl_rom_ctrl__rom_i.d_source[4:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_rom_ctrl__rom_i.d_source[5] No No No INPUT
tl_rom_ctrl__rom_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__rom_i.d_size[0] No No No INPUT
tl_rom_ctrl__rom_i.d_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rom_ctrl__rom_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__rom_i.d_opcode[0] No No No INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__rom_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rom_ctrl__regs_o.d_ready Yes Yes T19,T20,T41 Yes T4,T5,T6 OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0] Yes Yes T125,T126,T9 Yes T125,T126,T9 OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0] Yes Yes T19,T127,T128 Yes T19,T127,T128 OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[0] Yes Yes *T19,*T127,*T128 Yes T19,T127,T128 OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[2:1] No No No OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3] Yes Yes T19,T127,T128 Yes T19,T127,T128 OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0] Yes Yes T125,T126,T9 Yes T125,T126,T9 OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0] Yes Yes T19,T127,T128 Yes T19,T127,T128 OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__regs_o.a_source[1:0] Yes Yes *T9,*T12,*T19 Yes T9,T12,T19 OUTPUT
tl_rom_ctrl__regs_o.a_source[5:2] No No No OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__regs_o.a_size[0] No No No OUTPUT
tl_rom_ctrl__regs_o.a_size[1] Yes Yes T19,T127,T128 Yes T19,T127,T128 OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__regs_o.a_opcode[1:0] No No No OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2] Yes Yes T19,T127,T128 Yes T19,T127,T128 OUTPUT
tl_rom_ctrl__regs_o.a_valid Yes Yes T19,T127,T128 Yes T19,T127,T128 OUTPUT
tl_rom_ctrl__regs_i.a_ready Yes Yes T19,T127,T128 Yes T19,T127,T128 INPUT
tl_rom_ctrl__regs_i.d_error No No No INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0] Yes Yes T19,T127,T128 Yes T19,T127,T128 INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[1:0] Yes Yes T9,T12,*T125 Yes T125,T126,T9 INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[3:2] No No No INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[5:4] Yes Yes T19,T129,T130 Yes T19,T127,T128 INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6] No No No INPUT
tl_rom_ctrl__regs_i.d_data[31:0] Yes Yes T19,T127,T128 Yes T19,T127,T128 INPUT
tl_rom_ctrl__regs_i.d_sink No No No INPUT
tl_rom_ctrl__regs_i.d_source[1:0] Yes Yes *T9,*T12,*T19 Yes T9,T12,T19 INPUT
tl_rom_ctrl__regs_i.d_source[5:2] No No No INPUT
tl_rom_ctrl__regs_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__regs_i.d_size[0] No No No INPUT
tl_rom_ctrl__regs_i.d_size[1] Yes Yes T19,T129,T130 Yes T19,T127,T128 INPUT
tl_rom_ctrl__regs_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__regs_i.d_opcode[0] Yes Yes *T19,*T129,*T130 Yes T19,T127,T128 INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__regs_i.d_valid Yes Yes T19,T127,T128 Yes T19,T127,T128 INPUT
tl_peri_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_peri_o.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_peri_o.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_peri_o.a_user.instr_type[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_peri_o.a_user.instr_type[2:1] No No No OUTPUT
tl_peri_o.a_user.instr_type[3] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_peri_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_peri_o.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_peri_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_peri_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_peri_o.a_source[5:0] Yes Yes *T20,*T60,*T9 Yes T20,T60,T9 OUTPUT
tl_peri_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_peri_o.a_size[1:0] Yes Yes T38,T39,T40 Yes T38,T39,T40 OUTPUT
tl_peri_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_peri_o.a_opcode[0] Yes Yes *T60,*T9,*T61 Yes T60,T9,T61 OUTPUT
tl_peri_o.a_opcode[1] No No No OUTPUT
tl_peri_o.a_opcode[2] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_peri_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_peri_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_peri_i.d_error Yes Yes T131,T117,T132 Yes T131,T117,T132 INPUT
tl_peri_i.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_peri_i.d_user.rsp_intg[5:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_peri_i.d_user.rsp_intg[6] No No No INPUT
tl_peri_i.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_peri_i.d_sink No No No INPUT
tl_peri_i.d_source[5:0] Yes Yes *T20,*T60,*T9 Yes T20,T60,T9 INPUT
tl_peri_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_peri_i.d_size[1:0] Yes Yes T38,T39,T40 Yes T38,T39,T40 INPUT
tl_peri_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_peri_i.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_peri_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_peri_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_spi_host0_o.d_ready Yes Yes T25,T26,T27 Yes T25,T26,T27 OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0] Yes Yes T25,T26,T27 Yes T25,T26,T27 OUTPUT
tl_spi_host0_o.a_user.cmd_intg[0] Yes Yes *T25,*T26,*T27 Yes T25,T26,T27 OUTPUT
tl_spi_host0_o.a_user.cmd_intg[1] No No No OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:2] Yes Yes T25,T26,T27 Yes T25,T26,T27 OUTPUT
tl_spi_host0_o.a_user.instr_type[0] Yes Yes *T25,*T26,*T27 Yes T25,T26,T27 OUTPUT
tl_spi_host0_o.a_user.instr_type[2:1] No No No OUTPUT
tl_spi_host0_o.a_user.instr_type[3] Yes Yes T25,T26,T27 Yes T25,T26,T27 OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host0_o.a_data[31:0] Yes Yes T25,T26,T27 Yes T25,T26,T27 OUTPUT
tl_spi_host0_o.a_mask[3:0] Yes Yes T25,T26,T27 Yes T25,T26,T27 OUTPUT
tl_spi_host0_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host0_o.a_source[0] No No No OUTPUT
tl_spi_host0_o.a_source[1] Yes Yes *T25,*T26,*T27 Yes T25,T26,T27 OUTPUT
tl_spi_host0_o.a_source[5:2] No No No OUTPUT
tl_spi_host0_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host0_o.a_size[0] No No No OUTPUT
tl_spi_host0_o.a_size[1] Yes Yes T25,T26,T27 Yes T25,T26,T27 OUTPUT
tl_spi_host0_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host0_o.a_opcode[0] Yes Yes *T106,*T107,*T108 Yes T106,T107,T108 OUTPUT
tl_spi_host0_o.a_opcode[1] No No No OUTPUT
tl_spi_host0_o.a_opcode[2] Yes Yes T25,T26,T27 Yes T25,T26,T27 OUTPUT
tl_spi_host0_o.a_valid Yes Yes T25,T26,T27 Yes T25,T26,T27 OUTPUT
tl_spi_host0_i.a_ready Yes Yes T25,T26,T27 Yes T25,T26,T27 INPUT
tl_spi_host0_i.d_error No No No INPUT
tl_spi_host0_i.d_user.data_intg[6:0] Yes Yes T25,T26,T27 Yes T25,T26,T27 INPUT
tl_spi_host0_i.d_user.rsp_intg[1:0] Yes Yes T25,T26,T27 Yes T25,T26,T27 INPUT
tl_spi_host0_i.d_user.rsp_intg[3:2] No No No INPUT
tl_spi_host0_i.d_user.rsp_intg[5:4] Yes Yes T25,T133,*T134 Yes T25,T26,T27 INPUT
tl_spi_host0_i.d_user.rsp_intg[6] No No No INPUT
tl_spi_host0_i.d_data[31:0] Yes Yes T25,T26,T27 Yes T25,T26,T27 INPUT
tl_spi_host0_i.d_sink No No No INPUT
tl_spi_host0_i.d_source[0] No No No INPUT
tl_spi_host0_i.d_source[1] Yes Yes *T25,*T26,*T27 Yes T25,T26,T27 INPUT
tl_spi_host0_i.d_source[5:2] No No No INPUT
tl_spi_host0_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_spi_host0_i.d_size[0] No No No INPUT
tl_spi_host0_i.d_size[1] Yes Yes T25,T133,T134 Yes T25,T26,T27 INPUT
tl_spi_host0_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_spi_host0_i.d_opcode[0] Yes Yes *T25,*T26,*T27 Yes T25,T26,T27 INPUT
tl_spi_host0_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_spi_host0_i.d_valid Yes Yes T25,T26,T27 Yes T25,T26,T27 INPUT
tl_spi_host1_o.d_ready Yes Yes T43,T133,T125 Yes T43,T133,T125 OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0] Yes Yes T43,T125,T109 Yes T43,T125,T109 OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0] Yes Yes T43,T133,T125 Yes T43,T133,T125 OUTPUT
tl_spi_host1_o.a_user.instr_type[0] Yes Yes *T43,*T133,*T125 Yes T43,T133,T125 OUTPUT
tl_spi_host1_o.a_user.instr_type[2:1] No No No OUTPUT
tl_spi_host1_o.a_user.instr_type[3] Yes Yes T43,T133,T125 Yes T43,T133,T125 OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host1_o.a_data[31:0] Yes Yes T43,T125,T109 Yes T43,T125,T109 OUTPUT
tl_spi_host1_o.a_mask[3:0] Yes Yes T43,T133,T125 Yes T43,T133,T125 OUTPUT
tl_spi_host1_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host1_o.a_source[0] No No No OUTPUT
tl_spi_host1_o.a_source[1] Yes Yes *T43,*T133,*T109 Yes T43,T133,T109 OUTPUT
tl_spi_host1_o.a_source[5:2] No No No OUTPUT
tl_spi_host1_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host1_o.a_size[0] No No No OUTPUT
tl_spi_host1_o.a_size[1] Yes Yes T43,T133,T125 Yes T43,T133,T125 OUTPUT
tl_spi_host1_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host1_o.a_opcode[1:0] No No No OUTPUT
tl_spi_host1_o.a_opcode[2] Yes Yes T43,T133,T109 Yes T43,T133,T109 OUTPUT
tl_spi_host1_o.a_valid Yes Yes T43,T133,T125 Yes T43,T133,T125 OUTPUT
tl_spi_host1_i.a_ready Yes Yes T43,T133,T125 Yes T43,T133,T125 INPUT
tl_spi_host1_i.d_error No No No INPUT
tl_spi_host1_i.d_user.data_intg[6:0] Yes Yes T43,T109,T110 Yes T43,T109,T110 INPUT
tl_spi_host1_i.d_user.rsp_intg[1:0] Yes Yes T43,T133,T109 Yes T43,T133,T125 INPUT
tl_spi_host1_i.d_user.rsp_intg[3:2] No No No INPUT
tl_spi_host1_i.d_user.rsp_intg[5:4] Yes Yes T43,T133,T135 Yes T43,T133,T125 INPUT
tl_spi_host1_i.d_user.rsp_intg[6] No No No INPUT
tl_spi_host1_i.d_data[31:0] Yes Yes T43,T109,T110 Yes T43,T109,T110 INPUT
tl_spi_host1_i.d_sink No No No INPUT
tl_spi_host1_i.d_source[0] No No No INPUT
tl_spi_host1_i.d_source[1] Yes Yes *T43,*T133,*T109 Yes T43,T133,T109 INPUT
tl_spi_host1_i.d_source[5:2] No No No INPUT
tl_spi_host1_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_spi_host1_i.d_size[0] No No No INPUT
tl_spi_host1_i.d_size[1] Yes Yes T43,T133,T135 Yes T43,T133,T125 INPUT
tl_spi_host1_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_spi_host1_i.d_opcode[0] Yes Yes *T43,*T133,*T109 Yes T43,T133,T109 INPUT
tl_spi_host1_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_spi_host1_i.d_valid Yes Yes T43,T133,T125 Yes T43,T133,T125 INPUT
tl_usbdev_o.d_ready Yes Yes T6,T30,T31 Yes T6,T30,T31 OUTPUT
tl_usbdev_o.a_user.data_intg[6:0] Yes Yes T6,T30,T31 Yes T6,T30,T31 OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0] Yes Yes T6,T30,T31 Yes T6,T30,T31 OUTPUT
tl_usbdev_o.a_user.instr_type[0] Yes Yes *T6,*T30,*T31 Yes T6,T30,T31 OUTPUT
tl_usbdev_o.a_user.instr_type[2:1] No No No OUTPUT
tl_usbdev_o.a_user.instr_type[3] Yes Yes T6,T30,T31 Yes T6,T30,T31 OUTPUT
tl_usbdev_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_usbdev_o.a_data[31:0] Yes Yes T6,T30,T31 Yes T6,T30,T31 OUTPUT
tl_usbdev_o.a_mask[3:0] Yes Yes T6,T30,T31 Yes T6,T30,T31 OUTPUT
tl_usbdev_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_usbdev_o.a_source[0] No No No OUTPUT
tl_usbdev_o.a_source[1] Yes Yes *T6,*T30,*T31 Yes T6,T30,T31 OUTPUT
tl_usbdev_o.a_source[5:2] No No No OUTPUT
tl_usbdev_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_usbdev_o.a_size[0] No No No OUTPUT
tl_usbdev_o.a_size[1] Yes Yes T6,T30,T31 Yes T6,T30,T31 OUTPUT
tl_usbdev_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_usbdev_o.a_opcode[1:0] No No No OUTPUT
tl_usbdev_o.a_opcode[2] Yes Yes T6,T30,T31 Yes T6,T30,T31 OUTPUT
tl_usbdev_o.a_valid Yes Yes T6,T30,T31 Yes T6,T30,T31 OUTPUT
tl_usbdev_i.a_ready Yes Yes T6,T30,T31 Yes T6,T30,T31 INPUT
tl_usbdev_i.d_error No No No INPUT
tl_usbdev_i.d_user.data_intg[6:0] Yes Yes T6,T30,T31 Yes T6,T30,T31 INPUT
tl_usbdev_i.d_user.rsp_intg[1:0] Yes Yes T6,T30,T31 Yes T6,T30,T31 INPUT
tl_usbdev_i.d_user.rsp_intg[3:2] No No No INPUT
tl_usbdev_i.d_user.rsp_intg[5:4] Yes Yes T30,T31,T133 Yes T6,T30,T31 INPUT
tl_usbdev_i.d_user.rsp_intg[6] No No No INPUT
tl_usbdev_i.d_data[31:0] Yes Yes T6,T30,T31 Yes T6,T30,T31 INPUT
tl_usbdev_i.d_sink No No No INPUT
tl_usbdev_i.d_source[0] No No No INPUT
tl_usbdev_i.d_source[1] Yes Yes *T6,*T30,*T31 Yes T6,T30,T31 INPUT
tl_usbdev_i.d_source[5:2] No No No INPUT
tl_usbdev_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_usbdev_i.d_size[0] No No No INPUT
tl_usbdev_i.d_size[1] Yes Yes T30,T31,T133 Yes T6,T30,T31 INPUT
tl_usbdev_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_usbdev_i.d_opcode[0] Yes Yes *T6,*T30,*T31 Yes T6,T30,T31 INPUT
tl_usbdev_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_usbdev_i.d_valid Yes Yes T6,T30,T31 Yes T6,T30,T31 INPUT
tl_flash_ctrl__core_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[2:1] No No No OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__core_o.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__core_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__core_o.a_source[0] No No No OUTPUT
tl_flash_ctrl__core_o.a_source[1] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__core_o.a_source[5:2] No No No OUTPUT
tl_flash_ctrl__core_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__core_o.a_size[0] No No No OUTPUT
tl_flash_ctrl__core_o.a_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__core_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__core_o.a_opcode[1:0] No No No OUTPUT
tl_flash_ctrl__core_o.a_opcode[2] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__core_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__core_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__core_i.d_error Yes Yes T4,T5,T6 Yes T19,T20,T41 INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[2:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[3] No No No INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[5:4] Yes Yes T5,T54,T19 Yes T4,T5,T6 INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6] No No No INPUT
tl_flash_ctrl__core_i.d_data[31:0] Yes Yes T4,T5,T6 Yes T5,T54,T19 INPUT
tl_flash_ctrl__core_i.d_sink No No No INPUT
tl_flash_ctrl__core_i.d_source[0] No No No INPUT
tl_flash_ctrl__core_i.d_source[1] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__core_i.d_source[5:2] No No No INPUT
tl_flash_ctrl__core_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__core_i.d_size[0] No No No INPUT
tl_flash_ctrl__core_i.d_size[1] Yes Yes T5,T54,T19 Yes T4,T5,T6 INPUT
tl_flash_ctrl__core_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__core_i.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__core_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__core_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__prim_o.d_ready Yes Yes T19,T20,T41 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0] No No No OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0] No No No OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0] No No No OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0] No No No OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0] No No No OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0] No No No OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0] No No No OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0] No No No OUTPUT
tl_flash_ctrl__prim_o.a_valid No No No OUTPUT
tl_flash_ctrl__prim_i.a_ready No No No INPUT
tl_flash_ctrl__prim_i.d_error No No No INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0] No No No INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0] No No No INPUT
tl_flash_ctrl__prim_i.d_data[31:0] No No No INPUT
tl_flash_ctrl__prim_i.d_sink No No No INPUT
tl_flash_ctrl__prim_i.d_source[5:0] No No No INPUT
tl_flash_ctrl__prim_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__prim_i.d_size[1:0] No No No INPUT
tl_flash_ctrl__prim_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__prim_i.d_opcode[0] No No No INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__prim_i.d_valid No No No INPUT
tl_flash_ctrl__mem_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0] Yes Yes T5,T6,T54 Yes T5,T6,T54 OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__mem_o.a_source[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__mem_o.a_source[1] No No No OUTPUT
tl_flash_ctrl__mem_o.a_source[4:2] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__mem_o.a_source[5] No No No OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__mem_o.a_size[0] No No No OUTPUT
tl_flash_ctrl__mem_o.a_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__mem_o.a_opcode[1:0] No No No OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__mem_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__mem_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__mem_i.d_error Yes Yes T4,T5,T6 Yes T19,T20,T41 INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[2:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[3] No No No INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[4] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:5] No No No INPUT
tl_flash_ctrl__mem_i.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__mem_i.d_sink No No No INPUT
tl_flash_ctrl__mem_i.d_source[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__mem_i.d_source[1] No No No INPUT
tl_flash_ctrl__mem_i.d_source[4:2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__mem_i.d_source[5] No No No INPUT
tl_flash_ctrl__mem_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__mem_i.d_size[0] No No No INPUT
tl_flash_ctrl__mem_i.d_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__mem_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__mem_i.d_opcode[0] No No No INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__mem_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_hmac_o.d_ready Yes Yes T5,T54,T19 Yes T4,T5,T6 OUTPUT
tl_hmac_o.a_user.data_intg[6:0] Yes Yes T5,T54,T55 Yes T5,T54,T55 OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0] Yes Yes T5,T54,T55 Yes T5,T54,T55 OUTPUT
tl_hmac_o.a_user.instr_type[0] Yes Yes *T5,*T54,*T136 Yes T5,T54,T136 OUTPUT
tl_hmac_o.a_user.instr_type[2:1] No No No OUTPUT
tl_hmac_o.a_user.instr_type[3] Yes Yes T5,T54,T136 Yes T5,T54,T136 OUTPUT
tl_hmac_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_hmac_o.a_data[31:0] Yes Yes T5,T54,T55 Yes T5,T54,T55 OUTPUT
tl_hmac_o.a_mask[3:0] Yes Yes T5,T54,T136 Yes T5,T54,T136 OUTPUT
tl_hmac_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_hmac_o.a_source[0] No No No OUTPUT
tl_hmac_o.a_source[1] Yes Yes *T5,*T54,*T136 Yes T5,T54,T136 OUTPUT
tl_hmac_o.a_source[5:2] No No No OUTPUT
tl_hmac_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_hmac_o.a_size[0] No No No OUTPUT
tl_hmac_o.a_size[1] Yes Yes T5,T54,T136 Yes T5,T54,T136 OUTPUT
tl_hmac_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_hmac_o.a_opcode[0] Yes Yes *T137,*T138,*T139 Yes T137,T138,T139 OUTPUT
tl_hmac_o.a_opcode[1] No No No OUTPUT
tl_hmac_o.a_opcode[2] Yes Yes T5,T54,T136 Yes T5,T54,T136 OUTPUT
tl_hmac_o.a_valid Yes Yes T5,T54,T136 Yes T5,T54,T136 OUTPUT
tl_hmac_i.a_ready Yes Yes T5,T54,T136 Yes T5,T54,T136 INPUT
tl_hmac_i.d_error No No No INPUT
tl_hmac_i.d_user.data_intg[6:0] Yes Yes T5,T54,T55 Yes T5,T54,T55 INPUT
tl_hmac_i.d_user.rsp_intg[1:0] Yes Yes T5,T54,T55 Yes T5,T54,T55 INPUT
tl_hmac_i.d_user.rsp_intg[3:2] No No No INPUT
tl_hmac_i.d_user.rsp_intg[5:4] Yes Yes T5,T54,T55 Yes T5,T54,T55 INPUT
tl_hmac_i.d_user.rsp_intg[6] No No No INPUT
tl_hmac_i.d_data[31:0] Yes Yes T5,T54,T55 Yes T5,T54,T55 INPUT
tl_hmac_i.d_sink No No No INPUT
tl_hmac_i.d_source[0] No No No INPUT
tl_hmac_i.d_source[1] Yes Yes *T5,*T54,*T55 Yes T5,T54,T55 INPUT
tl_hmac_i.d_source[5:2] No No No INPUT
tl_hmac_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_hmac_i.d_size[0] No No No INPUT
tl_hmac_i.d_size[1] Yes Yes T5,T54,T55 Yes T5,T54,T55 INPUT
tl_hmac_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_hmac_i.d_opcode[0] Yes Yes *T5,*T54,*T55 Yes T5,T54,T55 INPUT
tl_hmac_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_hmac_i.d_valid Yes Yes T5,T54,T55 Yes T5,T54,T55 INPUT
tl_kmac_o.d_ready Yes Yes T19,T20,T41 Yes T4,T5,T6 OUTPUT
tl_kmac_o.a_user.data_intg[6:0] Yes Yes T41,T140,T141 Yes T41,T140,T141 OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0] Yes Yes T41,T136,T142 Yes T41,T136,T142 OUTPUT
tl_kmac_o.a_user.instr_type[0] Yes Yes *T41,*T136,*T142 Yes T41,T136,T142 OUTPUT
tl_kmac_o.a_user.instr_type[2:1] No No No OUTPUT
tl_kmac_o.a_user.instr_type[3] Yes Yes T41,T136,T142 Yes T41,T136,T142 OUTPUT
tl_kmac_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_kmac_o.a_data[31:0] Yes Yes T41,T140,T141 Yes T41,T140,T141 OUTPUT
tl_kmac_o.a_mask[3:0] Yes Yes T41,T136,T142 Yes T41,T136,T142 OUTPUT
tl_kmac_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_kmac_o.a_source[1:0] Yes Yes *T9,*T41,*T136 Yes T9,T41,T136 OUTPUT
tl_kmac_o.a_source[5:2] No No No OUTPUT
tl_kmac_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_kmac_o.a_size[0] No No No OUTPUT
tl_kmac_o.a_size[1] Yes Yes T41,T136,T142 Yes T41,T136,T142 OUTPUT
tl_kmac_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_kmac_o.a_opcode[0] Yes Yes *T140,*T141,*T143 Yes T140,T141,T143 OUTPUT
tl_kmac_o.a_opcode[1] No No No OUTPUT
tl_kmac_o.a_opcode[2] Yes Yes T41,T136,T142 Yes T41,T136,T142 OUTPUT
tl_kmac_o.a_valid Yes Yes T41,T136,T142 Yes T41,T136,T142 OUTPUT
tl_kmac_i.a_ready Yes Yes T41,T136,T142 Yes T41,T136,T142 INPUT
tl_kmac_i.d_error No No No INPUT
tl_kmac_i.d_user.data_intg[6:0] Yes Yes T41,T136,T142 Yes T41,T136,T142 INPUT
tl_kmac_i.d_user.rsp_intg[1:0] Yes Yes T41,T136,T142 Yes T41,T136,T142 INPUT
tl_kmac_i.d_user.rsp_intg[3:2] No No No INPUT
tl_kmac_i.d_user.rsp_intg[5:4] Yes Yes *T136,T142,T144 Yes T41,T136,T142 INPUT
tl_kmac_i.d_user.rsp_intg[6] No No No INPUT
tl_kmac_i.d_data[31:0] Yes Yes T41,T142,T144 Yes T142,T144,T145 INPUT
tl_kmac_i.d_sink No No No INPUT
tl_kmac_i.d_source[1:0] Yes Yes *T9,*T41,*T136 Yes T9,T41,T136 INPUT
tl_kmac_i.d_source[5:2] No No No INPUT
tl_kmac_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_kmac_i.d_size[0] No No No INPUT
tl_kmac_i.d_size[1] Yes Yes T136,T142,T144 Yes T41,T136,T142 INPUT
tl_kmac_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_kmac_i.d_opcode[0] Yes Yes *T41,*T142,*T144 Yes T142,T144,T145 INPUT
tl_kmac_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_kmac_i.d_valid Yes Yes T41,T136,T142 Yes T41,T136,T142 INPUT
tl_aes_o.d_ready Yes Yes T42,T19,T20 Yes T4,T5,T6 OUTPUT
tl_aes_o.a_user.data_intg[6:0] Yes Yes T42,T83,T146 Yes T42,T83,T146 OUTPUT
tl_aes_o.a_user.cmd_intg[0] Yes Yes *T42,*T83,*T146 Yes T42,T83,T146 OUTPUT
tl_aes_o.a_user.cmd_intg[1] No No No OUTPUT
tl_aes_o.a_user.cmd_intg[6:2] Yes Yes T42,T83,T136 Yes T42,T83,T136 OUTPUT
tl_aes_o.a_user.instr_type[0] Yes Yes *T42,*T83,*T136 Yes T42,T83,T136 OUTPUT
tl_aes_o.a_user.instr_type[2:1] No No No OUTPUT
tl_aes_o.a_user.instr_type[3] Yes Yes T42,T83,T136 Yes T42,T83,T136 OUTPUT
tl_aes_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_aes_o.a_data[31:0] Yes Yes T42,T83,T146 Yes T42,T83,T146 OUTPUT
tl_aes_o.a_mask[3:0] Yes Yes T42,T83,T136 Yes T42,T83,T136 OUTPUT
tl_aes_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_aes_o.a_source[1:0] Yes Yes *T61,*T42,*T83 Yes T61,T42,T83 OUTPUT
tl_aes_o.a_source[5:2] No No No OUTPUT
tl_aes_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_aes_o.a_size[0] No No No OUTPUT
tl_aes_o.a_size[1] Yes Yes T42,T83,T136 Yes T42,T83,T136 OUTPUT
tl_aes_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_aes_o.a_opcode[1:0] No No No OUTPUT
tl_aes_o.a_opcode[2] Yes Yes T42,T83,T136 Yes T42,T83,T136 OUTPUT
tl_aes_o.a_valid Yes Yes T42,T83,T136 Yes T42,T83,T136 OUTPUT
tl_aes_i.a_ready Yes Yes T42,T83,T136 Yes T42,T83,T136 INPUT
tl_aes_i.d_error No No No INPUT
tl_aes_i.d_user.data_intg[6:0] Yes Yes T42,T83,T136 Yes T42,T83,T136 INPUT
tl_aes_i.d_user.rsp_intg[1:0] Yes Yes T42,T83,T84 Yes T42,T83,T84 INPUT
tl_aes_i.d_user.rsp_intg[3:2] No No No INPUT
tl_aes_i.d_user.rsp_intg[5:4] Yes Yes T136,T147,T148 Yes T42,T83,T136 INPUT
tl_aes_i.d_user.rsp_intg[6] No No No INPUT
tl_aes_i.d_data[31:0] Yes Yes T42,T83,T136 Yes T42,T83,T136 INPUT
tl_aes_i.d_sink No No No INPUT
tl_aes_i.d_source[1:0] Yes Yes *T61,*T42,*T83 Yes T61,T42,T83 INPUT
tl_aes_i.d_source[5:2] No No No INPUT
tl_aes_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_aes_i.d_size[0] No No No INPUT
tl_aes_i.d_size[1] Yes Yes T136,T147,T148 Yes T42,T83,T136 INPUT
tl_aes_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_aes_i.d_opcode[0] Yes Yes *T42,*T83,*T136 Yes T42,T83,T136 INPUT
tl_aes_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_aes_i.d_valid Yes Yes T42,T83,T136 Yes T42,T83,T136 INPUT
tl_entropy_src_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_entropy_src_o.a_user.instr_type[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_entropy_src_o.a_user.instr_type[2:1] No No No OUTPUT
tl_entropy_src_o.a_user.instr_type[3] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_entropy_src_o.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_entropy_src_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_entropy_src_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_entropy_src_o.a_source[0] No No No OUTPUT
tl_entropy_src_o.a_source[1] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_entropy_src_o.a_source[5:2] No No No OUTPUT
tl_entropy_src_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_entropy_src_o.a_size[0] No No No OUTPUT
tl_entropy_src_o.a_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_entropy_src_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_entropy_src_o.a_opcode[1:0] No No No OUTPUT
tl_entropy_src_o.a_opcode[2] Yes Yes T5,T54,T41 Yes T5,T54,T41 OUTPUT
tl_entropy_src_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_entropy_src_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_entropy_src_i.d_error No No No INPUT
tl_entropy_src_i.d_user.data_intg[6:0] Yes Yes T41,T83,T84 Yes T41,T83,T84 INPUT
tl_entropy_src_i.d_user.rsp_intg[1:0] Yes Yes T5,T54,T19 Yes T4,T5,T6 INPUT
tl_entropy_src_i.d_user.rsp_intg[3:2] No No No INPUT
tl_entropy_src_i.d_user.rsp_intg[5:4] Yes Yes *T19,*T20,T41 Yes T4,T5,T6 INPUT
tl_entropy_src_i.d_user.rsp_intg[6] No No No INPUT
tl_entropy_src_i.d_data[31:0] Yes Yes T5,T54,T19 Yes T4,T5,T6 INPUT
tl_entropy_src_i.d_sink No No No INPUT
tl_entropy_src_i.d_source[0] No No No INPUT
tl_entropy_src_i.d_source[1] Yes Yes *T5,*T54,*T19 Yes T4,T5,T6 INPUT
tl_entropy_src_i.d_source[5:2] No No No INPUT
tl_entropy_src_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_entropy_src_i.d_size[0] No No No INPUT
tl_entropy_src_i.d_size[1] Yes Yes T19,T20,T41 Yes T4,T5,T6 INPUT
tl_entropy_src_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_entropy_src_i.d_opcode[0] Yes Yes *T41,*T83,*T84 Yes T5,T54,T41 INPUT
tl_entropy_src_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_entropy_src_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_csrng_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_csrng_o.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_csrng_o.a_user.instr_type[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_csrng_o.a_user.instr_type[2:1] No No No OUTPUT
tl_csrng_o.a_user.instr_type[3] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_csrng_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_data[31:0] Yes Yes T41,T83,T84 Yes T41,T83,T84 OUTPUT
tl_csrng_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_csrng_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_source[1:0] Yes Yes *T61,*T41,*T83 Yes T61,T41,T83 OUTPUT
tl_csrng_o.a_source[5:2] No No No OUTPUT
tl_csrng_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_size[0] No No No OUTPUT
tl_csrng_o.a_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_csrng_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_opcode[1:0] No No No OUTPUT
tl_csrng_o.a_opcode[2] Yes Yes T41,T83,T84 Yes T41,T83,T84 OUTPUT
tl_csrng_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_csrng_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_csrng_i.d_error No No No INPUT
tl_csrng_i.d_user.data_intg[6:0] Yes Yes T41,T83,T84 Yes T41,T83,T84 INPUT
tl_csrng_i.d_user.rsp_intg[1:0] Yes Yes T19,T20,T41 Yes T4,T5,T6 INPUT
tl_csrng_i.d_user.rsp_intg[3:2] No No No INPUT
tl_csrng_i.d_user.rsp_intg[5:4] Yes Yes *T19,*T20,T41 Yes T4,T5,T6 INPUT
tl_csrng_i.d_user.rsp_intg[6] No No No INPUT
tl_csrng_i.d_data[31:0] Yes Yes T19,T20,T41 Yes T4,T5,T6 INPUT
tl_csrng_i.d_sink No No No INPUT
tl_csrng_i.d_source[1:0] Yes Yes *T61,*T41,*T83 Yes T61,T41,T83 INPUT
tl_csrng_i.d_source[5:2] No No No INPUT
tl_csrng_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_csrng_i.d_size[0] No No No INPUT
tl_csrng_i.d_size[1] Yes Yes T19,T20,T41 Yes T4,T5,T6 INPUT
tl_csrng_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_csrng_i.d_opcode[0] Yes Yes *T41,*T83,*T84 Yes T41,T83,T84 INPUT
tl_csrng_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_csrng_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_edn0_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_edn0_o.a_user.data_intg[6:0] Yes Yes T41,T83,T84 Yes T41,T83,T84 OUTPUT
tl_edn0_o.a_user.cmd_intg[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_edn0_o.a_user.cmd_intg[1] No No No OUTPUT
tl_edn0_o.a_user.cmd_intg[6:2] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_edn0_o.a_user.instr_type[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_edn0_o.a_user.instr_type[2:1] No No No OUTPUT
tl_edn0_o.a_user.instr_type[3] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_edn0_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn0_o.a_data[31:0] Yes Yes T41,T83,T84 Yes T41,T83,T84 OUTPUT
tl_edn0_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_edn0_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn0_o.a_source[0] No No No OUTPUT
tl_edn0_o.a_source[1] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_edn0_o.a_source[5:2] No No No OUTPUT
tl_edn0_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_edn0_o.a_size[0] No No No OUTPUT
tl_edn0_o.a_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_edn0_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn0_o.a_opcode[1:0] No No No OUTPUT
tl_edn0_o.a_opcode[2] Yes Yes T41,T83,T84 Yes T41,T83,T84 OUTPUT
tl_edn0_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_edn0_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_edn0_i.d_error No No No INPUT
tl_edn0_i.d_user.data_intg[0] Yes Yes *T41,*T83,*T84 Yes T41,T83,T84 INPUT
tl_edn0_i.d_user.data_intg[1] No No No INPUT
tl_edn0_i.d_user.data_intg[6:2] Yes Yes T41,T83,T84 Yes T41,T83,T84 INPUT
tl_edn0_i.d_user.rsp_intg[1:0] Yes Yes T19,T20,T41 Yes T4,T5,T6 INPUT
tl_edn0_i.d_user.rsp_intg[3:2] No No No INPUT
tl_edn0_i.d_user.rsp_intg[5:4] Yes Yes *T19,*T20,T41 Yes T4,T5,T6 INPUT
tl_edn0_i.d_user.rsp_intg[6] No No No INPUT
tl_edn0_i.d_data[31:0] Yes Yes T19,T20,T41 Yes T4,T5,T6 INPUT
tl_edn0_i.d_sink No No No INPUT
tl_edn0_i.d_source[0] No No No INPUT
tl_edn0_i.d_source[1] Yes Yes *T19,*T20,*T41 Yes T4,T5,T6 INPUT
tl_edn0_i.d_source[5:2] No No No INPUT
tl_edn0_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_edn0_i.d_size[0] No No No INPUT
tl_edn0_i.d_size[1] Yes Yes T19,T20,T41 Yes T4,T5,T6 INPUT
tl_edn0_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_edn0_i.d_opcode[0] Yes Yes *T41,*T83,*T84 Yes T41,T83,T84 INPUT
tl_edn0_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_edn0_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_edn1_o.d_ready Yes Yes T19,T20,T41 Yes T4,T5,T6 OUTPUT
tl_edn1_o.a_user.data_intg[6:0] Yes Yes T41,T83,T84 Yes T41,T83,T84 OUTPUT
tl_edn1_o.a_user.cmd_intg[0] Yes Yes *T41,*T83,*T84 Yes T41,T83,T84 OUTPUT
tl_edn1_o.a_user.cmd_intg[1] No No No OUTPUT
tl_edn1_o.a_user.cmd_intg[6:2] Yes Yes T41,T83,T84 Yes T41,T83,T84 OUTPUT
tl_edn1_o.a_user.instr_type[0] Yes Yes *T41,*T83,*T84 Yes T41,T83,T84 OUTPUT
tl_edn1_o.a_user.instr_type[2:1] No No No OUTPUT
tl_edn1_o.a_user.instr_type[3] Yes Yes T41,T83,T84 Yes T41,T83,T84 OUTPUT
tl_edn1_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn1_o.a_data[31:0] Yes Yes T41,T83,T84 Yes T41,T83,T84 OUTPUT
tl_edn1_o.a_mask[3:0] Yes Yes T41,T83,T84 Yes T41,T83,T84 OUTPUT
tl_edn1_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn1_o.a_source[0] No No No OUTPUT
tl_edn1_o.a_source[1] Yes Yes *T41,*T83,*T84 Yes T41,T83,T84 OUTPUT
tl_edn1_o.a_source[5:2] No No No OUTPUT
tl_edn1_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_edn1_o.a_size[0] No No No OUTPUT
tl_edn1_o.a_size[1] Yes Yes T41,T83,T84 Yes T41,T83,T84 OUTPUT
tl_edn1_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn1_o.a_opcode[1:0] No No No OUTPUT
tl_edn1_o.a_opcode[2] Yes Yes T41,T83,T84 Yes T41,T83,T84 OUTPUT
tl_edn1_o.a_valid Yes Yes T41,T83,T84 Yes T41,T83,T84 OUTPUT
tl_edn1_i.a_ready Yes Yes T41,T83,T84 Yes T41,T83,T84 INPUT
tl_edn1_i.d_error No No No INPUT
tl_edn1_i.d_user.data_intg[6:0] Yes Yes T41,T83,T84 Yes T41,T83,T84 INPUT
tl_edn1_i.d_user.rsp_intg[1:0] Yes Yes T41,T83,T84 Yes T41,T83,T84 INPUT
tl_edn1_i.d_user.rsp_intg[3:2] No No No INPUT
tl_edn1_i.d_user.rsp_intg[5:4] Yes Yes *T82,*T149,*T86 Yes T41,T83,T84 INPUT
tl_edn1_i.d_user.rsp_intg[6] No No No INPUT
tl_edn1_i.d_data[31:0] Yes Yes T41,T83,T84 Yes T41,T83,T84 INPUT
tl_edn1_i.d_sink No No No INPUT
tl_edn1_i.d_source[0] No No No INPUT
tl_edn1_i.d_source[1] Yes Yes *T41,*T83,*T84 Yes T41,T83,T84 INPUT
tl_edn1_i.d_source[5:2] No No No INPUT
tl_edn1_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_edn1_i.d_size[0] No No No INPUT
tl_edn1_i.d_size[1] Yes Yes T82,T149,T86 Yes T41,T83,T84 INPUT
tl_edn1_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_edn1_i.d_opcode[0] Yes Yes *T41,*T83,*T84 Yes T41,T83,T84 INPUT
tl_edn1_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_edn1_i.d_valid Yes Yes T41,T83,T84 Yes T41,T83,T84 INPUT
tl_rv_plic_o.d_ready Yes Yes T19,T20,T41 Yes T4,T5,T6 OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0] Yes Yes T16,T17,T18 Yes T16,T17,T18 OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0] Yes Yes T16,T17,T18 Yes T16,T17,T18 OUTPUT
tl_rv_plic_o.a_user.instr_type[0] Yes Yes *T16,*T17,*T18 Yes T16,T17,T18 OUTPUT
tl_rv_plic_o.a_user.instr_type[2:1] No No No OUTPUT
tl_rv_plic_o.a_user.instr_type[3] Yes Yes T16,T17,T18 Yes T16,T17,T18 OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_plic_o.a_data[31:0] Yes Yes T16,T17,T18 Yes T16,T17,T18 OUTPUT
tl_rv_plic_o.a_mask[3:0] Yes Yes T16,T17,T18 Yes T16,T17,T18 OUTPUT
tl_rv_plic_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_plic_o.a_source[0] No No No OUTPUT
tl_rv_plic_o.a_source[1] Yes Yes *T16,*T17,*T18 Yes T16,T17,T18 OUTPUT
tl_rv_plic_o.a_source[5:2] No No No OUTPUT
tl_rv_plic_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_plic_o.a_size[0] No No No OUTPUT
tl_rv_plic_o.a_size[1] Yes Yes T16,T17,T18 Yes T16,T17,T18 OUTPUT
tl_rv_plic_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_plic_o.a_opcode[1:0] No No No OUTPUT
tl_rv_plic_o.a_opcode[2] Yes Yes T16,T17,T18 Yes T16,T17,T18 OUTPUT
tl_rv_plic_o.a_valid Yes Yes T16,T17,T18 Yes T16,T17,T18 OUTPUT
tl_rv_plic_i.a_ready Yes Yes T16,T17,T18 Yes T16,T17,T18 INPUT
tl_rv_plic_i.d_error No No No INPUT
tl_rv_plic_i.d_user.data_intg[6:0] Yes Yes T16,T17,T18 Yes T16,T17,T18 INPUT
tl_rv_plic_i.d_user.rsp_intg[1:0] Yes Yes T16,T17,T18 Yes T16,T17,T18 INPUT
tl_rv_plic_i.d_user.rsp_intg[3:2] No No No INPUT
tl_rv_plic_i.d_user.rsp_intg[5:4] Yes Yes T112,T131,T117 Yes T16,T17,T18 INPUT
tl_rv_plic_i.d_user.rsp_intg[6] No No No INPUT
tl_rv_plic_i.d_data[31:0] Yes Yes T16,T17,T18 Yes T16,T17,T18 INPUT
tl_rv_plic_i.d_sink No No No INPUT
tl_rv_plic_i.d_source[0] No No No INPUT
tl_rv_plic_i.d_source[1] Yes Yes *T16,*T17,*T18 Yes T16,T17,T18 INPUT
tl_rv_plic_i.d_source[5:2] No No No INPUT
tl_rv_plic_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_plic_i.d_size[0] No No No INPUT
tl_rv_plic_i.d_size[1] Yes Yes T112,T131,T117 Yes T16,T17,T18 INPUT
tl_rv_plic_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_plic_i.d_opcode[0] Yes Yes *T16,*T17,*T18 Yes T16,T17,T18 INPUT
tl_rv_plic_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rv_plic_i.d_valid Yes Yes T16,T17,T18 Yes T16,T17,T18 INPUT
tl_otbn_o.d_ready Yes Yes T5,T54,T19 Yes T4,T5,T6 OUTPUT
tl_otbn_o.a_user.data_intg[6:0] Yes Yes T5,T54,T55 Yes T5,T54,T55 OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0] Yes Yes T5,T54,T136 Yes T5,T54,T136 OUTPUT
tl_otbn_o.a_user.instr_type[0] Yes Yes *T5,*T54,*T136 Yes T5,T54,T136 OUTPUT
tl_otbn_o.a_user.instr_type[2:1] No No No OUTPUT
tl_otbn_o.a_user.instr_type[3] Yes Yes T5,T54,T136 Yes T5,T54,T136 OUTPUT
tl_otbn_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_otbn_o.a_data[31:0] Yes Yes T5,T54,T55 Yes T5,T54,T55 OUTPUT
tl_otbn_o.a_mask[3:0] Yes Yes T5,T54,T136 Yes T5,T54,T136 OUTPUT
tl_otbn_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_otbn_o.a_source[1:0] Yes Yes *T60,*T9,*T150 Yes T60,T9,T150 OUTPUT
tl_otbn_o.a_source[5:2] No No No OUTPUT
tl_otbn_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_otbn_o.a_size[0] No No No OUTPUT
tl_otbn_o.a_size[1] Yes Yes T5,T54,T136 Yes T5,T54,T136 OUTPUT
tl_otbn_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_otbn_o.a_opcode[1:0] No No No OUTPUT
tl_otbn_o.a_opcode[2] Yes Yes T5,T54,T136 Yes T5,T54,T136 OUTPUT
tl_otbn_o.a_valid Yes Yes T5,T54,T136 Yes T5,T54,T136 OUTPUT
tl_otbn_i.a_ready Yes Yes T5,T54,T136 Yes T5,T54,T136 INPUT
tl_otbn_i.d_error No No No INPUT
tl_otbn_i.d_user.data_intg[6:0] Yes Yes T5,T54,T55 Yes T5,T54,T55 INPUT
tl_otbn_i.d_user.rsp_intg[1:0] Yes Yes T5,T54,T136 Yes T5,T54,T136 INPUT
tl_otbn_i.d_user.rsp_intg[3:2] No No No INPUT
tl_otbn_i.d_user.rsp_intg[5:4] Yes Yes T5,T54,*T136 Yes T5,T54,T136 INPUT
tl_otbn_i.d_user.rsp_intg[6] No No No INPUT
tl_otbn_i.d_data[31:0] Yes Yes T5,T54,T136 Yes T5,T54,T136 INPUT
tl_otbn_i.d_sink No No No INPUT
tl_otbn_i.d_source[1:0] Yes Yes *T60,*T9,*T150 Yes T60,T9,T150 INPUT
tl_otbn_i.d_source[5:2] No No No INPUT
tl_otbn_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_otbn_i.d_size[0] No No No INPUT
tl_otbn_i.d_size[1] Yes Yes T5,T54,T136 Yes T5,T54,T136 INPUT
tl_otbn_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_otbn_i.d_opcode[0] Yes Yes *T5,*T54,*T55 Yes T5,T54,T55 INPUT
tl_otbn_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_otbn_i.d_valid Yes Yes T5,T54,T136 Yes T5,T54,T136 INPUT
tl_keymgr_o.d_ready Yes Yes T5,T54,T19 Yes T4,T5,T6 OUTPUT
tl_keymgr_o.a_user.data_intg[6:0] Yes Yes T5,T54,T41 Yes T5,T54,T41 OUTPUT
tl_keymgr_o.a_user.cmd_intg[0] Yes Yes *T5,*T54,*T41 Yes T5,T54,T41 OUTPUT
tl_keymgr_o.a_user.cmd_intg[1] No No No OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:2] Yes Yes T5,T54,T41 Yes T5,T54,T41 OUTPUT
tl_keymgr_o.a_user.instr_type[0] Yes Yes *T5,*T54,*T41 Yes T5,T54,T41 OUTPUT
tl_keymgr_o.a_user.instr_type[2:1] No No No OUTPUT
tl_keymgr_o.a_user.instr_type[3] Yes Yes T5,T54,T41 Yes T5,T54,T41 OUTPUT
tl_keymgr_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_keymgr_o.a_data[31:0] Yes Yes T5,T41,T55 Yes T5,T41,T55 OUTPUT
tl_keymgr_o.a_mask[3:0] Yes Yes T5,T54,T41 Yes T5,T54,T41 OUTPUT
tl_keymgr_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_keymgr_o.a_source[0] No No No OUTPUT
tl_keymgr_o.a_source[1] Yes Yes *T5,*T54,*T41 Yes T5,T54,T41 OUTPUT
tl_keymgr_o.a_source[5:2] No No No OUTPUT
tl_keymgr_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_keymgr_o.a_size[0] No No No OUTPUT
tl_keymgr_o.a_size[1] Yes Yes T5,T54,T41 Yes T5,T54,T41 OUTPUT
tl_keymgr_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_keymgr_o.a_opcode[1:0] No No No OUTPUT
tl_keymgr_o.a_opcode[2] Yes Yes T5,T54,T41 Yes T5,T54,T41 OUTPUT
tl_keymgr_o.a_valid Yes Yes T5,T54,T41 Yes T5,T54,T41 OUTPUT
tl_keymgr_i.a_ready Yes Yes T5,T54,T41 Yes T5,T54,T41 INPUT
tl_keymgr_i.d_error No No No INPUT
tl_keymgr_i.d_user.data_intg[6:0] Yes Yes T54,T41,T142 Yes T54,T41,T142 INPUT
tl_keymgr_i.d_user.rsp_intg[1:0] Yes Yes T5,T54,T41 Yes T5,T54,T41 INPUT
tl_keymgr_i.d_user.rsp_intg[3:2] No No No INPUT
tl_keymgr_i.d_user.rsp_intg[5:4] Yes Yes T142,T144,T145 Yes T5,T54,T41 INPUT
tl_keymgr_i.d_user.rsp_intg[6] No No No INPUT
tl_keymgr_i.d_data[31:0] Yes Yes T5,T54,T41 Yes T5,T54,T41 INPUT
tl_keymgr_i.d_sink No No No INPUT
tl_keymgr_i.d_source[0] No No No INPUT
tl_keymgr_i.d_source[1] Yes Yes *T5,*T54,*T41 Yes T5,T54,T41 INPUT
tl_keymgr_i.d_source[5:2] No No No INPUT
tl_keymgr_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_keymgr_i.d_size[0] No No No INPUT
tl_keymgr_i.d_size[1] Yes Yes T142,T144,T145 Yes T5,T54,T41 INPUT
tl_keymgr_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_keymgr_i.d_opcode[0] Yes Yes *T5,*T54,*T41 Yes T5,T54,T41 INPUT
tl_keymgr_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_keymgr_i.d_valid Yes Yes T5,T54,T41 Yes T5,T54,T41 INPUT
tl_rv_core_ibex__cfg_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[1] No No No OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:2] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[2:1] No No No OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cfg_o.a_source[1:0] Yes Yes *T9,*T12,*T4 Yes T9,T12,T4 OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:2] No No No OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cfg_o.a_size[0] No No No OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[1:0] No No No OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cfg_i.d_error Yes Yes T9,T12 Yes T9,T12 INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0] Yes Yes T5,T54,T16 Yes T5,T54,T16 INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[2:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[3] No No No INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[5:4] Yes Yes T19,T20,T41 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6] No No No INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0] Yes Yes T5,T54,T16 Yes T5,T54,T16 INPUT
tl_rv_core_ibex__cfg_i.d_sink No No No INPUT
tl_rv_core_ibex__cfg_i.d_source[1:0] Yes Yes *T9,*T12,*T4 Yes T9,T12,T4 INPUT
tl_rv_core_ibex__cfg_i.d_source[5:2] No No No INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cfg_i.d_size[0] No No No INPUT
tl_rv_core_ibex__cfg_i.d_size[1] Yes Yes T19,T20,T41 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cfg_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_sram_ctrl_main__regs_o.d_ready Yes Yes T5,T54,T19 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0] Yes Yes T5,T54,T55 Yes T5,T54,T55 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[0] Yes Yes *T5,*T54,*T55 Yes T5,T54,T55 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[1] No No No OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:2] Yes Yes T151,T152,T153 Yes T151,T152,T153 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[0] Yes Yes *T5,*T54,*T55 Yes T5,T54,T55 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[2:1] No No No OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3] Yes Yes T5,T54,T55 Yes T5,T54,T55 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__regs_o.a_data[3:0] Yes Yes *T5,*T54,*T55 Yes T5,T54,T55 OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:4] No No No OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0] Yes Yes T5,T54,T55 Yes T5,T54,T55 OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__regs_o.a_source[1:0] Yes Yes *T154,*T155,*T5 Yes T154,T155,T5 OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:2] No No No OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__regs_o.a_size[0] No No No OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1] Yes Yes T5,T54,T55 Yes T5,T54,T55 OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[1:0] No No No OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2] Yes Yes T151,T152,T153 Yes T151,T152,T153 OUTPUT
tl_sram_ctrl_main__regs_o.a_valid Yes Yes T5,T54,T55 Yes T5,T54,T55 OUTPUT
tl_sram_ctrl_main__regs_i.a_ready Yes Yes T5,T54,T55 Yes T5,T54,T55 INPUT
tl_sram_ctrl_main__regs_i.d_error No No No INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[5:0] Yes Yes *T156,*T157,*T158 Yes T156,T157,T158 INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6] No No No INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[1:0] Yes Yes T51,T151,T52 Yes T5,T54,T55 INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[3:2] No No No INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[5:4] Yes Yes *T51,T151,*T52 Yes T5,T54,T55 INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6] No No No INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0] Yes Yes T51,T151,T52 Yes T5,T54,T55 INPUT
tl_sram_ctrl_main__regs_i.d_sink No No No INPUT
tl_sram_ctrl_main__regs_i.d_source[0] No No Yes T154,T155 INPUT
tl_sram_ctrl_main__regs_i.d_source[1] Yes Yes *T51,*T151,*T52 Yes T5,T54,T55 INPUT
tl_sram_ctrl_main__regs_i.d_source[5:2] No No No INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__regs_i.d_size[0] No No No INPUT
tl_sram_ctrl_main__regs_i.d_size[1] Yes Yes T51,T151,T52 Yes T5,T54,T55 INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0] Yes Yes *T151,*T153,*T73 Yes T151,T152,T153 INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__regs_i.d_valid Yes Yes T5,T54,T55 Yes T5,T54,T55 INPUT
tl_sram_ctrl_main__ram_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__ram_o.a_source[4:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5] No No No OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__ram_o.a_size[0] No No No OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[1] No No No OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_sram_ctrl_main__ram_i.d_error Yes Yes T4,T5,T6 Yes T19,T20,T41 INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[2:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[3] No No No INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[5:4] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6] No No No INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_sram_ctrl_main__ram_i.d_sink No No No INPUT
tl_sram_ctrl_main__ram_i.d_source[4:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_sram_ctrl_main__ram_i.d_source[5] No No No INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__ram_i.d_size[0] No No No INPUT
tl_sram_ctrl_main__ram_i.d_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__ram_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
scanmode_i[3:0] Unreachable Unreachable Unreachable INPUT

*Tests covering at least one bit in the range
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