Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	93.33			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	96.55	100.00	93.33			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	93.33			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	93.33			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T332,T336
0	1	Covered	T9,T332,T336
1	0	Covered	T12

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T332,T336,T12
1	Covered	T9,T332,T336

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T332,T336,T12
1	Covered	T9,T332,T336

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T9,T332,T336
1	1	Covered	T332,T336,T12

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T332,T336
1	0	Covered	T332,T336,T12
1	1	Covered	T9,T332,T336

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T9,T332,T336

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T332,T336
0	Covered	T332,T336,T12

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T332,T336
0	Covered	T332,T336,T12

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	990331138	973151380	0	0
CheckNGreaterZero_A	2004	2004	0	0
GntImpliesReady_A	990331138	8456	0	0
GntImpliesValid_A	990331138	8456	0	0
GrantKnown_A	990331138	973151380	0	0
IdxKnown_A	990331138	973151380	0	0
IndexIsCorrect_A	990331138	8456	0	0
NoReadyValidNoGrant_A	990331138	0	0	0
Priority_A	990331138	8456	0	0
ReadyAndValidImplyGrant_A	990331138	8456	0	0
ReqAndReadyImplyGrant_A	990331138	8456	0	0
ReqImpliesValid_A	990331138	8456	0	0
ValidKnown_A	990331138	973151380	0	0
gen_data_port_assertion.DataFlow_A	990331138	8456	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	990331138	973151380	0	0
T4	182158	182042	0	0
T5	249200	249188	0	0
T6	195762	195638	0	0
T16	262656	262532	0	0
T19	521760	521520	0	0
T20	1093696	1093662	0	0
T41	1891514	1891310	0	0
T42	144950	144840	0	0
T54	251672	251660	0	0
T85	324590	324378	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2004	2004	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T16	2	2	0	0
T19	2	2	0	0
T20	2	2	0	0
T41	2	2	0	0
T42	2	2	0	0
T54	2	2	0	0
T85	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	990331138	8456	0	0
T44	176438	0	0	0
T253	175268	0	0	0
T293	411592	0	0	0
T332	221754	2819	0	0
T333	549570	0	0	0
T334	309968	0	0	0
T335	247644	0	0	0
T336	0	2814	0	0
T337	0	2823	0	0
T423	153702	0	0	0
T424	288438	0	0	0
T425	273664	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	990331138	8456	0	0
T44	176438	0	0	0
T253	175268	0	0	0
T293	411592	0	0	0
T332	221754	2819	0	0
T333	549570	0	0	0
T334	309968	0	0	0
T335	247644	0	0	0
T336	0	2814	0	0
T337	0	2823	0	0
T423	153702	0	0	0
T424	288438	0	0	0
T425	273664	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	990331138	973151380	0	0
T4	182158	182042	0	0
T5	249200	249188	0	0
T6	195762	195638	0	0
T16	262656	262532	0	0
T19	521760	521520	0	0
T20	1093696	1093662	0	0
T41	1891514	1891310	0	0
T42	144950	144840	0	0
T54	251672	251660	0	0
T85	324590	324378	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	990331138	973151380	0	0
T4	182158	182042	0	0
T5	249200	249188	0	0
T6	195762	195638	0	0
T16	262656	262532	0	0
T19	521760	521520	0	0
T20	1093696	1093662	0	0
T41	1891514	1891310	0	0
T42	144950	144840	0	0
T54	251672	251660	0	0
T85	324590	324378	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	990331138	8456	0	0
T44	176438	0	0	0
T253	175268	0	0	0
T293	411592	0	0	0
T332	221754	2819	0	0
T333	549570	0	0	0
T334	309968	0	0	0
T335	247644	0	0	0
T336	0	2814	0	0
T337	0	2823	0	0
T423	153702	0	0	0
T424	288438	0	0	0
T425	273664	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	990331138	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	990331138	8456	0	0
T44	176438	0	0	0
T253	175268	0	0	0
T293	411592	0	0	0
T332	221754	2819	0	0
T333	549570	0	0	0
T334	309968	0	0	0
T335	247644	0	0	0
T336	0	2814	0	0
T337	0	2823	0	0
T423	153702	0	0	0
T424	288438	0	0	0
T425	273664	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	990331138	8456	0	0
T44	176438	0	0	0
T253	175268	0	0	0
T293	411592	0	0	0
T332	221754	2819	0	0
T333	549570	0	0	0
T334	309968	0	0	0
T335	247644	0	0	0
T336	0	2814	0	0
T337	0	2823	0	0
T423	153702	0	0	0
T424	288438	0	0	0
T425	273664	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	990331138	8456	0	0
T44	176438	0	0	0
T253	175268	0	0	0
T293	411592	0	0	0
T332	221754	2819	0	0
T333	549570	0	0	0
T334	309968	0	0	0
T335	247644	0	0	0
T336	0	2814	0	0
T337	0	2823	0	0
T423	153702	0	0	0
T424	288438	0	0	0
T425	273664	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	990331138	8456	0	0
T44	176438	0	0	0
T253	175268	0	0	0
T293	411592	0	0	0
T332	221754	2819	0	0
T333	549570	0	0	0
T334	309968	0	0	0
T335	247644	0	0	0
T336	0	2814	0	0
T337	0	2823	0	0
T423	153702	0	0	0
T424	288438	0	0	0
T425	273664	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	990331138	973151380	0	0
T4	182158	182042	0	0
T5	249200	249188	0	0
T6	195762	195638	0	0
T16	262656	262532	0	0
T19	521760	521520	0	0
T20	1093696	1093662	0	0
T41	1891514	1891310	0	0
T42	144950	144840	0	0
T54	251672	251660	0	0
T85	324590	324378	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	990331138	8456	0	0
T44	176438	0	0	0
T253	175268	0	0	0
T293	411592	0	0	0
T332	221754	2819	0	0
T333	549570	0	0	0
T334	309968	0	0	0
T335	247644	0	0	0
T336	0	2814	0	0
T337	0	2823	0	0
T423	153702	0	0	0
T424	288438	0	0	0
T425	273664	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T332,T336
0	1	Covered	T332,T336,T337
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T332,T336,T337
1	Covered	T9,T332,T336

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T332,T336,T337
1	Covered	T9,T332,T336

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T332,T336,T337
1	1	Covered	T332,T336,T337

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T332,T336
1	0	Covered	T332,T336,T337
1	1	Covered	T332,T336,T337

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T332,T336,T337

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T332,T336
0	Covered	T332,T336,T337

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T332,T336
0	Covered	T332,T336,T337

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	495165569	486575690	0	0
CheckNGreaterZero_A	1002	1002	0	0
GntImpliesReady_A	495165569	5271	0	0
GntImpliesValid_A	495165569	5271	0	0
GrantKnown_A	495165569	486575690	0	0
IdxKnown_A	495165569	486575690	0	0
IndexIsCorrect_A	495165569	5271	0	0
NoReadyValidNoGrant_A	495165569	0	0	0
Priority_A	495165569	5271	0	0
ReadyAndValidImplyGrant_A	495165569	5271	0	0
ReqAndReadyImplyGrant_A	495165569	5271	0	0
ReqImpliesValid_A	495165569	5271	0	0
ValidKnown_A	495165569	486575690	0	0
gen_data_port_assertion.DataFlow_A	495165569	5271	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	486575690	0	0
T4	91079	91021	0	0
T5	124600	124594	0	0
T6	97881	97819	0	0
T16	131328	131266	0	0
T19	260880	260760	0	0
T20	546848	546831	0	0
T41	945757	945655	0	0
T42	72475	72420	0	0
T54	125836	125830	0	0
T85	162295	162189	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1002	1002	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T41	1	1	0	0
T42	1	1	0	0
T54	1	1	0	0
T85	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	5271	0	0
T44	88219	0	0	0
T253	87634	0	0	0
T293	205796	0	0	0
T332	110877	1758	0	0
T333	274785	0	0	0
T334	154984	0	0	0
T335	123822	0	0	0
T336	0	1752	0	0
T337	0	1761	0	0
T423	76851	0	0	0
T424	144219	0	0	0
T425	136832	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	5271	0	0
T44	88219	0	0	0
T253	87634	0	0	0
T293	205796	0	0	0
T332	110877	1758	0	0
T333	274785	0	0	0
T334	154984	0	0	0
T335	123822	0	0	0
T336	0	1752	0	0
T337	0	1761	0	0
T423	76851	0	0	0
T424	144219	0	0	0
T425	136832	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	486575690	0	0
T4	91079	91021	0	0
T5	124600	124594	0	0
T6	97881	97819	0	0
T16	131328	131266	0	0
T19	260880	260760	0	0
T20	546848	546831	0	0
T41	945757	945655	0	0
T42	72475	72420	0	0
T54	125836	125830	0	0
T85	162295	162189	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	486575690	0	0
T4	91079	91021	0	0
T5	124600	124594	0	0
T6	97881	97819	0	0
T16	131328	131266	0	0
T19	260880	260760	0	0
T20	546848	546831	0	0
T41	945757	945655	0	0
T42	72475	72420	0	0
T54	125836	125830	0	0
T85	162295	162189	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	5271	0	0
T44	88219	0	0	0
T253	87634	0	0	0
T293	205796	0	0	0
T332	110877	1758	0	0
T333	274785	0	0	0
T334	154984	0	0	0
T335	123822	0	0	0
T336	0	1752	0	0
T337	0	1761	0	0
T423	76851	0	0	0
T424	144219	0	0	0
T425	136832	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	5271	0	0
T44	88219	0	0	0
T253	87634	0	0	0
T293	205796	0	0	0
T332	110877	1758	0	0
T333	274785	0	0	0
T334	154984	0	0	0
T335	123822	0	0	0
T336	0	1752	0	0
T337	0	1761	0	0
T423	76851	0	0	0
T424	144219	0	0	0
T425	136832	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	5271	0	0
T44	88219	0	0	0
T253	87634	0	0	0
T293	205796	0	0	0
T332	110877	1758	0	0
T333	274785	0	0	0
T334	154984	0	0	0
T335	123822	0	0	0
T336	0	1752	0	0
T337	0	1761	0	0
T423	76851	0	0	0
T424	144219	0	0	0
T425	136832	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	5271	0	0
T44	88219	0	0	0
T253	87634	0	0	0
T293	205796	0	0	0
T332	110877	1758	0	0
T333	274785	0	0	0
T334	154984	0	0	0
T335	123822	0	0	0
T336	0	1752	0	0
T337	0	1761	0	0
T423	76851	0	0	0
T424	144219	0	0	0
T425	136832	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	5271	0	0
T44	88219	0	0	0
T253	87634	0	0	0
T293	205796	0	0	0
T332	110877	1758	0	0
T333	274785	0	0	0
T334	154984	0	0	0
T335	123822	0	0	0
T336	0	1752	0	0
T337	0	1761	0	0
T423	76851	0	0	0
T424	144219	0	0	0
T425	136832	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	486575690	0	0
T4	91079	91021	0	0
T5	124600	124594	0	0
T6	97881	97819	0	0
T16	131328	131266	0	0
T19	260880	260760	0	0
T20	546848	546831	0	0
T41	945757	945655	0	0
T42	72475	72420	0	0
T54	125836	125830	0	0
T85	162295	162189	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	5271	0	0
T44	88219	0	0	0
T253	87634	0	0	0
T293	205796	0	0	0
T332	110877	1758	0	0
T333	274785	0	0	0
T334	154984	0	0	0
T335	123822	0	0	0
T336	0	1752	0	0
T337	0	1761	0	0
T423	76851	0	0	0
T424	144219	0	0	0
T425	136832	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T332,T336
0	1	Covered	T9,T332,T336
1	0	Covered	T12

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T332,T336,T12
1	Covered	T9,T332,T336

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T332,T336,T12
1	Covered	T9,T332,T336

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T9,T332,T336
1	1	Covered	T332,T336,T12

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T332,T336
1	0	Covered	T332,T336,T12
1	1	Covered	T9,T332,T336

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T9,T332,T336

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T332,T336
0	Covered	T332,T336,T12

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T332,T336
0	Covered	T332,T336,T12

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	495165569	486575690	0	0
CheckNGreaterZero_A	1002	1002	0	0
GntImpliesReady_A	495165569	3185	0	0
GntImpliesValid_A	495165569	3185	0	0
GrantKnown_A	495165569	486575690	0	0
IdxKnown_A	495165569	486575690	0	0
IndexIsCorrect_A	495165569	3185	0	0
NoReadyValidNoGrant_A	495165569	0	0	0
Priority_A	495165569	3185	0	0
ReadyAndValidImplyGrant_A	495165569	3185	0	0
ReqAndReadyImplyGrant_A	495165569	3185	0	0
ReqImpliesValid_A	495165569	3185	0	0
ValidKnown_A	495165569	486575690	0	0
gen_data_port_assertion.DataFlow_A	495165569	3185	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	486575690	0	0
T4	91079	91021	0	0
T5	124600	124594	0	0
T6	97881	97819	0	0
T16	131328	131266	0	0
T19	260880	260760	0	0
T20	546848	546831	0	0
T41	945757	945655	0	0
T42	72475	72420	0	0
T54	125836	125830	0	0
T85	162295	162189	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1002	1002	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T41	1	1	0	0
T42	1	1	0	0
T54	1	1	0	0
T85	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	3185	0	0
T44	88219	0	0	0
T253	87634	0	0	0
T293	205796	0	0	0
T332	110877	1061	0	0
T333	274785	0	0	0
T334	154984	0	0	0
T335	123822	0	0	0
T336	0	1062	0	0
T337	0	1062	0	0
T423	76851	0	0	0
T424	144219	0	0	0
T425	136832	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	3185	0	0
T44	88219	0	0	0
T253	87634	0	0	0
T293	205796	0	0	0
T332	110877	1061	0	0
T333	274785	0	0	0
T334	154984	0	0	0
T335	123822	0	0	0
T336	0	1062	0	0
T337	0	1062	0	0
T423	76851	0	0	0
T424	144219	0	0	0
T425	136832	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	486575690	0	0
T4	91079	91021	0	0
T5	124600	124594	0	0
T6	97881	97819	0	0
T16	131328	131266	0	0
T19	260880	260760	0	0
T20	546848	546831	0	0
T41	945757	945655	0	0
T42	72475	72420	0	0
T54	125836	125830	0	0
T85	162295	162189	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	486575690	0	0
T4	91079	91021	0	0
T5	124600	124594	0	0
T6	97881	97819	0	0
T16	131328	131266	0	0
T19	260880	260760	0	0
T20	546848	546831	0	0
T41	945757	945655	0	0
T42	72475	72420	0	0
T54	125836	125830	0	0
T85	162295	162189	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	3185	0	0
T44	88219	0	0	0
T253	87634	0	0	0
T293	205796	0	0	0
T332	110877	1061	0	0
T333	274785	0	0	0
T334	154984	0	0	0
T335	123822	0	0	0
T336	0	1062	0	0
T337	0	1062	0	0
T423	76851	0	0	0
T424	144219	0	0	0
T425	136832	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	3185	0	0
T44	88219	0	0	0
T253	87634	0	0	0
T293	205796	0	0	0
T332	110877	1061	0	0
T333	274785	0	0	0
T334	154984	0	0	0
T335	123822	0	0	0
T336	0	1062	0	0
T337	0	1062	0	0
T423	76851	0	0	0
T424	144219	0	0	0
T425	136832	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	3185	0	0
T44	88219	0	0	0
T253	87634	0	0	0
T293	205796	0	0	0
T332	110877	1061	0	0
T333	274785	0	0	0
T334	154984	0	0	0
T335	123822	0	0	0
T336	0	1062	0	0
T337	0	1062	0	0
T423	76851	0	0	0
T424	144219	0	0	0
T425	136832	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	3185	0	0
T44	88219	0	0	0
T253	87634	0	0	0
T293	205796	0	0	0
T332	110877	1061	0	0
T333	274785	0	0	0
T334	154984	0	0	0
T335	123822	0	0	0
T336	0	1062	0	0
T337	0	1062	0	0
T423	76851	0	0	0
T424	144219	0	0	0
T425	136832	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	3185	0	0
T44	88219	0	0	0
T253	87634	0	0	0
T293	205796	0	0	0
T332	110877	1061	0	0
T333	274785	0	0	0
T334	154984	0	0	0
T335	123822	0	0	0
T336	0	1062	0	0
T337	0	1062	0	0
T423	76851	0	0	0
T424	144219	0	0	0
T425	136832	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	486575690	0	0
T4	91079	91021	0	0
T5	124600	124594	0	0
T6	97881	97819	0	0
T16	131328	131266	0	0
T19	260880	260760	0	0
T20	546848	546831	0	0
T41	945757	945655	0	0
T42	72475	72420	0	0
T54	125836	125830	0	0
T85	162295	162189	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495165569	3185	0	0
T44	88219	0	0	0
T253	87634	0	0	0
T293	205796	0	0	0
T332	110877	1061	0	0
T333	274785	0	0	0
T334	154984	0	0	0
T335	123822	0	0	0
T336	0	1062	0	0
T337	0	1062	0	0
T423	76851	0	0	0
T424	144219	0	0	0
T425	136832	0	0	0