Unified Coverage Report :: Module :: prim_mubi4_sync

Module : prim_mubi4_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync	100.00						100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.83	99.34	100.00			100.00	100.00	u_pinmux_strap_sampling

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : prim_mubi4_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1002	1002	0	0
OutputsKnown_A	123339791	122671748	0	0
gen_no_flops.OutputDelay_A	123339791	122671748	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1002	1002	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T41	1	1	0	0
T42	1	1	0	0
T54	1	1	0	0
T85	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123339791	122671748	0	0
T4	23030	22227	0	0
T5	299956	299430	0	0
T6	24360	23859	0	0
T16	32530	31886	0	0
T19	65278	64647	0	0
T20	131492	131362	0	0
T41	228258	227743	0	0
T42	18172	17763	0	0
T54	302924	302396	0	0
T85	40253	39700	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123339791	122671748	0	0
T4	23030	22227	0	0
T5	299956	299430	0	0
T6	24360	23859	0	0
T16	32530	31886	0	0
T19	65278	64647	0	0
T20	131492	131362	0	0
T41	228258	227743	0	0
T42	18172	17763	0	0
T54	302924	302396	0	0
T85	40253	39700	0	0

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1002	1002	0	0
OutputsKnown_A	123339791	122671748	0	0
gen_no_flops.OutputDelay_A	123339791	122671748	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1002	1002	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T41	1	1	0	0
T42	1	1	0	0
T54	1	1	0	0
T85	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123339791	122671748	0	0
T4	23030	22227	0	0
T5	299956	299430	0	0
T6	24360	23859	0	0
T16	32530	31886	0	0
T19	65278	64647	0	0
T20	131492	131362	0	0
T41	228258	227743	0	0
T42	18172	17763	0	0
T54	302924	302396	0	0
T85	40253	39700	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123339791	122671748	0	0
T4	23030	22227	0	0
T5	299956	299430	0	0
T6	24360	23859	0	0
T16	32530	31886	0	0
T19	65278	64647	0	0
T20	131492	131362	0	0
T41	228258	227743	0	0
T42	18172	17763	0	0
T54	302924	302396	0	0
T85	40253	39700	0	0