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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.10 95.49 93.94 95.40 94.74 97.53 99.51


Total test records in report: 2873
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T276 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.3168269080 Jun 21 08:01:47 PM PDT 24 Jun 21 08:09:23 PM PDT 24 3939135307 ps
T931 /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.1252535644 Jun 21 08:31:17 PM PDT 24 Jun 21 08:49:17 PM PDT 24 12107249407 ps
T388 /workspace/coverage/default/1.rom_e2e_asm_init_dev.282378025 Jun 21 08:22:00 PM PDT 24 Jun 21 09:24:37 PM PDT 24 15778982384 ps
T145 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.4267988817 Jun 21 08:19:54 PM PDT 24 Jun 21 09:21:23 PM PDT 24 17585941148 ps
T932 /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.2104513405 Jun 21 08:17:02 PM PDT 24 Jun 21 08:20:12 PM PDT 24 2678263170 ps
T147 /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.4173481603 Jun 21 07:58:53 PM PDT 24 Jun 21 11:09:50 PM PDT 24 59139589218 ps
T232 /workspace/coverage/default/96.chip_sw_all_escalation_resets.3134262921 Jun 21 08:35:50 PM PDT 24 Jun 21 08:43:39 PM PDT 24 4744419040 ps
T257 /workspace/coverage/default/69.chip_sw_all_escalation_resets.691141993 Jun 21 08:32:26 PM PDT 24 Jun 21 08:41:57 PM PDT 24 4951293084 ps
T258 /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.1432091294 Jun 21 08:14:22 PM PDT 24 Jun 21 08:20:06 PM PDT 24 2599339660 ps
T259 /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.3968461587 Jun 21 07:59:55 PM PDT 24 Jun 21 08:06:34 PM PDT 24 3599906160 ps
T260 /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.993537222 Jun 21 07:58:40 PM PDT 24 Jun 21 09:19:55 PM PDT 24 44094431792 ps
T241 /workspace/coverage/default/1.chip_sw_plic_sw_irq.3431871214 Jun 21 08:10:53 PM PDT 24 Jun 21 08:14:40 PM PDT 24 2457752300 ps
T261 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.2185010323 Jun 21 07:58:24 PM PDT 24 Jun 21 08:09:11 PM PDT 24 4821827448 ps
T262 /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.79578498 Jun 21 08:29:53 PM PDT 24 Jun 21 08:37:36 PM PDT 24 3555714848 ps
T263 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.197693821 Jun 21 08:00:36 PM PDT 24 Jun 21 08:28:28 PM PDT 24 8895251018 ps
T30 /workspace/coverage/default/0.chip_sw_usbdev_stream.4127007015 Jun 21 07:56:46 PM PDT 24 Jun 21 08:57:53 PM PDT 24 18621388104 ps
T83 /workspace/coverage/default/1.chip_sw_alert_handler_entropy.2477309951 Jun 21 08:06:06 PM PDT 24 Jun 21 08:11:00 PM PDT 24 3052216446 ps
T933 /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.3939261699 Jun 21 08:03:24 PM PDT 24 Jun 21 08:25:51 PM PDT 24 5664813124 ps
T747 /workspace/coverage/default/32.chip_sw_all_escalation_resets.2892711679 Jun 21 08:29:30 PM PDT 24 Jun 21 08:38:24 PM PDT 24 4501161570 ps
T768 /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.181641201 Jun 21 08:31:32 PM PDT 24 Jun 21 08:37:01 PM PDT 24 3119020538 ps
T754 /workspace/coverage/default/0.chip_sw_all_escalation_resets.3645217210 Jun 21 07:57:52 PM PDT 24 Jun 21 08:10:41 PM PDT 24 5358672966 ps
T120 /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.3298550763 Jun 21 08:07:53 PM PDT 24 Jun 21 08:19:47 PM PDT 24 6180660660 ps
T794 /workspace/coverage/default/98.chip_sw_all_escalation_resets.3096668457 Jun 21 08:35:59 PM PDT 24 Jun 21 08:48:10 PM PDT 24 5105406834 ps
T934 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.435461592 Jun 21 08:23:58 PM PDT 24 Jun 21 08:27:10 PM PDT 24 2324453774 ps
T935 /workspace/coverage/default/2.chip_sw_aes_enc.2553763774 Jun 21 08:17:36 PM PDT 24 Jun 21 08:23:03 PM PDT 24 2906624732 ps
T167 /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.2617710898 Jun 21 07:57:45 PM PDT 24 Jun 21 08:00:10 PM PDT 24 3291864337 ps
T214 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.2554735048 Jun 21 08:21:00 PM PDT 24 Jun 21 08:50:51 PM PDT 24 10008410152 ps
T192 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.694688033 Jun 21 08:06:24 PM PDT 24 Jun 21 08:11:28 PM PDT 24 2645749714 ps
T348 /workspace/coverage/default/0.chip_sival_flash_info_access.2028624850 Jun 21 07:59:18 PM PDT 24 Jun 21 08:03:49 PM PDT 24 2744246400 ps
T310 /workspace/coverage/default/62.chip_sw_all_escalation_resets.2826732828 Jun 21 08:32:10 PM PDT 24 Jun 21 08:42:43 PM PDT 24 5244272530 ps
T936 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.1990028714 Jun 21 08:06:02 PM PDT 24 Jun 21 09:05:31 PM PDT 24 15825299354 ps
T798 /workspace/coverage/default/2.chip_sw_all_escalation_resets.2223210883 Jun 21 08:14:52 PM PDT 24 Jun 21 08:28:07 PM PDT 24 5086248240 ps
T125 /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.4089051025 Jun 21 07:59:24 PM PDT 24 Jun 21 08:09:51 PM PDT 24 6300278470 ps
T937 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1101585617 Jun 21 08:26:10 PM PDT 24 Jun 21 08:53:46 PM PDT 24 12785726582 ps
T938 /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.2246817898 Jun 21 07:58:13 PM PDT 24 Jun 21 08:16:58 PM PDT 24 6379528248 ps
T399 /workspace/coverage/default/0.rom_e2e_jtag_inject_rma.3860167405 Jun 21 08:01:50 PM PDT 24 Jun 21 09:04:21 PM PDT 24 37487458040 ps
T60 /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3750469287 Jun 21 07:56:59 PM PDT 24 Jun 21 08:03:47 PM PDT 24 3605062746 ps
T8 /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.810921034 Jun 21 08:20:31 PM PDT 24 Jun 21 08:25:20 PM PDT 24 4283887946 ps
T221 /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.1683517585 Jun 21 07:57:59 PM PDT 24 Jun 21 09:36:24 PM PDT 24 48560478320 ps
T939 /workspace/coverage/default/2.chip_sw_aes_smoketest.3808390328 Jun 21 08:27:31 PM PDT 24 Jun 21 08:31:51 PM PDT 24 3326563540 ps
T940 /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.227927336 Jun 21 08:19:34 PM PDT 24 Jun 21 08:28:35 PM PDT 24 5289486760 ps
T36 /workspace/coverage/default/2.chip_sw_gpio.3279032791 Jun 21 08:15:37 PM PDT 24 Jun 21 08:25:11 PM PDT 24 3747464664 ps
T311 /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2557765138 Jun 21 08:30:28 PM PDT 24 Jun 21 08:38:17 PM PDT 24 4163735192 ps
T941 /workspace/coverage/default/2.chip_sw_uart_tx_rx.1684227556 Jun 21 08:13:49 PM PDT 24 Jun 21 08:26:02 PM PDT 24 4937453924 ps
T225 /workspace/coverage/default/2.chip_sw_flash_init.4166032407 Jun 21 08:15:34 PM PDT 24 Jun 21 08:50:36 PM PDT 24 18281038512 ps
T942 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.3349094391 Jun 21 08:07:52 PM PDT 24 Jun 21 08:41:14 PM PDT 24 7603486060 ps
T943 /workspace/coverage/default/2.chip_sw_csrng_kat_test.1092446463 Jun 21 08:19:57 PM PDT 24 Jun 21 08:24:20 PM PDT 24 2761177296 ps
T189 /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.4193301278 Jun 21 08:15:03 PM PDT 24 Jun 22 12:11:11 AM PDT 24 78413729364 ps
T944 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.1967749920 Jun 21 08:18:09 PM PDT 24 Jun 21 08:33:23 PM PDT 24 6691331976 ps
T945 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.3270578175 Jun 21 08:06:07 PM PDT 24 Jun 21 09:15:59 PM PDT 24 15321954728 ps
T946 /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.3238732646 Jun 21 07:57:28 PM PDT 24 Jun 21 08:18:59 PM PDT 24 6118356626 ps
T65 /workspace/coverage/default/0.chip_tap_straps_testunlock0.2664013313 Jun 21 08:00:34 PM PDT 24 Jun 21 08:10:21 PM PDT 24 5701513273 ps
T947 /workspace/coverage/default/1.rom_e2e_smoke.84699340 Jun 21 08:17:56 PM PDT 24 Jun 21 09:19:32 PM PDT 24 14742182110 ps
T341 /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.561526772 Jun 21 07:57:22 PM PDT 24 Jun 21 08:08:59 PM PDT 24 3972352476 ps
T948 /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.1837411916 Jun 21 08:24:11 PM PDT 24 Jun 21 08:28:00 PM PDT 24 3103339986 ps
T713 /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.2371856705 Jun 21 08:13:44 PM PDT 24 Jun 21 08:38:14 PM PDT 24 10004194760 ps
T172 /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.3631049204 Jun 21 08:23:15 PM PDT 24 Jun 21 08:29:37 PM PDT 24 2994478640 ps
T949 /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.1512245975 Jun 21 08:22:17 PM PDT 24 Jun 21 08:32:13 PM PDT 24 4319027060 ps
T950 /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.2867203196 Jun 21 08:18:11 PM PDT 24 Jun 21 08:25:37 PM PDT 24 3841229416 ps
T72 /workspace/coverage/default/0.chip_sw_usbdev_pullup.208174407 Jun 21 07:58:13 PM PDT 24 Jun 21 08:04:06 PM PDT 24 2914774696 ps
T951 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.515158850 Jun 21 08:14:18 PM PDT 24 Jun 21 08:25:03 PM PDT 24 5057476840 ps
T34 /workspace/coverage/default/0.chip_sw_usbdev_dpi.1516008868 Jun 21 07:58:21 PM PDT 24 Jun 21 08:53:51 PM PDT 24 11665482230 ps
T952 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.141086294 Jun 21 07:58:36 PM PDT 24 Jun 21 08:38:28 PM PDT 24 23574720170 ps
T953 /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.2324732770 Jun 21 07:59:37 PM PDT 24 Jun 21 08:07:12 PM PDT 24 5134946472 ps
T954 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.942528494 Jun 21 08:25:19 PM PDT 24 Jun 21 08:36:34 PM PDT 24 4611517079 ps
T360 /workspace/coverage/default/1.chip_sw_all_escalation_resets.389881659 Jun 21 08:03:10 PM PDT 24 Jun 21 08:13:29 PM PDT 24 6238066462 ps
T349 /workspace/coverage/default/1.chip_sw_hmac_enc.3478537232 Jun 21 08:08:19 PM PDT 24 Jun 21 08:12:55 PM PDT 24 2703149976 ps
T237 /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.4028252921 Jun 21 08:31:07 PM PDT 24 Jun 21 08:37:40 PM PDT 24 3707232328 ps
T955 /workspace/coverage/default/0.chip_sw_example_rom.182879872 Jun 21 07:57:30 PM PDT 24 Jun 21 07:59:27 PM PDT 24 2187341936 ps
T155 /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.4098594339 Jun 21 08:06:14 PM PDT 24 Jun 21 08:08:02 PM PDT 24 2507591565 ps
T956 /workspace/coverage/default/0.chip_sw_hmac_multistream.3319595306 Jun 21 08:03:22 PM PDT 24 Jun 21 08:29:28 PM PDT 24 6672887012 ps
T957 /workspace/coverage/default/2.rom_e2e_smoke.3276152897 Jun 21 08:28:22 PM PDT 24 Jun 21 09:23:59 PM PDT 24 15146410800 ps
T183 /workspace/coverage/default/0.chip_sw_spi_device_pass_through.792241058 Jun 21 07:58:56 PM PDT 24 Jun 21 08:10:19 PM PDT 24 6578813509 ps
T277 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3006715360 Jun 21 08:22:11 PM PDT 24 Jun 21 08:31:51 PM PDT 24 5670998654 ps
T730 /workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.3886802945 Jun 21 08:07:40 PM PDT 24 Jun 21 08:34:39 PM PDT 24 7740924090 ps
T778 /workspace/coverage/default/30.chip_sw_all_escalation_resets.3596537354 Jun 21 08:29:51 PM PDT 24 Jun 21 08:41:55 PM PDT 24 5692691416 ps
T958 /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.1169101488 Jun 21 08:17:23 PM PDT 24 Jun 21 09:03:58 PM PDT 24 11761097428 ps
T959 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.2291896809 Jun 21 08:27:28 PM PDT 24 Jun 21 09:33:20 PM PDT 24 15488188200 ps
T796 /workspace/coverage/default/86.chip_sw_all_escalation_resets.2295089620 Jun 21 08:36:28 PM PDT 24 Jun 21 08:47:24 PM PDT 24 5024043130 ps
T960 /workspace/coverage/default/4.chip_tap_straps_testunlock0.2126041101 Jun 21 08:27:03 PM PDT 24 Jun 21 08:32:33 PM PDT 24 3961462383 ps
T961 /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.3986869554 Jun 21 08:32:52 PM PDT 24 Jun 21 08:38:56 PM PDT 24 4318722560 ps
T766 /workspace/coverage/default/16.chip_sw_all_escalation_resets.1123625535 Jun 21 08:27:49 PM PDT 24 Jun 21 08:36:51 PM PDT 24 5072289018 ps
T233 /workspace/coverage/default/79.chip_sw_all_escalation_resets.3347213216 Jun 21 08:33:48 PM PDT 24 Jun 21 08:42:53 PM PDT 24 5519710110 ps
T962 /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3512564682 Jun 21 08:20:23 PM PDT 24 Jun 21 08:30:26 PM PDT 24 8005663806 ps
T963 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.4263821854 Jun 21 07:57:05 PM PDT 24 Jun 21 08:07:57 PM PDT 24 4088469528 ps
T964 /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.49159902 Jun 21 08:03:19 PM PDT 24 Jun 21 08:07:20 PM PDT 24 2821312404 ps
T267 /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.1196591684 Jun 21 08:20:37 PM PDT 24 Jun 21 08:32:32 PM PDT 24 8308588685 ps
T470 /workspace/coverage/default/0.chip_sw_otbn_randomness.1614258856 Jun 21 08:02:36 PM PDT 24 Jun 21 08:20:49 PM PDT 24 5614526882 ps
T246 /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.3601003308 Jun 21 08:14:26 PM PDT 24 Jun 21 08:19:47 PM PDT 24 2571886250 ps
T965 /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.480528967 Jun 21 08:05:44 PM PDT 24 Jun 21 11:34:26 PM PDT 24 254944882644 ps
T966 /workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.2053951806 Jun 21 08:15:37 PM PDT 24 Jun 21 08:19:28 PM PDT 24 2888996295 ps
T967 /workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.220517924 Jun 21 07:58:39 PM PDT 24 Jun 21 09:36:13 PM PDT 24 27177619544 ps
T968 /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.3548003854 Jun 21 08:06:05 PM PDT 24 Jun 21 08:44:26 PM PDT 24 32719353500 ps
T557 /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.461789772 Jun 21 07:59:27 PM PDT 24 Jun 21 08:14:30 PM PDT 24 4664637736 ps
T3 /workspace/coverage/default/1.chip_sw_sleep_pin_retention.2590536306 Jun 21 08:06:35 PM PDT 24 Jun 21 08:11:58 PM PDT 24 3874893256 ps
T420 /workspace/coverage/default/0.chip_sw_example_concurrency.3897347636 Jun 21 07:58:10 PM PDT 24 Jun 21 08:04:06 PM PDT 24 2671474148 ps
T193 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.2308681733 Jun 21 08:17:46 PM PDT 24 Jun 21 08:24:50 PM PDT 24 3794073842 ps
T421 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1872256602 Jun 21 08:17:09 PM PDT 24 Jun 21 09:16:19 PM PDT 24 36821790450 ps
T353 /workspace/coverage/default/1.chip_sw_pattgen_ios.3236919213 Jun 21 08:04:33 PM PDT 24 Jun 21 08:07:33 PM PDT 24 2939225608 ps
T422 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.4146569929 Jun 21 08:03:21 PM PDT 24 Jun 21 08:16:46 PM PDT 24 7189627772 ps
T11 /workspace/coverage/default/2.chip_sw_sleep_pin_retention.3604128869 Jun 21 08:14:42 PM PDT 24 Jun 21 08:20:00 PM PDT 24 3643917792 ps
T423 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.2646632063 Jun 21 07:58:23 PM PDT 24 Jun 21 09:02:20 PM PDT 24 17503260538 ps
T12 /workspace/coverage/default/0.chip_sw_sleep_pin_retention.1029796116 Jun 21 07:58:25 PM PDT 24 Jun 21 08:04:50 PM PDT 24 4387523500 ps
T424 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.387143306 Jun 21 07:59:22 PM PDT 24 Jun 21 08:12:23 PM PDT 24 4616112838 ps
T969 /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.2423229229 Jun 21 08:20:55 PM PDT 24 Jun 21 08:31:42 PM PDT 24 5232036652 ps
T365 /workspace/coverage/default/2.chip_sw_hmac_enc.2789068795 Jun 21 08:20:20 PM PDT 24 Jun 21 08:26:21 PM PDT 24 3126323440 ps
T124 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.1486728825 Jun 21 08:21:13 PM PDT 24 Jun 21 08:27:50 PM PDT 24 5780421852 ps
T970 /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.4076426562 Jun 21 08:18:33 PM PDT 24 Jun 21 08:23:34 PM PDT 24 2840608220 ps
T971 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.3979299708 Jun 21 08:12:37 PM PDT 24 Jun 21 08:18:12 PM PDT 24 3271167912 ps
T755 /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.2648971420 Jun 21 08:34:55 PM PDT 24 Jun 21 08:40:15 PM PDT 24 3566684176 ps
T972 /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.3789247848 Jun 21 08:29:24 PM PDT 24 Jun 21 09:21:56 PM PDT 24 15292833474 ps
T266 /workspace/coverage/default/1.rom_volatile_raw_unlock.3377174024 Jun 21 08:13:37 PM PDT 24 Jun 21 08:15:40 PM PDT 24 2665790607 ps
T784 /workspace/coverage/default/71.chip_sw_all_escalation_resets.1893344730 Jun 21 08:32:54 PM PDT 24 Jun 21 08:43:10 PM PDT 24 6286075724 ps
T42 /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.2106096256 Jun 21 08:04:28 PM PDT 24 Jun 21 08:09:22 PM PDT 24 3149389332 ps
T825 /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1688235485 Jun 21 08:35:06 PM PDT 24 Jun 21 08:39:54 PM PDT 24 2996579256 ps
T218 /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.589425573 Jun 21 08:00:01 PM PDT 24 Jun 21 08:10:53 PM PDT 24 4861352497 ps
T751 /workspace/coverage/default/37.chip_sw_all_escalation_resets.1777741540 Jun 21 08:31:27 PM PDT 24 Jun 21 08:44:39 PM PDT 24 5339303816 ps
T973 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.8752048 Jun 21 07:58:38 PM PDT 24 Jun 21 08:06:51 PM PDT 24 6312798702 ps
T73 /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.2815037761 Jun 21 08:24:45 PM PDT 24 Jun 21 08:33:31 PM PDT 24 6816105600 ps
T43 /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.1552507742 Jun 21 07:59:14 PM PDT 24 Jun 21 08:05:08 PM PDT 24 2607318896 ps
T974 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1468285331 Jun 21 08:01:01 PM PDT 24 Jun 21 08:07:12 PM PDT 24 3577520063 ps
T975 /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.576196108 Jun 21 08:06:55 PM PDT 24 Jun 21 08:11:40 PM PDT 24 2646375890 ps
T976 /workspace/coverage/default/0.chip_sw_csrng_kat_test.241820922 Jun 21 08:00:14 PM PDT 24 Jun 21 08:03:14 PM PDT 24 2066275200 ps
T748 /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.3868187628 Jun 21 08:33:13 PM PDT 24 Jun 21 08:40:54 PM PDT 24 3540705276 ps
T16 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2037179550 Jun 21 08:22:52 PM PDT 24 Jun 21 08:29:51 PM PDT 24 7304959308 ps
T238 /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.2691327019 Jun 21 08:33:14 PM PDT 24 Jun 21 08:39:22 PM PDT 24 3851449116 ps
T977 /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.1091321872 Jun 21 08:27:54 PM PDT 24 Jun 21 08:38:18 PM PDT 24 4487541120 ps
T213 /workspace/coverage/default/0.chip_sw_alert_handler_escalation.4176865638 Jun 21 07:59:59 PM PDT 24 Jun 21 08:09:45 PM PDT 24 5736673948 ps
T823 /workspace/coverage/default/60.chip_sw_all_escalation_resets.2148742812 Jun 21 08:32:40 PM PDT 24 Jun 21 08:42:09 PM PDT 24 5922382228 ps
T49 /workspace/coverage/default/1.chip_sw_spi_device_tpm.4028881773 Jun 21 08:06:28 PM PDT 24 Jun 21 08:13:21 PM PDT 24 3569295864 ps
T347 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.2567342953 Jun 21 08:16:14 PM PDT 24 Jun 21 08:29:52 PM PDT 24 4338729926 ps
T978 /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.3114115304 Jun 21 08:02:04 PM PDT 24 Jun 21 08:08:55 PM PDT 24 4955676324 ps
T136 /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.2242549082 Jun 21 08:04:12 PM PDT 24 Jun 21 08:12:19 PM PDT 24 7162644680 ps
T979 /workspace/coverage/default/2.chip_sw_rv_timer_irq.2213537762 Jun 21 08:17:20 PM PDT 24 Jun 21 08:22:44 PM PDT 24 3302491856 ps
T322 /workspace/coverage/default/2.chip_plic_all_irqs_20.746145849 Jun 21 08:20:58 PM PDT 24 Jun 21 08:32:12 PM PDT 24 4763470200 ps
T980 /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.3613887898 Jun 21 08:05:30 PM PDT 24 Jun 21 08:11:58 PM PDT 24 5810838804 ps
T100 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.258095581 Jun 21 08:22:02 PM PDT 24 Jun 21 08:48:02 PM PDT 24 25991923598 ps
T90 /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.1081289652 Jun 21 08:24:54 PM PDT 24 Jun 21 08:32:10 PM PDT 24 3687217736 ps
T981 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.3032573047 Jun 21 08:19:22 PM PDT 24 Jun 21 08:27:38 PM PDT 24 6532276396 ps
T982 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.4058108302 Jun 21 07:59:30 PM PDT 24 Jun 21 08:11:23 PM PDT 24 4389078006 ps
T287 /workspace/coverage/default/77.chip_sw_all_escalation_resets.221196309 Jun 21 08:35:15 PM PDT 24 Jun 21 08:43:58 PM PDT 24 5461647988 ps
T372 /workspace/coverage/default/2.chip_sival_flash_info_access.2274557822 Jun 21 08:14:01 PM PDT 24 Jun 21 08:19:22 PM PDT 24 3623995368 ps
T983 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.1332710229 Jun 21 07:57:54 PM PDT 24 Jun 21 08:18:40 PM PDT 24 5750030017 ps
T13 /workspace/coverage/default/2.chip_sw_sleep_pin_wake.3765038908 Jun 21 08:16:17 PM PDT 24 Jun 21 08:22:35 PM PDT 24 3008634776 ps
T440 /workspace/coverage/default/45.chip_sw_all_escalation_resets.2505209161 Jun 21 08:31:54 PM PDT 24 Jun 21 08:43:34 PM PDT 24 5815773682 ps
T441 /workspace/coverage/default/93.chip_sw_all_escalation_resets.3950235677 Jun 21 08:35:13 PM PDT 24 Jun 21 08:46:58 PM PDT 24 5367191880 ps
T278 /workspace/coverage/default/5.chip_sw_data_integrity_escalation.4290858416 Jun 21 08:27:32 PM PDT 24 Jun 21 08:39:15 PM PDT 24 6070926766 ps
T194 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.3047717349 Jun 21 08:03:08 PM PDT 24 Jun 21 08:10:11 PM PDT 24 3138390050 ps
T442 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2375925726 Jun 21 08:04:06 PM PDT 24 Jun 21 08:12:51 PM PDT 24 6411076726 ps
T443 /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.408688579 Jun 21 08:27:49 PM PDT 24 Jun 21 08:44:44 PM PDT 24 9934146412 ps
T444 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.501683759 Jun 21 08:10:25 PM PDT 24 Jun 21 09:57:59 PM PDT 24 21079690984 ps
T445 /workspace/coverage/default/97.chip_sw_all_escalation_resets.2504869791 Jun 21 08:35:50 PM PDT 24 Jun 21 08:46:10 PM PDT 24 6139142310 ps
T446 /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3886343610 Jun 21 08:33:12 PM PDT 24 Jun 21 08:40:16 PM PDT 24 3529285706 ps
T984 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2213203379 Jun 21 08:24:39 PM PDT 24 Jun 21 08:36:00 PM PDT 24 4663350528 ps
T465 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.1053955709 Jun 21 07:59:56 PM PDT 24 Jun 21 08:23:20 PM PDT 24 5787845904 ps
T985 /workspace/coverage/default/1.chip_sw_power_sleep_load.393674560 Jun 21 08:17:09 PM PDT 24 Jun 21 08:28:57 PM PDT 24 11148465004 ps
T986 /workspace/coverage/default/2.chip_sw_power_sleep_load.3333182100 Jun 21 08:22:57 PM PDT 24 Jun 21 08:33:09 PM PDT 24 10465126430 ps
T987 /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.2180985093 Jun 21 08:22:38 PM PDT 24 Jun 21 08:44:06 PM PDT 24 6126659000 ps
T148 /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.2382286407 Jun 21 08:06:25 PM PDT 24 Jun 21 11:18:44 PM PDT 24 60333145400 ps
T137 /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.3612874317 Jun 21 08:01:19 PM PDT 24 Jun 21 08:06:39 PM PDT 24 2355044352 ps
T279 /workspace/coverage/default/1.chip_sw_data_integrity_escalation.4253232916 Jun 21 08:06:55 PM PDT 24 Jun 21 08:19:50 PM PDT 24 6015759330 ps
T222 /workspace/coverage/default/0.chip_sw_flash_init.4221645682 Jun 21 07:57:47 PM PDT 24 Jun 21 08:31:24 PM PDT 24 18741285830 ps
T690 /workspace/coverage/default/10.chip_sw_all_escalation_resets.1328522981 Jun 21 08:27:49 PM PDT 24 Jun 21 08:41:15 PM PDT 24 4684329336 ps
T21 /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3972517290 Jun 21 08:01:54 PM PDT 24 Jun 21 08:06:08 PM PDT 24 3061854728 ps
T126 /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.825205766 Jun 21 08:20:19 PM PDT 24 Jun 21 08:33:25 PM PDT 24 5246505860 ps
T988 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.3788346781 Jun 21 08:02:47 PM PDT 24 Jun 21 08:11:16 PM PDT 24 6723489944 ps
T738 /workspace/coverage/default/11.chip_sw_all_escalation_resets.3708126255 Jun 21 08:27:46 PM PDT 24 Jun 21 08:41:52 PM PDT 24 5760326054 ps
T989 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.3234603117 Jun 21 08:19:36 PM PDT 24 Jun 21 08:36:29 PM PDT 24 11027466506 ps
T990 /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.2787035020 Jun 21 08:24:31 PM PDT 24 Jun 21 08:43:06 PM PDT 24 11618785616 ps
T354 /workspace/coverage/default/2.chip_sw_pattgen_ios.2636338410 Jun 21 08:14:33 PM PDT 24 Jun 21 08:19:04 PM PDT 24 2640195416 ps
T739 /workspace/coverage/default/14.chip_sw_all_escalation_resets.2250327616 Jun 21 08:27:22 PM PDT 24 Jun 21 08:36:42 PM PDT 24 5194190320 ps
T35 /workspace/coverage/default/0.chip_sw_usbdev_pincfg.1295435933 Jun 21 08:00:06 PM PDT 24 Jun 21 10:18:03 PM PDT 24 32160103860 ps
T991 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.1782593201 Jun 21 08:15:39 PM PDT 24 Jun 21 08:34:15 PM PDT 24 5964989275 ps
T992 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.3141305466 Jun 21 07:59:34 PM PDT 24 Jun 21 08:19:12 PM PDT 24 8285852514 ps
T993 /workspace/coverage/default/0.chip_sw_kmac_smoketest.910483460 Jun 21 08:01:52 PM PDT 24 Jun 21 08:06:54 PM PDT 24 2524258520 ps
T994 /workspace/coverage/default/0.chip_sw_inject_scramble_seed.1338838642 Jun 21 07:57:37 PM PDT 24 Jun 21 11:22:53 PM PDT 24 64338725982 ps
T56 /workspace/coverage/default/0.chip_jtag_csr_rw.4284660315 Jun 21 07:52:06 PM PDT 24 Jun 21 08:11:32 PM PDT 24 9023327743 ps
T826 /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.1059190967 Jun 21 08:30:45 PM PDT 24 Jun 21 08:37:53 PM PDT 24 4030795950 ps
T694 /workspace/coverage/default/1.chip_sw_power_idle_load.1734153630 Jun 21 08:12:21 PM PDT 24 Jun 21 08:24:59 PM PDT 24 4249134114 ps
T756 /workspace/coverage/default/27.chip_sw_all_escalation_resets.4043035132 Jun 21 08:29:33 PM PDT 24 Jun 21 08:40:51 PM PDT 24 5587491904 ps
T995 /workspace/coverage/default/2.chip_tap_straps_dev.333056971 Jun 21 08:21:20 PM PDT 24 Jun 21 08:24:06 PM PDT 24 2532923114 ps
T996 /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.1385907207 Jun 21 07:59:39 PM PDT 24 Jun 21 08:05:52 PM PDT 24 3700149922 ps
T168 /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.1840460794 Jun 21 08:00:20 PM PDT 24 Jun 21 08:02:55 PM PDT 24 2820924357 ps
T787 /workspace/coverage/default/99.chip_sw_all_escalation_resets.797486725 Jun 21 08:36:26 PM PDT 24 Jun 21 08:46:33 PM PDT 24 5048954660 ps
T997 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.3463321466 Jun 21 08:02:14 PM PDT 24 Jun 21 08:24:33 PM PDT 24 8029571058 ps
T998 /workspace/coverage/default/2.rom_keymgr_functest.924356925 Jun 21 08:27:08 PM PDT 24 Jun 21 08:36:28 PM PDT 24 5338101812 ps
T999 /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.889191014 Jun 21 08:17:20 PM PDT 24 Jun 21 08:24:30 PM PDT 24 5259449400 ps
T813 /workspace/coverage/default/72.chip_sw_all_escalation_resets.3707809534 Jun 21 08:34:26 PM PDT 24 Jun 21 08:45:40 PM PDT 24 6457705346 ps
T1000 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.996362156 Jun 21 08:19:24 PM PDT 24 Jun 21 08:23:53 PM PDT 24 3304965528 ps
T333 /workspace/coverage/default/2.chip_sw_entropy_src_csrng.1678518128 Jun 21 08:18:31 PM PDT 24 Jun 21 08:45:54 PM PDT 24 6269204632 ps
T799 /workspace/coverage/default/26.chip_sw_all_escalation_resets.2455771088 Jun 21 08:28:20 PM PDT 24 Jun 21 08:38:17 PM PDT 24 5493251438 ps
T1001 /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.4288075557 Jun 21 08:14:09 PM PDT 24 Jun 21 08:22:27 PM PDT 24 6045870640 ps
T334 /workspace/coverage/default/0.chip_sw_entropy_src_csrng.2940800380 Jun 21 08:00:13 PM PDT 24 Jun 21 08:35:19 PM PDT 24 8062379872 ps
T786 /workspace/coverage/default/92.chip_sw_all_escalation_resets.2422133340 Jun 21 08:34:37 PM PDT 24 Jun 21 08:42:46 PM PDT 24 4265457960 ps
T782 /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.161690673 Jun 21 08:25:39 PM PDT 24 Jun 21 08:33:51 PM PDT 24 3646715308 ps
T752 /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.2842717021 Jun 21 08:15:03 PM PDT 24 Jun 21 08:27:12 PM PDT 24 6033031400 ps
T1002 /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.795030423 Jun 21 08:02:29 PM PDT 24 Jun 21 08:09:56 PM PDT 24 2870386478 ps
T397 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.131253000 Jun 21 08:05:49 PM PDT 24 Jun 21 09:34:49 PM PDT 24 23628363600 ps
T336 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.2962825258 Jun 21 08:03:00 PM PDT 24 Jun 21 08:15:30 PM PDT 24 5468652850 ps
T66 /workspace/coverage/default/4.chip_tap_straps_rma.30599185 Jun 21 08:26:20 PM PDT 24 Jun 21 08:29:18 PM PDT 24 2809339154 ps
T234 /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.454655280 Jun 21 07:58:19 PM PDT 24 Jun 21 08:08:31 PM PDT 24 6803448684 ps
T1003 /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.547262570 Jun 21 08:13:30 PM PDT 24 Jun 21 08:24:29 PM PDT 24 4063470448 ps
T1004 /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.62651014 Jun 21 08:16:12 PM PDT 24 Jun 21 08:48:08 PM PDT 24 29559054350 ps
T345 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.2266673675 Jun 21 08:14:57 PM PDT 24 Jun 21 08:24:33 PM PDT 24 4395227740 ps
T280 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.2097630910 Jun 21 08:20:12 PM PDT 24 Jun 21 08:29:28 PM PDT 24 3662175092 ps
T758 /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.3465426604 Jun 21 08:34:46 PM PDT 24 Jun 21 08:41:04 PM PDT 24 4219771646 ps
T1005 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2620025275 Jun 21 08:12:47 PM PDT 24 Jun 21 08:23:37 PM PDT 24 4698992560 ps
T128 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4206896275 Jun 21 08:00:07 PM PDT 24 Jun 21 08:08:27 PM PDT 24 5290196244 ps
T797 /workspace/coverage/default/6.chip_sw_all_escalation_resets.3210859863 Jun 21 08:26:44 PM PDT 24 Jun 21 08:35:57 PM PDT 24 4463802546 ps
T1006 /workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.2075785669 Jun 21 08:04:13 PM PDT 24 Jun 21 08:08:40 PM PDT 24 3214050501 ps
T141 /workspace/coverage/default/0.chip_sw_usbdev_config_host.77105502 Jun 21 08:00:08 PM PDT 24 Jun 21 08:38:24 PM PDT 24 8735349940 ps
T1007 /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.3048492151 Jun 21 08:24:17 PM PDT 24 Jun 21 08:27:48 PM PDT 24 3355481230 ps
T1008 /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.1647562240 Jun 21 08:28:07 PM PDT 24 Jun 21 08:40:31 PM PDT 24 10508530967 ps
T772 /workspace/coverage/default/73.chip_sw_all_escalation_resets.1869862283 Jun 21 08:33:20 PM PDT 24 Jun 21 08:43:50 PM PDT 24 4870125684 ps
T1009 /workspace/coverage/default/1.chip_sw_clkmgr_jitter.3603456489 Jun 21 08:10:50 PM PDT 24 Jun 21 08:14:15 PM PDT 24 2630434875 ps
T770 /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.2750844095 Jun 21 08:32:52 PM PDT 24 Jun 21 08:39:53 PM PDT 24 3847947332 ps
T1010 /workspace/coverage/default/2.chip_sw_edn_kat.3754961153 Jun 21 08:20:12 PM PDT 24 Jun 21 08:30:53 PM PDT 24 3703094208 ps
T1011 /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.2297073299 Jun 21 08:29:39 PM PDT 24 Jun 21 08:38:14 PM PDT 24 4269717920 ps
T775 /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.3893689443 Jun 21 08:34:37 PM PDT 24 Jun 21 08:40:10 PM PDT 24 3376283850 ps
T1012 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.164386022 Jun 21 07:57:57 PM PDT 24 Jun 21 08:19:58 PM PDT 24 7300833052 ps
T223 /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.3721294410 Jun 21 08:04:08 PM PDT 24 Jun 21 09:39:22 PM PDT 24 48009120340 ps
T281 /workspace/coverage/default/0.chip_sw_data_integrity_escalation.102852164 Jun 21 07:57:30 PM PDT 24 Jun 21 08:10:04 PM PDT 24 5590506760 ps
T1013 /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.4070474787 Jun 21 08:16:08 PM PDT 24 Jun 21 08:24:02 PM PDT 24 4898227912 ps
T1014 /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.2812228285 Jun 21 07:58:37 PM PDT 24 Jun 21 08:09:26 PM PDT 24 5011702800 ps
T361 /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.691904429 Jun 21 08:18:19 PM PDT 24 Jun 21 08:30:37 PM PDT 24 19776725380 ps
T328 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.3774020605 Jun 21 08:15:44 PM PDT 24 Jun 21 08:28:46 PM PDT 24 4940051560 ps
T398 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.2590949724 Jun 21 08:06:40 PM PDT 24 Jun 21 09:49:21 PM PDT 24 24317284784 ps
T1015 /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.1605973060 Jun 21 07:59:58 PM PDT 24 Jun 21 08:08:49 PM PDT 24 4932836722 ps
T456 /workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.4080623663 Jun 21 08:04:17 PM PDT 24 Jun 21 09:01:13 PM PDT 24 42205859494 ps
T1016 /workspace/coverage/default/1.chip_sw_uart_smoketest.3994596222 Jun 21 08:14:45 PM PDT 24 Jun 21 08:18:36 PM PDT 24 3387796430 ps
T1017 /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.1919160958 Jun 21 08:00:42 PM PDT 24 Jun 21 08:06:50 PM PDT 24 2339917044 ps
T469 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.2183252775 Jun 21 08:09:29 PM PDT 24 Jun 21 09:19:37 PM PDT 24 19021057936 ps
T17 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.1111804682 Jun 21 08:03:11 PM PDT 24 Jun 21 08:36:12 PM PDT 24 22157743186 ps
T1018 /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2650719787 Jun 21 08:25:36 PM PDT 24 Jun 21 08:52:02 PM PDT 24 8146206344 ps
T1019 /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.359680433 Jun 21 08:07:07 PM PDT 24 Jun 21 08:29:24 PM PDT 24 5934313376 ps
T150 /workspace/coverage/default/2.chip_plic_all_irqs_10.3388755525 Jun 21 08:21:27 PM PDT 24 Jun 21 08:31:03 PM PDT 24 3815412590 ps
T1020 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.190096159 Jun 21 08:00:25 PM PDT 24 Jun 21 08:19:26 PM PDT 24 11552360031 ps
T1021 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.2165397583 Jun 21 08:10:11 PM PDT 24 Jun 21 08:19:20 PM PDT 24 6503004568 ps
T1022 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2285435854 Jun 21 08:04:27 PM PDT 24 Jun 21 08:30:41 PM PDT 24 15737343445 ps
T1023 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.1596661354 Jun 21 08:04:10 PM PDT 24 Jun 21 08:12:49 PM PDT 24 6203043960 ps
T1024 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.2826635714 Jun 21 08:24:38 PM PDT 24 Jun 21 09:29:28 PM PDT 24 15028435226 ps
T340 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.3968765800 Jun 21 07:58:00 PM PDT 24 Jun 21 08:09:19 PM PDT 24 4584957708 ps
T1025 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.3558140350 Jun 21 08:05:57 PM PDT 24 Jun 21 09:47:14 PM PDT 24 24904171692 ps
T282 /workspace/coverage/default/3.chip_sw_data_integrity_escalation.4277728611 Jun 21 08:24:35 PM PDT 24 Jun 21 08:35:32 PM PDT 24 6434012712 ps
T151 /workspace/coverage/default/0.chip_plic_all_irqs_10.3212075741 Jun 21 07:59:27 PM PDT 24 Jun 21 08:09:22 PM PDT 24 3673045480 ps
T224 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.3407815341 Jun 21 08:18:07 PM PDT 24 Jun 21 09:49:28 PM PDT 24 46678635280 ps
T1026 /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.576251313 Jun 21 08:26:24 PM PDT 24 Jun 21 08:34:29 PM PDT 24 7136342099 ps
T807 /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.1486025679 Jun 21 08:35:29 PM PDT 24 Jun 21 08:40:29 PM PDT 24 3639606876 ps
T1027 /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.2292973867 Jun 21 08:01:20 PM PDT 24 Jun 21 08:07:03 PM PDT 24 6340033392 ps
T1028 /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.4248745274 Jun 21 08:29:56 PM PDT 24 Jun 21 08:38:52 PM PDT 24 8067172286 ps
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