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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.10 95.49 93.94 95.40 94.74 97.53 99.51


Total test records in report: 2873
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T129 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.642645784 Jun 21 08:22:20 PM PDT 24 Jun 21 08:29:30 PM PDT 24 4776217596 ps
T377 /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3127626193 Jun 21 07:59:53 PM PDT 24 Jun 21 08:05:03 PM PDT 24 4674163590 ps
T156 /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2699419001 Jun 21 07:59:03 PM PDT 24 Jun 21 08:00:47 PM PDT 24 2875627968 ps
T691 /workspace/coverage/default/74.chip_sw_all_escalation_resets.2753723746 Jun 21 08:34:34 PM PDT 24 Jun 21 08:45:28 PM PDT 24 5777713920 ps
T1029 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.4128901752 Jun 21 08:27:16 PM PDT 24 Jun 21 09:24:34 PM PDT 24 14753890496 ps
T1030 /workspace/coverage/default/0.chip_sw_otbn_smoketest.3616259646 Jun 21 08:03:01 PM PDT 24 Jun 21 08:21:14 PM PDT 24 5781374648 ps
T1031 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1958171930 Jun 21 08:18:14 PM PDT 24 Jun 21 08:41:29 PM PDT 24 11630537181 ps
T1032 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3546561502 Jun 21 07:58:04 PM PDT 24 Jun 21 08:09:04 PM PDT 24 4573820822 ps
T764 /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.1410282723 Jun 21 08:33:31 PM PDT 24 Jun 21 08:40:05 PM PDT 24 3681568240 ps
T731 /workspace/coverage/default/63.chip_sw_all_escalation_resets.391784453 Jun 21 08:31:58 PM PDT 24 Jun 21 08:41:57 PM PDT 24 5944043634 ps
T1033 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.3497379709 Jun 21 08:03:45 PM PDT 24 Jun 21 08:26:36 PM PDT 24 9083561752 ps
T1034 /workspace/coverage/default/0.chip_sw_edn_auto_mode.864667739 Jun 21 07:58:43 PM PDT 24 Jun 21 08:17:25 PM PDT 24 4747484010 ps
T162 /workspace/coverage/default/9.chip_sw_all_escalation_resets.418968383 Jun 21 08:32:58 PM PDT 24 Jun 21 08:41:08 PM PDT 24 6069391120 ps
T1035 /workspace/coverage/default/38.chip_sw_all_escalation_resets.972409453 Jun 21 08:30:43 PM PDT 24 Jun 21 08:39:05 PM PDT 24 5279648550 ps
T1036 /workspace/coverage/default/0.chip_sw_hmac_smoketest.2032502629 Jun 21 08:06:18 PM PDT 24 Jun 21 08:11:39 PM PDT 24 3591986502 ps
T14 /workspace/coverage/default/0.chip_sw_sleep_pin_wake.3284520848 Jun 21 07:58:12 PM PDT 24 Jun 21 08:03:47 PM PDT 24 5752838284 ps
T426 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.3570890325 Jun 21 08:19:06 PM PDT 24 Jun 21 08:46:30 PM PDT 24 9975939877 ps
T427 /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.2740714697 Jun 21 08:28:52 PM PDT 24 Jun 21 08:34:55 PM PDT 24 3656979896 ps
T215 /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.218433549 Jun 21 08:08:27 PM PDT 24 Jun 21 08:35:56 PM PDT 24 7817752640 ps
T428 /workspace/coverage/default/1.chip_sw_aes_idle.815603520 Jun 21 08:06:09 PM PDT 24 Jun 21 08:10:21 PM PDT 24 2451309000 ps
T429 /workspace/coverage/default/23.chip_sw_all_escalation_resets.842237933 Jun 21 08:30:42 PM PDT 24 Jun 21 08:41:12 PM PDT 24 5026536896 ps
T430 /workspace/coverage/default/0.chip_sw_aes_entropy.4139880501 Jun 21 08:00:03 PM PDT 24 Jun 21 08:04:34 PM PDT 24 2982334934 ps
T431 /workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.122133788 Jun 21 08:32:00 PM PDT 24 Jun 21 10:30:49 PM PDT 24 37132920422 ps
T432 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.1766146112 Jun 21 08:06:38 PM PDT 24 Jun 21 08:58:38 PM PDT 24 11407245800 ps
T324 /workspace/coverage/default/2.chip_plic_all_irqs_0.1352505910 Jun 21 08:20:15 PM PDT 24 Jun 21 08:46:06 PM PDT 24 6257344980 ps
T753 /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.2586577234 Jun 21 08:09:45 PM PDT 24 Jun 21 08:17:14 PM PDT 24 3636632016 ps
T1037 /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.3457642740 Jun 21 07:59:10 PM PDT 24 Jun 21 08:08:36 PM PDT 24 5151430318 ps
T152 /workspace/coverage/default/1.chip_plic_all_irqs_10.2469934078 Jun 21 08:09:23 PM PDT 24 Jun 21 08:20:43 PM PDT 24 4356632440 ps
T1038 /workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.3665895506 Jun 21 08:25:17 PM PDT 24 Jun 21 09:00:41 PM PDT 24 8699596410 ps
T357 /workspace/coverage/default/49.chip_sw_all_escalation_resets.2041016349 Jun 21 08:31:12 PM PDT 24 Jun 21 08:40:02 PM PDT 24 4998295430 ps
T1039 /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.481882931 Jun 21 08:07:18 PM PDT 24 Jun 21 08:12:10 PM PDT 24 3075847096 ps
T1040 /workspace/coverage/default/1.chip_sw_alert_handler_escalation.3334383770 Jun 21 08:07:54 PM PDT 24 Jun 21 08:17:25 PM PDT 24 5452086276 ps
T226 /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.2519809103 Jun 21 08:21:42 PM PDT 24 Jun 21 08:55:15 PM PDT 24 25565721104 ps
T9 /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.3634635982 Jun 21 08:01:16 PM PDT 24 Jun 21 08:07:54 PM PDT 24 3326794180 ps
T716 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.1861405018 Jun 21 08:06:23 PM PDT 24 Jun 21 08:59:01 PM PDT 24 11584684664 ps
T466 /workspace/coverage/default/2.chip_sw_kmac_entropy.1731115969 Jun 21 08:16:03 PM PDT 24 Jun 21 08:21:42 PM PDT 24 3067401632 ps
T717 /workspace/coverage/default/91.chip_sw_all_escalation_resets.810886380 Jun 21 08:35:11 PM PDT 24 Jun 21 08:45:34 PM PDT 24 5986372750 ps
T718 /workspace/coverage/default/1.chip_tap_straps_testunlock0.1687537190 Jun 21 08:11:29 PM PDT 24 Jun 21 08:14:56 PM PDT 24 3458586546 ps
T396 /workspace/coverage/default/1.chip_sw_edn_boot_mode.3450912059 Jun 21 08:07:03 PM PDT 24 Jun 21 08:16:37 PM PDT 24 3509484296 ps
T719 /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.2605563567 Jun 21 08:33:31 PM PDT 24 Jun 21 08:40:55 PM PDT 24 3796346032 ps
T296 /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.2605572077 Jun 21 08:03:18 PM PDT 24 Jun 21 08:09:34 PM PDT 24 2478980328 ps
T720 /workspace/coverage/default/81.chip_sw_all_escalation_resets.1425318229 Jun 21 08:35:16 PM PDT 24 Jun 21 08:45:20 PM PDT 24 4985191800 ps
T721 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3988111371 Jun 21 08:05:43 PM PDT 24 Jun 21 09:11:53 PM PDT 24 44957528128 ps
T1041 /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.3639488826 Jun 21 08:20:30 PM PDT 24 Jun 21 08:47:51 PM PDT 24 12959793250 ps
T1042 /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.3200157280 Jun 21 08:00:41 PM PDT 24 Jun 21 08:44:46 PM PDT 24 26337557000 ps
T130 /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.1380554801 Jun 21 08:27:39 PM PDT 24 Jun 21 08:39:00 PM PDT 24 8424410680 ps
T380 /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1872506592 Jun 21 08:32:34 PM PDT 24 Jun 21 08:37:42 PM PDT 24 3668607168 ps
T227 /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.150470448 Jun 21 08:15:47 PM PDT 24 Jun 21 08:23:21 PM PDT 24 5410756346 ps
T381 /workspace/coverage/default/0.chip_sw_edn_boot_mode.3603522558 Jun 21 07:59:08 PM PDT 24 Jun 21 08:10:51 PM PDT 24 3135341072 ps
T283 /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.3451870632 Jun 21 07:59:14 PM PDT 24 Jun 21 08:08:03 PM PDT 24 3456829228 ps
T382 /workspace/coverage/default/43.chip_sw_all_escalation_resets.644965065 Jun 21 08:32:17 PM PDT 24 Jun 21 08:39:29 PM PDT 24 4650986868 ps
T383 /workspace/coverage/default/66.chip_sw_all_escalation_resets.2067638193 Jun 21 08:35:52 PM PDT 24 Jun 21 08:46:59 PM PDT 24 4513893460 ps
T384 /workspace/coverage/default/0.chip_sw_hmac_enc_idle.3015256762 Jun 21 08:03:54 PM PDT 24 Jun 21 08:07:40 PM PDT 24 2682687480 ps
T216 /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.467591122 Jun 21 07:58:53 PM PDT 24 Jun 21 08:29:00 PM PDT 24 9566440752 ps
T385 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.2790994413 Jun 21 08:07:36 PM PDT 24 Jun 21 08:18:36 PM PDT 24 3655684364 ps
T44 /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.2982301113 Jun 21 08:16:27 PM PDT 24 Jun 21 08:20:22 PM PDT 24 2228283352 ps
T1043 /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.2381124050 Jun 21 08:27:43 PM PDT 24 Jun 21 08:56:25 PM PDT 24 8565649132 ps
T371 /workspace/coverage/default/2.chip_sw_aon_timer_irq.939252630 Jun 21 08:17:41 PM PDT 24 Jun 21 08:24:59 PM PDT 24 3831726052 ps
T1044 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.3718610321 Jun 21 08:20:12 PM PDT 24 Jun 21 08:54:27 PM PDT 24 11553078332 ps
T1045 /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2365982048 Jun 21 08:19:05 PM PDT 24 Jun 21 11:25:06 PM PDT 24 254654659152 ps
T1046 /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.1899097769 Jun 21 08:00:40 PM PDT 24 Jun 21 08:05:57 PM PDT 24 3287028360 ps
T228 /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.3801696387 Jun 21 08:09:30 PM PDT 24 Jun 21 09:45:19 PM PDT 24 48263901164 ps
T1047 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3811880117 Jun 21 08:24:21 PM PDT 24 Jun 21 08:31:09 PM PDT 24 3547333349 ps
T1048 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3443718499 Jun 21 08:13:02 PM PDT 24 Jun 21 08:22:43 PM PDT 24 4662439208 ps
T1049 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.2456067754 Jun 21 08:06:02 PM PDT 24 Jun 21 08:17:23 PM PDT 24 4815539370 ps
T814 /workspace/coverage/default/70.chip_sw_all_escalation_resets.208807714 Jun 21 08:34:30 PM PDT 24 Jun 21 08:43:16 PM PDT 24 5482491464 ps
T1050 /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.333704563 Jun 21 08:05:09 PM PDT 24 Jun 21 08:28:13 PM PDT 24 9573266833 ps
T1051 /workspace/coverage/default/1.rom_keymgr_functest.161935198 Jun 21 08:19:27 PM PDT 24 Jun 21 08:30:30 PM PDT 24 5351626372 ps
T1052 /workspace/coverage/default/2.chip_sw_example_rom.294920248 Jun 21 08:13:05 PM PDT 24 Jun 21 08:15:33 PM PDT 24 2813509830 ps
T1053 /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.2486283203 Jun 21 07:59:06 PM PDT 24 Jun 21 08:10:14 PM PDT 24 5589087720 ps
T1054 /workspace/coverage/default/3.chip_tap_straps_rma.662850341 Jun 21 08:25:50 PM PDT 24 Jun 21 08:33:33 PM PDT 24 4946215087 ps
T351 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.258775331 Jun 21 08:07:15 PM PDT 24 Jun 21 08:21:40 PM PDT 24 5161615592 ps
T762 /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.1520500079 Jun 21 08:31:22 PM PDT 24 Jun 21 08:39:06 PM PDT 24 3985227450 ps
T1055 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.2385539742 Jun 21 08:12:03 PM PDT 24 Jun 21 08:17:06 PM PDT 24 3567566524 ps
T1056 /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.373461011 Jun 21 08:00:20 PM PDT 24 Jun 21 08:07:48 PM PDT 24 4852557808 ps
T1057 /workspace/coverage/default/1.chip_sw_kmac_idle.3521742493 Jun 21 08:09:01 PM PDT 24 Jun 21 08:11:52 PM PDT 24 2574444400 ps
T254 /workspace/coverage/default/78.chip_sw_all_escalation_resets.3324134246 Jun 21 08:35:27 PM PDT 24 Jun 21 08:43:46 PM PDT 24 4811387782 ps
T22 /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.1985152253 Jun 21 08:04:18 PM PDT 24 Jun 21 08:09:02 PM PDT 24 2939396412 ps
T23 /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3345184988 Jun 21 08:14:18 PM PDT 24 Jun 21 08:18:59 PM PDT 24 3289585653 ps
T1058 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.2322963819 Jun 21 07:58:23 PM PDT 24 Jun 21 09:28:43 PM PDT 24 48504058595 ps
T1059 /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.1847062690 Jun 21 08:09:17 PM PDT 24 Jun 21 08:16:22 PM PDT 24 4517493140 ps
T1060 /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.3850551180 Jun 21 08:06:13 PM PDT 24 Jun 21 08:16:17 PM PDT 24 5754350574 ps
T780 /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.2479709753 Jun 21 08:34:41 PM PDT 24 Jun 21 08:39:52 PM PDT 24 3550025940 ps
T1061 /workspace/coverage/default/2.chip_sw_power_idle_load.2227027038 Jun 21 08:24:18 PM PDT 24 Jun 21 08:34:22 PM PDT 24 4738574454 ps
T1062 /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.3115844171 Jun 21 08:27:59 PM PDT 24 Jun 21 09:25:36 PM PDT 24 16453479048 ps
T229 /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.1684579205 Jun 21 07:59:34 PM PDT 24 Jun 21 08:38:59 PM PDT 24 18653600777 ps
T1063 /workspace/coverage/default/1.chip_sw_hmac_enc_idle.3305995720 Jun 21 08:07:40 PM PDT 24 Jun 21 08:11:42 PM PDT 24 3567323292 ps
T1064 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.1143459359 Jun 21 08:09:26 PM PDT 24 Jun 21 08:21:52 PM PDT 24 4891931441 ps
T1065 /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.3203211974 Jun 21 08:04:23 PM PDT 24 Jun 21 08:11:57 PM PDT 24 3684501880 ps
T1066 /workspace/coverage/default/2.chip_sw_example_flash.546654281 Jun 21 08:16:06 PM PDT 24 Jun 21 08:20:50 PM PDT 24 2821665562 ps
T1067 /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.852789885 Jun 21 08:09:01 PM PDT 24 Jun 21 08:12:36 PM PDT 24 2102128038 ps
T1068 /workspace/coverage/default/2.chip_tap_straps_prod.1822717076 Jun 21 08:22:22 PM PDT 24 Jun 21 08:25:18 PM PDT 24 2306748644 ps
T801 /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3084445991 Jun 21 08:32:56 PM PDT 24 Jun 21 08:42:37 PM PDT 24 3662721032 ps
T471 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3060029109 Jun 21 08:05:31 PM PDT 24 Jun 21 09:12:56 PM PDT 24 24852393817 ps
T689 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.1811751475 Jun 21 08:11:13 PM PDT 24 Jun 21 08:30:26 PM PDT 24 11088304712 ps
T765 /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.4233428944 Jun 21 08:25:52 PM PDT 24 Jun 21 08:32:52 PM PDT 24 3241968558 ps
T1069 /workspace/coverage/default/1.chip_sw_otbn_randomness.459237967 Jun 21 08:05:48 PM PDT 24 Jun 21 08:23:19 PM PDT 24 5420364120 ps
T1070 /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.3177115827 Jun 21 08:13:27 PM PDT 24 Jun 21 08:32:39 PM PDT 24 6047142200 ps
T1071 /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.460387385 Jun 21 08:09:21 PM PDT 24 Jun 21 09:00:53 PM PDT 24 23409238372 ps
T827 /workspace/coverage/default/52.chip_sw_all_escalation_resets.1276757729 Jun 21 08:31:59 PM PDT 24 Jun 21 08:42:22 PM PDT 24 4861520000 ps
T734 /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.1377970737 Jun 21 08:29:39 PM PDT 24 Jun 21 08:35:15 PM PDT 24 3689787896 ps
T1072 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3168421235 Jun 21 08:12:30 PM PDT 24 Jun 21 08:24:21 PM PDT 24 4653759371 ps
T1073 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.1600356326 Jun 21 08:24:33 PM PDT 24 Jun 21 08:37:24 PM PDT 24 4566312208 ps
T736 /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3399497621 Jun 21 08:31:56 PM PDT 24 Jun 21 08:37:41 PM PDT 24 3066895296 ps
T1074 /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.3840350142 Jun 21 08:03:49 PM PDT 24 Jun 21 08:06:47 PM PDT 24 2948552810 ps
T1075 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.408616826 Jun 21 08:03:43 PM PDT 24 Jun 21 08:13:56 PM PDT 24 5748249940 ps
T472 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3830665088 Jun 21 08:22:33 PM PDT 24 Jun 21 09:25:02 PM PDT 24 24724266223 ps
T1076 /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.306554217 Jun 21 08:20:46 PM PDT 24 Jun 21 08:34:48 PM PDT 24 6989807350 ps
T1077 /workspace/coverage/default/24.chip_sw_all_escalation_resets.4068210592 Jun 21 08:30:00 PM PDT 24 Jun 21 08:42:01 PM PDT 24 5615122556 ps
T1078 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.579954324 Jun 21 08:03:12 PM PDT 24 Jun 21 08:17:02 PM PDT 24 4465308448 ps
T1079 /workspace/coverage/default/2.chip_sw_flash_ctrl_access.1254472705 Jun 21 08:14:23 PM PDT 24 Jun 21 08:33:20 PM PDT 24 5678864168 ps
T1080 /workspace/coverage/default/2.chip_sw_edn_sw_mode.3125553048 Jun 21 08:20:58 PM PDT 24 Jun 21 08:57:50 PM PDT 24 10797071776 ps
T1081 /workspace/coverage/default/56.chip_sw_all_escalation_resets.1231355712 Jun 21 08:32:47 PM PDT 24 Jun 21 08:44:59 PM PDT 24 4953095268 ps
T742 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.3465277384 Jun 21 07:58:56 PM PDT 24 Jun 21 08:06:19 PM PDT 24 3936087400 ps
T303 /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.284874790 Jun 21 08:20:36 PM PDT 24 Jun 21 08:39:30 PM PDT 24 8296986198 ps
T683 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.455907446 Jun 21 08:15:55 PM PDT 24 Jun 21 08:18:00 PM PDT 24 2701871785 ps
T1082 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.1361340573 Jun 21 08:24:56 PM PDT 24 Jun 21 09:41:15 PM PDT 24 14929839850 ps
T195 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.2065541135 Jun 21 08:05:25 PM PDT 24 Jun 21 08:16:58 PM PDT 24 5582453118 ps
T1083 /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.2038366198 Jun 21 08:22:11 PM PDT 24 Jun 21 08:28:17 PM PDT 24 3365652384 ps
T1084 /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.440757181 Jun 21 08:24:37 PM PDT 24 Jun 21 08:32:01 PM PDT 24 2992966200 ps
T1085 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.2801313909 Jun 21 08:07:37 PM PDT 24 Jun 21 08:37:05 PM PDT 24 7760355336 ps
T196 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.172681586 Jun 21 08:03:35 PM PDT 24 Jun 21 08:34:21 PM PDT 24 24141818666 ps
T378 /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1194322493 Jun 21 08:13:05 PM PDT 24 Jun 21 08:18:12 PM PDT 24 5138296320 ps
T1086 /workspace/coverage/default/0.chip_tap_straps_prod.3204119168 Jun 21 08:00:26 PM PDT 24 Jun 21 08:23:54 PM PDT 24 13431409753 ps
T684 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.3634654217 Jun 21 08:00:35 PM PDT 24 Jun 21 08:02:33 PM PDT 24 3066309657 ps
T1087 /workspace/coverage/default/2.chip_sw_edn_auto_mode.3531029159 Jun 21 08:19:28 PM PDT 24 Jun 21 08:45:14 PM PDT 24 5869177550 ps
T1088 /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.1292705538 Jun 21 08:27:03 PM PDT 24 Jun 21 08:56:16 PM PDT 24 8351117080 ps
T791 /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.3659695957 Jun 21 08:29:07 PM PDT 24 Jun 21 08:35:32 PM PDT 24 3569159082 ps
T1089 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3759082829 Jun 21 08:26:27 PM PDT 24 Jun 21 08:32:58 PM PDT 24 3690896652 ps
T726 /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.99256349 Jun 21 08:06:39 PM PDT 24 Jun 21 08:22:21 PM PDT 24 5092001802 ps
T737 /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.2065019375 Jun 21 08:29:22 PM PDT 24 Jun 21 08:37:42 PM PDT 24 3971703480 ps
T817 /workspace/coverage/default/84.chip_sw_all_escalation_resets.2848051211 Jun 21 08:35:49 PM PDT 24 Jun 21 08:45:22 PM PDT 24 5857387270 ps
T757 /workspace/coverage/default/83.chip_sw_all_escalation_resets.1580990103 Jun 21 08:34:25 PM PDT 24 Jun 21 08:43:52 PM PDT 24 5293842056 ps
T1090 /workspace/coverage/default/1.chip_sw_edn_auto_mode.2873781967 Jun 21 08:07:09 PM PDT 24 Jun 21 08:27:06 PM PDT 24 4858730806 ps
T1091 /workspace/coverage/default/1.chip_sw_aes_masking_off.3710832313 Jun 21 08:08:30 PM PDT 24 Jun 21 08:14:25 PM PDT 24 3121720961 ps
T819 /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.2528644277 Jun 21 08:31:08 PM PDT 24 Jun 21 08:36:57 PM PDT 24 3103476136 ps
T1092 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.3212315723 Jun 21 08:09:09 PM PDT 24 Jun 21 08:18:26 PM PDT 24 4304392700 ps
T268 /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.415169187 Jun 21 08:15:29 PM PDT 24 Jun 21 08:19:55 PM PDT 24 3359106297 ps
T364 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3775832533 Jun 21 08:12:50 PM PDT 24 Jun 21 08:26:43 PM PDT 24 5418575299 ps
T1093 /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1218128420 Jun 21 08:24:20 PM PDT 24 Jun 21 08:32:03 PM PDT 24 6779364816 ps
T1094 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2857266812 Jun 21 08:04:42 PM PDT 24 Jun 21 08:48:52 PM PDT 24 20462984156 ps
T1095 /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.3635030543 Jun 21 08:19:53 PM PDT 24 Jun 21 08:25:19 PM PDT 24 3385743858 ps
T743 /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.2596929018 Jun 21 08:30:03 PM PDT 24 Jun 21 08:39:07 PM PDT 24 4016830016 ps
T1096 /workspace/coverage/default/67.chip_sw_all_escalation_resets.2149157438 Jun 21 08:32:44 PM PDT 24 Jun 21 08:42:44 PM PDT 24 6436494592 ps
T1097 /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.2420344358 Jun 21 08:03:56 PM PDT 24 Jun 21 08:08:46 PM PDT 24 3488662760 ps
T702 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.2511104608 Jun 21 08:03:22 PM PDT 24 Jun 21 08:07:46 PM PDT 24 2534129630 ps
T1098 /workspace/coverage/default/2.chip_tap_straps_testunlock0.2782720698 Jun 21 08:20:59 PM PDT 24 Jun 21 08:28:03 PM PDT 24 4555326313 ps
T1099 /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.1008872442 Jun 21 08:27:54 PM PDT 24 Jun 21 08:36:48 PM PDT 24 3245378292 ps
T1100 /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.1002630086 Jun 21 08:15:21 PM PDT 24 Jun 21 08:24:23 PM PDT 24 6733114506 ps
T1101 /workspace/coverage/default/1.chip_sw_flash_crash_alert.1782816159 Jun 21 08:11:41 PM PDT 24 Jun 21 08:22:12 PM PDT 24 6155126960 ps
T297 /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.4289679766 Jun 21 08:00:49 PM PDT 24 Jun 21 08:06:02 PM PDT 24 2934756943 ps
T197 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.4258691442 Jun 21 08:05:35 PM PDT 24 Jun 21 08:13:36 PM PDT 24 2900130264 ps
T1102 /workspace/coverage/default/0.chip_sw_aes_smoketest.3093208304 Jun 21 08:03:56 PM PDT 24 Jun 21 08:07:55 PM PDT 24 2350379612 ps
T242 /workspace/coverage/default/2.chip_sw_plic_sw_irq.782803749 Jun 21 08:19:43 PM PDT 24 Jun 21 08:23:32 PM PDT 24 2587771876 ps
T809 /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.1649136707 Jun 21 08:35:11 PM PDT 24 Jun 21 08:40:31 PM PDT 24 3494650472 ps
T10 /workspace/coverage/default/1.chip_jtag_csr_rw.789542222 Jun 21 08:03:44 PM PDT 24 Jun 21 08:44:36 PM PDT 24 20956784089 ps
T433 /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.657948832 Jun 21 08:28:42 PM PDT 24 Jun 21 08:43:08 PM PDT 24 11712612176 ps
T230 /workspace/coverage/default/1.chip_sw_flash_init.3158541307 Jun 21 08:03:18 PM PDT 24 Jun 21 08:40:36 PM PDT 24 21050180777 ps
T91 /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.1556777364 Jun 21 08:29:52 PM PDT 24 Jun 21 08:37:10 PM PDT 24 3559949080 ps
T434 /workspace/coverage/default/58.chip_sw_all_escalation_resets.2685803048 Jun 21 08:31:41 PM PDT 24 Jun 21 08:43:08 PM PDT 24 5711477346 ps
T435 /workspace/coverage/default/2.chip_sw_clkmgr_jitter.3572503437 Jun 21 08:21:41 PM PDT 24 Jun 21 08:24:27 PM PDT 24 2634257168 ps
T436 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.4030726139 Jun 21 08:16:44 PM PDT 24 Jun 21 08:23:46 PM PDT 24 7010165160 ps
T437 /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.947169261 Jun 21 08:27:25 PM PDT 24 Jun 21 08:50:06 PM PDT 24 7486621560 ps
T438 /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.2681365965 Jun 21 08:17:07 PM PDT 24 Jun 21 08:23:26 PM PDT 24 6254863920 ps
T439 /workspace/coverage/default/1.chip_sw_example_rom.978709379 Jun 21 08:01:31 PM PDT 24 Jun 21 08:03:43 PM PDT 24 2852477194 ps
T467 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.1975040945 Jun 21 08:19:26 PM PDT 24 Jun 21 08:36:47 PM PDT 24 5620693896 ps
T1103 /workspace/coverage/default/0.chip_sw_uart_tx_rx.4172638079 Jun 21 08:00:45 PM PDT 24 Jun 21 08:10:44 PM PDT 24 4094264184 ps
T1104 /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.716006768 Jun 21 07:58:54 PM PDT 24 Jun 21 08:04:17 PM PDT 24 2771720258 ps
T1105 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1556100943 Jun 21 08:13:01 PM PDT 24 Jun 21 09:35:51 PM PDT 24 24605481513 ps
T1106 /workspace/coverage/default/48.chip_sw_all_escalation_resets.798603146 Jun 21 08:32:06 PM PDT 24 Jun 21 08:42:24 PM PDT 24 3861109712 ps
T744 /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.393537734 Jun 21 08:29:58 PM PDT 24 Jun 21 08:36:26 PM PDT 24 3017807720 ps
T1107 /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.2424392526 Jun 21 08:17:06 PM PDT 24 Jun 21 08:39:21 PM PDT 24 8668503945 ps
T773 /workspace/coverage/default/18.chip_sw_all_escalation_resets.3275552215 Jun 21 08:28:35 PM PDT 24 Jun 21 08:37:58 PM PDT 24 4731693280 ps
T1108 /workspace/coverage/default/1.rom_e2e_asm_init_rma.109117252 Jun 21 08:23:26 PM PDT 24 Jun 21 09:29:26 PM PDT 24 15241382206 ps
T1109 /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.1794312748 Jun 21 08:04:46 PM PDT 24 Jun 21 08:23:02 PM PDT 24 7871760270 ps
T1110 /workspace/coverage/default/1.chip_sw_aes_entropy.2368398542 Jun 21 08:07:26 PM PDT 24 Jun 21 08:11:51 PM PDT 24 2769234144 ps
T777 /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2461419369 Jun 21 08:35:07 PM PDT 24 Jun 21 08:41:38 PM PDT 24 3996577988 ps
T84 /workspace/coverage/default/2.chip_sw_gpio_smoketest.3688350221 Jun 21 08:23:27 PM PDT 24 Jun 21 08:27:58 PM PDT 24 3004222191 ps
T1111 /workspace/coverage/default/1.chip_sw_edn_sw_mode.2245905492 Jun 21 08:07:18 PM PDT 24 Jun 21 08:31:27 PM PDT 24 5986732628 ps
T1112 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1480003928 Jun 21 08:01:03 PM PDT 24 Jun 21 08:12:36 PM PDT 24 4018258992 ps
T1113 /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.1121016972 Jun 21 08:16:18 PM PDT 24 Jun 21 08:36:07 PM PDT 24 5740066509 ps
T1114 /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.2309322822 Jun 21 08:13:51 PM PDT 24 Jun 21 08:17:49 PM PDT 24 2677986300 ps
T304 /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.2659084207 Jun 21 08:08:31 PM PDT 24 Jun 21 08:18:04 PM PDT 24 8053440093 ps
T1115 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.847172462 Jun 21 08:07:08 PM PDT 24 Jun 21 09:07:53 PM PDT 24 17484041616 ps
T774 /workspace/coverage/default/68.chip_sw_all_escalation_resets.2708100423 Jun 21 08:32:38 PM PDT 24 Jun 21 08:43:40 PM PDT 24 6370368680 ps
T1116 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.1556408476 Jun 21 08:00:48 PM PDT 24 Jun 21 08:11:52 PM PDT 24 4694411903 ps
T1117 /workspace/coverage/default/0.chip_sw_aes_masking_off.2481295370 Jun 21 08:01:56 PM PDT 24 Jun 21 08:08:11 PM PDT 24 2808487621 ps
T255 /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.1875727606 Jun 21 08:05:19 PM PDT 24 Jun 21 08:15:47 PM PDT 24 5770916846 ps
T1118 /workspace/coverage/default/1.rom_e2e_static_critical.1356386154 Jun 21 08:24:48 PM PDT 24 Jun 21 09:45:08 PM PDT 24 17304159360 ps
T1119 /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.982396082 Jun 21 08:08:50 PM PDT 24 Jun 21 08:51:50 PM PDT 24 12663761300 ps
T1120 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.2301840824 Jun 21 08:05:43 PM PDT 24 Jun 21 09:08:19 PM PDT 24 15770788080 ps
T795 /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.2031043577 Jun 21 08:32:02 PM PDT 24 Jun 21 08:42:38 PM PDT 24 4702674108 ps
T1121 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.301295423 Jun 21 08:02:45 PM PDT 24 Jun 21 08:15:31 PM PDT 24 4375540556 ps
T219 /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.1360516859 Jun 21 08:19:44 PM PDT 24 Jun 21 09:07:32 PM PDT 24 12963624616 ps
T1122 /workspace/coverage/default/1.chip_sw_edn_kat.2759892226 Jun 21 08:07:20 PM PDT 24 Jun 21 08:16:51 PM PDT 24 3697846580 ps
T1123 /workspace/coverage/default/0.chip_sw_usbdev_setuprx.3228284003 Jun 21 07:58:25 PM PDT 24 Jun 21 08:07:41 PM PDT 24 4026328498 ps
T1124 /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.3591602738 Jun 21 08:15:19 PM PDT 24 Jun 21 08:20:28 PM PDT 24 3469791962 ps
T220 /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.201720177 Jun 21 08:01:15 PM PDT 24 Jun 21 09:04:00 PM PDT 24 13113515768 ps
T1125 /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.2275104812 Jun 21 08:28:21 PM PDT 24 Jun 21 08:39:16 PM PDT 24 4115669936 ps
T1126 /workspace/coverage/default/1.chip_sw_kmac_smoketest.3830196550 Jun 21 08:15:05 PM PDT 24 Jun 21 08:19:42 PM PDT 24 3300551096 ps
T1127 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.184538289 Jun 21 08:17:31 PM PDT 24 Jun 21 09:13:05 PM PDT 24 18803354857 ps
T781 /workspace/coverage/default/25.chip_sw_all_escalation_resets.3238810809 Jun 21 08:28:57 PM PDT 24 Jun 21 08:40:41 PM PDT 24 6085129252 ps
T342 /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.930591847 Jun 21 08:16:34 PM PDT 24 Jun 21 08:26:57 PM PDT 24 4416120332 ps
T1128 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.1301461402 Jun 21 08:01:41 PM PDT 24 Jun 21 08:14:29 PM PDT 24 4332578940 ps
T1129 /workspace/coverage/default/0.rom_keymgr_functest.1677940232 Jun 21 08:04:00 PM PDT 24 Jun 21 08:11:11 PM PDT 24 3742071806 ps
T473 /workspace/coverage/default/2.chip_sw_edn_boot_mode.750864502 Jun 21 08:20:51 PM PDT 24 Jun 21 08:30:43 PM PDT 24 2814249408 ps
T1130 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.2584954462 Jun 21 08:05:22 PM PDT 24 Jun 21 08:08:50 PM PDT 24 3012239129 ps
T824 /workspace/coverage/default/42.chip_sw_all_escalation_resets.373240884 Jun 21 08:30:25 PM PDT 24 Jun 21 08:41:55 PM PDT 24 5869543940 ps
T1131 /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.1908698655 Jun 21 08:14:36 PM PDT 24 Jun 21 08:18:03 PM PDT 24 3305365614 ps
T1132 /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.1734397106 Jun 21 08:11:34 PM PDT 24 Jun 21 08:20:16 PM PDT 24 3747978296 ps
T243 /workspace/coverage/default/0.chip_sw_plic_sw_irq.660134636 Jun 21 07:59:52 PM PDT 24 Jun 21 08:05:19 PM PDT 24 3265253336 ps
T1133 /workspace/coverage/default/1.chip_sw_example_manufacturer.3423893201 Jun 21 08:06:45 PM PDT 24 Jun 21 08:11:01 PM PDT 24 3287720728 ps
T1134 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.3751217662 Jun 21 08:02:26 PM PDT 24 Jun 21 08:38:52 PM PDT 24 9319253624 ps
T1135 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.3795476447 Jun 21 07:58:56 PM PDT 24 Jun 21 08:07:07 PM PDT 24 4050870695 ps
T362 /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.2943169721 Jun 21 08:11:09 PM PDT 24 Jun 21 08:15:27 PM PDT 24 2835753349 ps
T1136 /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.2286722289 Jun 21 08:11:05 PM PDT 24 Jun 21 08:36:59 PM PDT 24 10189289672 ps
T1137 /workspace/coverage/default/1.chip_sw_aes_smoketest.1427712143 Jun 21 08:12:28 PM PDT 24 Jun 21 08:16:03 PM PDT 24 3524427644 ps
T1138 /workspace/coverage/default/0.chip_tap_straps_rma.2595612241 Jun 21 07:59:25 PM PDT 24 Jun 21 08:06:19 PM PDT 24 4801125609 ps
T805 /workspace/coverage/default/7.chip_sw_all_escalation_resets.302259980 Jun 21 08:27:00 PM PDT 24 Jun 21 08:38:40 PM PDT 24 5297454410 ps
T1139 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.2869602396 Jun 21 08:11:00 PM PDT 24 Jun 21 08:27:40 PM PDT 24 10360617319 ps
T1140 /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.1308836046 Jun 21 08:27:26 PM PDT 24 Jun 21 09:07:16 PM PDT 24 13962161800 ps
T1141 /workspace/coverage/default/2.chip_sw_hmac_enc_idle.3632544305 Jun 21 08:19:16 PM PDT 24 Jun 21 08:24:44 PM PDT 24 3110751616 ps
T1142 /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.2222025022 Jun 21 08:08:50 PM PDT 24 Jun 21 08:19:23 PM PDT 24 8798531054 ps
T1143 /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.965516598 Jun 21 08:17:47 PM PDT 24 Jun 21 08:24:45 PM PDT 24 3821185168 ps
T330 /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.294894164 Jun 21 08:05:03 PM PDT 24 Jun 21 08:37:22 PM PDT 24 11703995416 ps
T1144 /workspace/coverage/default/1.chip_sw_ast_clk_outputs.3339799872 Jun 21 08:12:28 PM PDT 24 Jun 21 08:27:19 PM PDT 24 6526706220 ps
T703 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.2063662915 Jun 21 08:05:37 PM PDT 24 Jun 21 08:10:11 PM PDT 24 2647639160 ps
T1145 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1632658967 Jun 21 08:03:32 PM PDT 24 Jun 21 08:05:23 PM PDT 24 2487357477 ps
T808 /workspace/coverage/default/65.chip_sw_all_escalation_resets.2957972927 Jun 21 08:33:16 PM PDT 24 Jun 21 08:45:05 PM PDT 24 6719455176 ps
T1146 /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.2721613080 Jun 21 08:32:03 PM PDT 24 Jun 21 08:37:55 PM PDT 24 3801416978 ps
T1147 /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.1219349026 Jun 21 08:00:44 PM PDT 24 Jun 21 08:05:43 PM PDT 24 5744578024 ps
T1148 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.4228936587 Jun 21 08:06:11 PM PDT 24 Jun 21 09:06:16 PM PDT 24 14558039392 ps
T1149 /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.211050526 Jun 21 08:13:46 PM PDT 24 Jun 21 08:21:04 PM PDT 24 3055072840 ps
T1150 /workspace/coverage/default/2.rom_e2e_static_critical.3299256589 Jun 21 08:29:09 PM PDT 24 Jun 21 09:32:15 PM PDT 24 17571265720 ps
T1151 /workspace/coverage/default/2.chip_sw_alert_handler_entropy.934595443 Jun 21 08:18:45 PM PDT 24 Jun 21 08:24:16 PM PDT 24 2923519653 ps
T58 /workspace/coverage/default/1.chip_sw_alert_test.3089139706 Jun 21 08:05:43 PM PDT 24 Jun 21 08:09:57 PM PDT 24 2995092250 ps
T1152 /workspace/coverage/default/2.chip_sw_aes_entropy.2706675855 Jun 21 08:20:19 PM PDT 24 Jun 21 08:25:01 PM PDT 24 2569534390 ps
T800 /workspace/coverage/default/89.chip_sw_all_escalation_resets.4172659240 Jun 21 08:35:48 PM PDT 24 Jun 21 08:44:21 PM PDT 24 4459246268 ps
T1153 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.1343385535 Jun 21 08:02:51 PM PDT 24 Jun 21 08:18:46 PM PDT 24 5157991558 ps
T59 /workspace/coverage/default/0.chip_sw_alert_test.433454259 Jun 21 08:02:32 PM PDT 24 Jun 21 08:07:38 PM PDT 24 3062801770 ps
T1154 /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.656495449 Jun 21 08:01:48 PM PDT 24 Jun 21 08:09:35 PM PDT 24 3544977015 ps
T820 /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2074362638 Jun 21 08:32:50 PM PDT 24 Jun 21 08:39:10 PM PDT 24 3341452440 ps
T418 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.332505149 Jun 21 08:03:51 PM PDT 24 Jun 21 08:30:24 PM PDT 24 24712666640 ps
T1155 /workspace/coverage/default/0.chip_sw_ast_clk_outputs.2675872295 Jun 21 08:00:06 PM PDT 24 Jun 21 08:15:39 PM PDT 24 6848279694 ps
T1156 /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.3748400596 Jun 21 07:59:14 PM PDT 24 Jun 21 08:13:54 PM PDT 24 11459937606 ps
T326 /workspace/coverage/default/1.chip_plic_all_irqs_20.1957017252 Jun 21 08:10:10 PM PDT 24 Jun 21 08:22:40 PM PDT 24 5084938900 ps
T1157 /workspace/coverage/default/2.chip_sw_ast_clk_outputs.1510374961 Jun 21 08:21:20 PM PDT 24 Jun 21 08:37:36 PM PDT 24 6950816640 ps
T1158 /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.2487944893 Jun 21 08:09:43 PM PDT 24 Jun 21 08:18:04 PM PDT 24 4945817192 ps
T1159 /workspace/coverage/default/2.chip_sw_aes_masking_off.1980430388 Jun 21 08:20:31 PM PDT 24 Jun 21 08:27:39 PM PDT 24 3234384098 ps
T184 /workspace/coverage/default/1.chip_sw_spi_device_pass_through.3835249098 Jun 21 08:04:16 PM PDT 24 Jun 21 08:16:42 PM PDT 24 6106175722 ps
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