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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.10 95.49 93.94 95.40 94.74 97.53 99.51


Total test records in report: 2873
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T395 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.3679401439 Jun 21 07:58:16 PM PDT 24 Jun 21 08:15:03 PM PDT 24 5671673212 ps
T1160 /workspace/coverage/default/1.chip_sw_hmac_smoketest.3374944858 Jun 21 08:13:35 PM PDT 24 Jun 21 08:21:34 PM PDT 24 3793810760 ps
T1161 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.824558252 Jun 21 08:17:09 PM PDT 24 Jun 21 08:45:12 PM PDT 24 23149580344 ps
T811 /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.3882090202 Jun 21 08:32:34 PM PDT 24 Jun 21 08:39:42 PM PDT 24 3752510404 ps
T1162 /workspace/coverage/default/2.rom_e2e_asm_init_dev.3094169380 Jun 21 08:27:53 PM PDT 24 Jun 21 09:33:58 PM PDT 24 15967797100 ps
T1163 /workspace/coverage/default/1.chip_sw_csrng_kat_test.1810957241 Jun 21 08:08:13 PM PDT 24 Jun 21 08:12:33 PM PDT 24 3545866664 ps
T468 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.1537833847 Jun 21 08:08:14 PM PDT 24 Jun 21 08:22:34 PM PDT 24 5705692532 ps
T1164 /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.2935939086 Jun 21 08:26:07 PM PDT 24 Jun 21 08:30:09 PM PDT 24 3095132132 ps
T792 /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.3776237832 Jun 21 08:28:40 PM PDT 24 Jun 21 08:35:16 PM PDT 24 3706958668 ps
T346 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.73988965 Jun 21 07:58:17 PM PDT 24 Jun 21 08:09:53 PM PDT 24 4471701379 ps
T374 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.2923924307 Jun 21 08:13:11 PM PDT 24 Jun 21 08:17:41 PM PDT 24 3348010240 ps
T1165 /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.2087076911 Jun 21 08:22:57 PM PDT 24 Jun 21 08:28:30 PM PDT 24 3173548432 ps
T1166 /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3029236979 Jun 21 08:33:52 PM PDT 24 Jun 21 08:39:38 PM PDT 24 3598158312 ps
T343 /workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.953945782 Jun 21 08:12:30 PM PDT 24 Jun 21 08:22:03 PM PDT 24 4027948024 ps
T1167 /workspace/coverage/default/0.chip_sw_flash_ctrl_access.912086562 Jun 21 07:57:41 PM PDT 24 Jun 21 08:18:31 PM PDT 24 5433773876 ps
T1168 /workspace/coverage/default/0.chip_sw_kmac_entropy.819154394 Jun 21 07:57:11 PM PDT 24 Jun 21 08:00:54 PM PDT 24 2298412440 ps
T1169 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3578712268 Jun 21 08:12:13 PM PDT 24 Jun 21 08:39:25 PM PDT 24 9571148994 ps
T1170 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.3728055297 Jun 21 08:15:10 PM PDT 24 Jun 21 08:26:06 PM PDT 24 4276288916 ps
T1171 /workspace/coverage/default/0.chip_sw_aes_idle.1081668052 Jun 21 07:59:46 PM PDT 24 Jun 21 08:03:36 PM PDT 24 2625159096 ps
T1172 /workspace/coverage/default/0.chip_sw_uart_smoketest.215505888 Jun 21 08:04:36 PM PDT 24 Jun 21 08:10:06 PM PDT 24 3296400500 ps
T1173 /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1352567952 Jun 21 08:26:42 PM PDT 24 Jun 21 08:42:39 PM PDT 24 11963580193 ps
T1174 /workspace/coverage/default/0.chip_sw_aes_enc.1011394396 Jun 21 07:58:59 PM PDT 24 Jun 21 08:03:05 PM PDT 24 3009948408 ps
T1175 /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.2431939009 Jun 21 08:17:08 PM PDT 24 Jun 21 08:32:49 PM PDT 24 6370680888 ps
T1176 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.1066979113 Jun 21 08:08:54 PM PDT 24 Jun 21 08:15:00 PM PDT 24 2750246159 ps
T788 /workspace/coverage/default/75.chip_sw_all_escalation_resets.1361603571 Jun 21 08:33:46 PM PDT 24 Jun 21 08:43:35 PM PDT 24 4984582450 ps
T821 /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.409863256 Jun 21 08:31:17 PM PDT 24 Jun 21 08:37:29 PM PDT 24 3460685118 ps
T373 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.678439225 Jun 21 08:08:00 PM PDT 24 Jun 21 08:17:31 PM PDT 24 4124629148 ps
T1177 /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.1693473125 Jun 21 08:15:49 PM PDT 24 Jun 21 08:20:30 PM PDT 24 3174268960 ps
T818 /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1971304870 Jun 21 08:33:07 PM PDT 24 Jun 21 08:41:07 PM PDT 24 3905281028 ps
T769 /workspace/coverage/default/39.chip_sw_all_escalation_resets.187328596 Jun 21 08:32:12 PM PDT 24 Jun 21 08:40:48 PM PDT 24 5988103848 ps
T1178 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.2157095553 Jun 21 07:58:18 PM PDT 24 Jun 21 08:17:11 PM PDT 24 8143030852 ps
T681 /workspace/coverage/default/3.chip_tap_straps_dev.1736914265 Jun 21 08:24:28 PM PDT 24 Jun 21 08:38:47 PM PDT 24 9060529594 ps
T1179 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.1254837654 Jun 21 08:08:53 PM PDT 24 Jun 21 08:30:12 PM PDT 24 8005912008 ps
T1180 /workspace/coverage/default/0.rom_e2e_asm_init_dev.1248459676 Jun 21 08:10:04 PM PDT 24 Jun 21 09:23:37 PM PDT 24 16218052140 ps
T1181 /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.279173908 Jun 21 08:23:28 PM PDT 24 Jun 21 08:30:52 PM PDT 24 4131329992 ps
T803 /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.475661093 Jun 21 08:28:30 PM PDT 24 Jun 21 08:36:06 PM PDT 24 4096336216 ps
T1182 /workspace/coverage/default/53.chip_sw_all_escalation_resets.294695903 Jun 21 08:33:59 PM PDT 24 Jun 21 08:46:46 PM PDT 24 6557878196 ps
T1183 /workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.1636054692 Jun 21 08:27:05 PM PDT 24 Jun 21 09:45:03 PM PDT 24 17865502528 ps
T1184 /workspace/coverage/default/1.chip_sw_hmac_oneshot.434955322 Jun 21 08:08:18 PM PDT 24 Jun 21 08:13:49 PM PDT 24 3235216536 ps
T1185 /workspace/coverage/default/15.chip_sw_all_escalation_resets.3211263937 Jun 21 08:29:11 PM PDT 24 Jun 21 08:39:07 PM PDT 24 5012093168 ps
T46 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1825611915 Jun 21 08:00:56 PM PDT 24 Jun 21 08:08:18 PM PDT 24 5372689240 ps
T1186 /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.4261523398 Jun 21 08:20:09 PM PDT 24 Jun 21 08:24:19 PM PDT 24 2914509236 ps
T1187 /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.31085568 Jun 21 08:05:37 PM PDT 24 Jun 21 08:11:19 PM PDT 24 3630863128 ps
T1188 /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.328696537 Jun 21 08:21:59 PM PDT 24 Jun 21 08:30:16 PM PDT 24 4698180476 ps
T1189 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.20801342 Jun 21 08:09:44 PM PDT 24 Jun 21 09:22:53 PM PDT 24 16040350360 ps
T745 /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.2366709540 Jun 21 08:32:01 PM PDT 24 Jun 21 08:39:53 PM PDT 24 4215347414 ps
T1190 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.750908654 Jun 21 08:00:01 PM PDT 24 Jun 21 08:14:02 PM PDT 24 8041962430 ps
T1191 /workspace/coverage/default/0.chip_sw_aon_timer_irq.1996413321 Jun 21 08:01:05 PM PDT 24 Jun 21 08:08:32 PM PDT 24 4174613420 ps
T1192 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.1113017040 Jun 21 08:04:35 PM PDT 24 Jun 21 08:15:59 PM PDT 24 4309480616 ps
T185 /workspace/coverage/default/2.chip_sw_spi_device_pass_through.3334481042 Jun 21 08:16:45 PM PDT 24 Jun 21 08:31:52 PM PDT 24 7384129684 ps
T448 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1066380421 Jun 21 07:59:32 PM PDT 24 Jun 21 08:05:54 PM PDT 24 7295545916 ps
T1193 /workspace/coverage/default/0.chip_sw_power_sleep_load.3510249955 Jun 21 08:00:54 PM PDT 24 Jun 21 08:11:40 PM PDT 24 9929727130 ps
T332 /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.4183018663 Jun 21 07:59:36 PM PDT 24 Jun 21 08:34:43 PM PDT 24 14446445880 ps
T1194 /workspace/coverage/default/40.chip_sw_all_escalation_resets.3269713140 Jun 21 08:30:45 PM PDT 24 Jun 21 08:40:47 PM PDT 24 6196422904 ps
T1195 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.4070746938 Jun 21 08:23:44 PM PDT 24 Jun 21 08:29:35 PM PDT 24 3512332154 ps
T1196 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.3354842330 Jun 21 08:19:38 PM PDT 24 Jun 21 08:28:22 PM PDT 24 4981729880 ps
T1197 /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.1707664417 Jun 21 08:27:24 PM PDT 24 Jun 21 08:37:02 PM PDT 24 3695318680 ps
T1198 /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.4280391616 Jun 21 08:27:31 PM PDT 24 Jun 21 10:07:48 PM PDT 24 30006570880 ps
T1199 /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.957898873 Jun 21 08:06:09 PM PDT 24 Jun 21 08:11:54 PM PDT 24 2913951900 ps
T1200 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.3689381890 Jun 21 07:59:30 PM PDT 24 Jun 21 08:53:35 PM PDT 24 21022695643 ps
T1201 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.2920683431 Jun 21 07:59:45 PM PDT 24 Jun 21 08:40:50 PM PDT 24 9238563532 ps
T312 /workspace/coverage/default/4.chip_sw_all_escalation_resets.3470173278 Jun 21 08:26:33 PM PDT 24 Jun 21 08:38:03 PM PDT 24 4809470056 ps
T761 /workspace/coverage/default/64.chip_sw_all_escalation_resets.3439171862 Jun 21 08:33:27 PM PDT 24 Jun 21 08:42:44 PM PDT 24 5132929500 ps
T1202 /workspace/coverage/default/0.rom_e2e_asm_init_rma.4099105461 Jun 21 08:05:31 PM PDT 24 Jun 21 09:01:16 PM PDT 24 15078567911 ps
T1203 /workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.891192589 Jun 21 08:01:36 PM PDT 24 Jun 21 08:28:37 PM PDT 24 7673412100 ps
T1204 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.613755962 Jun 21 08:01:44 PM PDT 24 Jun 21 08:29:53 PM PDT 24 15678446274 ps
T1205 /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.2810479623 Jun 21 08:26:48 PM PDT 24 Jun 21 08:40:00 PM PDT 24 10360197720 ps
T1206 /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.2603472294 Jun 21 08:23:40 PM PDT 24 Jun 21 08:27:14 PM PDT 24 2817628724 ps
T1207 /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.3756063847 Jun 21 08:32:54 PM PDT 24 Jun 21 08:39:02 PM PDT 24 3961609284 ps
T1208 /workspace/coverage/default/1.chip_tap_straps_rma.4036486200 Jun 21 08:12:05 PM PDT 24 Jun 21 08:19:10 PM PDT 24 5357479939 ps
T741 /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.3175799949 Jun 21 08:33:15 PM PDT 24 Jun 21 08:39:38 PM PDT 24 3796807096 ps
T1209 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.1779258968 Jun 21 08:04:24 PM PDT 24 Jun 21 08:30:07 PM PDT 24 20912495016 ps
T1210 /workspace/coverage/default/0.chip_sw_alert_handler_entropy.2084883945 Jun 21 08:04:04 PM PDT 24 Jun 21 08:08:27 PM PDT 24 2479681398 ps
T1211 /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.413199937 Jun 21 08:29:09 PM PDT 24 Jun 21 09:12:28 PM PDT 24 11958932455 ps
T1212 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.3414922213 Jun 21 08:02:05 PM PDT 24 Jun 21 08:09:55 PM PDT 24 3229421888 ps
T804 /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.3203094371 Jun 21 08:36:59 PM PDT 24 Jun 21 08:43:26 PM PDT 24 3984971640 ps
T1213 /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.1437634211 Jun 21 08:27:15 PM PDT 24 Jun 21 08:31:53 PM PDT 24 3089115320 ps
T1214 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.254095002 Jun 21 08:16:01 PM PDT 24 Jun 21 08:35:35 PM PDT 24 7427654310 ps
T1215 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.2245181557 Jun 21 08:05:51 PM PDT 24 Jun 21 08:09:38 PM PDT 24 2643015566 ps
T1216 /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.1379899505 Jun 21 08:05:42 PM PDT 24 Jun 21 08:08:22 PM PDT 24 3175369180 ps
T1217 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.355835946 Jun 21 08:21:11 PM PDT 24 Jun 21 08:43:59 PM PDT 24 6375408299 ps
T1218 /workspace/coverage/default/0.chip_sw_flash_crash_alert.968100885 Jun 21 08:03:24 PM PDT 24 Jun 21 08:14:26 PM PDT 24 5963680832 ps
T1219 /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.3074109071 Jun 21 08:05:17 PM PDT 24 Jun 21 08:10:07 PM PDT 24 3591628994 ps
T1220 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.1274785578 Jun 21 08:00:39 PM PDT 24 Jun 21 08:40:34 PM PDT 24 9302616854 ps
T1221 /workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.2302134591 Jun 21 08:18:43 PM PDT 24 Jun 21 08:42:30 PM PDT 24 8073976712 ps
T1222 /workspace/coverage/default/59.chip_sw_all_escalation_resets.41312536 Jun 21 08:34:37 PM PDT 24 Jun 21 08:44:42 PM PDT 24 5105674532 ps
T785 /workspace/coverage/default/36.chip_sw_all_escalation_resets.1404407010 Jun 21 08:30:00 PM PDT 24 Jun 21 08:39:28 PM PDT 24 5594551188 ps
T15 /workspace/coverage/default/1.chip_sw_sleep_pin_wake.866853844 Jun 21 08:08:10 PM PDT 24 Jun 21 08:13:37 PM PDT 24 3655437900 ps
T1223 /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.4173005024 Jun 21 08:00:47 PM PDT 24 Jun 21 08:10:11 PM PDT 24 4861188764 ps
T1224 /workspace/coverage/default/0.chip_sw_example_flash.1259712827 Jun 21 07:58:14 PM PDT 24 Jun 21 08:03:27 PM PDT 24 2923496704 ps
T682 /workspace/coverage/default/4.chip_tap_straps_dev.244924851 Jun 21 08:26:14 PM PDT 24 Jun 21 08:45:59 PM PDT 24 11654655431 ps
T1225 /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.288269219 Jun 21 08:07:16 PM PDT 24 Jun 21 08:10:42 PM PDT 24 2384864248 ps
T335 /workspace/coverage/default/1.chip_sw_entropy_src_csrng.1140304737 Jun 21 08:08:03 PM PDT 24 Jun 21 08:28:21 PM PDT 24 5357712128 ps
T1226 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.3982979069 Jun 21 08:18:00 PM PDT 24 Jun 21 08:39:59 PM PDT 24 6820036802 ps
T1227 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.2847251012 Jun 21 08:10:14 PM PDT 24 Jun 21 09:15:45 PM PDT 24 15753961650 ps
T1228 /workspace/coverage/default/2.chip_sw_aes_idle.1497644566 Jun 21 08:19:19 PM PDT 24 Jun 21 08:23:32 PM PDT 24 2363905508 ps
T186 /workspace/coverage/default/1.chip_jtag_mem_access.2263036386 Jun 21 08:03:43 PM PDT 24 Jun 21 08:30:14 PM PDT 24 13694855795 ps
T288 /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.2050434729 Jun 21 08:33:40 PM PDT 24 Jun 21 08:38:50 PM PDT 24 4119704846 ps
T776 /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.1145098486 Jun 21 08:34:51 PM PDT 24 Jun 21 08:42:03 PM PDT 24 3569578536 ps
T1229 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.1372276447 Jun 21 08:04:22 PM PDT 24 Jun 21 08:17:25 PM PDT 24 5169821251 ps
T1230 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.3651657971 Jun 21 08:05:40 PM PDT 24 Jun 21 08:19:13 PM PDT 24 9009432072 ps
T256 /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.2974882603 Jun 21 08:16:21 PM PDT 24 Jun 21 08:27:49 PM PDT 24 6154372500 ps
T1231 /workspace/coverage/default/0.chip_sw_power_idle_load.3794214298 Jun 21 08:00:52 PM PDT 24 Jun 21 08:14:23 PM PDT 24 3874705400 ps
T217 /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.352412280 Jun 21 08:19:51 PM PDT 24 Jun 21 08:41:55 PM PDT 24 7690360360 ps
T1232 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.12105872 Jun 21 08:25:33 PM PDT 24 Jun 21 08:51:02 PM PDT 24 8947133150 ps
T1233 /workspace/coverage/default/2.chip_sw_example_concurrency.1199824655 Jun 21 08:14:40 PM PDT 24 Jun 21 08:19:38 PM PDT 24 2607086672 ps
T337 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.632117324 Jun 21 07:59:09 PM PDT 24 Jun 21 08:10:34 PM PDT 24 5223575374 ps
T1234 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.506927073 Jun 21 08:22:54 PM PDT 24 Jun 21 08:34:52 PM PDT 24 4405801361 ps
T1235 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.2699619254 Jun 21 07:58:49 PM PDT 24 Jun 21 08:06:57 PM PDT 24 7247346856 ps
T1236 /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.703482298 Jun 21 08:15:55 PM PDT 24 Jun 21 08:27:52 PM PDT 24 12227464393 ps
T815 /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.672431097 Jun 21 08:30:20 PM PDT 24 Jun 21 08:37:43 PM PDT 24 3797000654 ps
T1237 /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.940633179 Jun 21 08:21:30 PM PDT 24 Jun 21 08:33:07 PM PDT 24 4806835244 ps
T1238 /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.518243790 Jun 21 08:27:43 PM PDT 24 Jun 21 09:03:57 PM PDT 24 13274124200 ps
T1239 /workspace/coverage/default/0.chip_sw_kmac_app_rom.2832706003 Jun 21 08:00:04 PM PDT 24 Jun 21 08:03:36 PM PDT 24 2548937368 ps
T1240 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.3615422514 Jun 21 08:09:38 PM PDT 24 Jun 21 09:37:13 PM PDT 24 18884497830 ps
T1241 /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.598070619 Jun 21 08:28:45 PM PDT 24 Jun 21 08:37:22 PM PDT 24 3679862234 ps
T1242 /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.910202872 Jun 21 08:18:55 PM PDT 24 Jun 21 08:26:07 PM PDT 24 3170878932 ps
T327 /workspace/coverage/default/0.chip_plic_all_irqs_20.1836227861 Jun 21 07:59:17 PM PDT 24 Jun 21 08:15:04 PM PDT 24 5385400080 ps
T1243 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.2916236293 Jun 21 08:17:31 PM PDT 24 Jun 21 08:38:38 PM PDT 24 7427210228 ps
T344 /workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.2341977882 Jun 21 08:00:56 PM PDT 24 Jun 21 08:07:57 PM PDT 24 3666560176 ps
T1244 /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.2373829868 Jun 21 08:06:38 PM PDT 24 Jun 21 08:14:56 PM PDT 24 5459049576 ps
T1245 /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.3841311077 Jun 21 07:58:36 PM PDT 24 Jun 21 11:55:07 PM PDT 24 79162180720 ps
T1246 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.2043935150 Jun 21 08:01:19 PM PDT 24 Jun 21 08:09:20 PM PDT 24 4322024760 ps
T1247 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.3444730484 Jun 21 08:08:03 PM PDT 24 Jun 21 08:44:56 PM PDT 24 9106702116 ps
T793 /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.250701814 Jun 21 08:27:15 PM PDT 24 Jun 21 08:34:49 PM PDT 24 3856639090 ps
T1248 /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.2931762692 Jun 21 08:25:20 PM PDT 24 Jun 21 08:33:42 PM PDT 24 4495207720 ps
T92 /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.1999306155 Jun 21 08:33:51 PM PDT 24 Jun 21 08:39:55 PM PDT 24 4350111942 ps
T1249 /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.1936279074 Jun 21 07:57:50 PM PDT 24 Jun 21 08:00:24 PM PDT 24 2726526755 ps
T401 /workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.2179043246 Jun 21 08:13:00 PM PDT 24 Jun 21 08:15:43 PM PDT 24 2807232890 ps
T1250 /workspace/coverage/default/0.chip_sw_edn_sw_mode.1345019019 Jun 21 08:03:52 PM PDT 24 Jun 21 08:31:51 PM PDT 24 7832269664 ps
T305 /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.2205376586 Jun 21 07:59:46 PM PDT 24 Jun 21 08:14:53 PM PDT 24 9215302364 ps
T37 /workspace/coverage/default/0.chip_sw_gpio.1490578369 Jun 21 08:00:04 PM PDT 24 Jun 21 08:09:07 PM PDT 24 3905091648 ps
T157 /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.394664167 Jun 21 08:17:58 PM PDT 24 Jun 21 08:19:41 PM PDT 24 2094970587 ps
T1251 /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.343377003 Jun 21 08:32:31 PM PDT 24 Jun 21 08:39:06 PM PDT 24 3663789880 ps
T1252 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.850762337 Jun 21 08:03:37 PM PDT 24 Jun 21 09:05:42 PM PDT 24 39712106202 ps
T1253 /workspace/coverage/default/0.chip_sw_usbdev_vbus.645402254 Jun 21 07:57:14 PM PDT 24 Jun 21 08:00:07 PM PDT 24 2600002660 ps
T50 /workspace/coverage/default/0.chip_sw_spi_device_tpm.65685700 Jun 21 08:01:14 PM PDT 24 Jun 21 08:08:54 PM PDT 24 3050869439 ps
T1254 /workspace/coverage/default/2.rom_volatile_raw_unlock.455332772 Jun 21 08:23:35 PM PDT 24 Jun 21 08:25:20 PM PDT 24 2104036700 ps
T1255 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.3473145150 Jun 21 08:25:04 PM PDT 24 Jun 21 08:37:37 PM PDT 24 3862549762 ps
T1256 /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.1517256392 Jun 21 08:27:36 PM PDT 24 Jun 21 08:42:12 PM PDT 24 13723278902 ps
T733 /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.1124146619 Jun 21 08:30:06 PM PDT 24 Jun 21 08:36:33 PM PDT 24 3355714100 ps
T1257 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.2513085236 Jun 21 08:28:00 PM PDT 24 Jun 21 09:34:54 PM PDT 24 15255855400 ps
T812 /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.565614999 Jun 21 08:30:29 PM PDT 24 Jun 21 08:37:44 PM PDT 24 4015749632 ps
T1258 /workspace/coverage/default/2.chip_sw_example_manufacturer.1549921389 Jun 21 08:14:51 PM PDT 24 Jun 21 08:18:23 PM PDT 24 3221313660 ps
T1259 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.3672285290 Jun 21 08:04:01 PM PDT 24 Jun 21 08:20:01 PM PDT 24 9188529292 ps
T763 /workspace/coverage/default/88.chip_sw_all_escalation_resets.2881860962 Jun 21 08:35:37 PM PDT 24 Jun 21 08:43:28 PM PDT 24 4641166384 ps
T1260 /workspace/coverage/default/1.rom_e2e_asm_init_prod.3587119139 Jun 21 08:22:20 PM PDT 24 Jun 21 09:28:13 PM PDT 24 15750084112 ps
T187 /workspace/coverage/default/2.chip_jtag_mem_access.728409483 Jun 21 08:13:44 PM PDT 24 Jun 21 08:38:59 PM PDT 24 13162814185 ps
T1261 /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.3916930327 Jun 21 08:22:39 PM PDT 24 Jun 21 08:29:40 PM PDT 24 3134915427 ps
T1262 /workspace/coverage/default/2.chip_sw_csrng_smoketest.61200089 Jun 21 08:23:24 PM PDT 24 Jun 21 08:27:00 PM PDT 24 2568766320 ps
T1263 /workspace/coverage/default/1.chip_tap_straps_dev.1520403515 Jun 21 08:11:12 PM PDT 24 Jun 21 08:35:23 PM PDT 24 14155710478 ps
T1264 /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.427878150 Jun 21 08:01:11 PM PDT 24 Jun 21 09:34:03 PM PDT 24 45606380732 ps
T269 /workspace/coverage/default/2.chip_sw_data_integrity_escalation.1012337271 Jun 21 08:14:51 PM PDT 24 Jun 21 08:29:36 PM PDT 24 4659171890 ps
T1265 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.3342867750 Jun 21 08:18:12 PM PDT 24 Jun 21 08:31:49 PM PDT 24 7555145738 ps
T1266 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1340849597 Jun 21 08:12:05 PM PDT 24 Jun 21 08:18:57 PM PDT 24 3346671144 ps
T329 /workspace/coverage/default/0.chip_plic_all_irqs_0.799223853 Jun 21 08:01:40 PM PDT 24 Jun 21 08:22:17 PM PDT 24 6319398184 ps
T1267 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.426792322 Jun 21 08:08:58 PM PDT 24 Jun 21 08:26:21 PM PDT 24 8980179272 ps
T1268 /workspace/coverage/default/2.chip_sw_kmac_smoketest.420353221 Jun 21 08:28:09 PM PDT 24 Jun 21 08:32:17 PM PDT 24 2735299360 ps
T1269 /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.4247329401 Jun 21 08:04:55 PM PDT 24 Jun 21 08:12:09 PM PDT 24 5034497496 ps
T375 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.4266606236 Jun 21 08:06:34 PM PDT 24 Jun 21 08:10:18 PM PDT 24 2843563597 ps
T1270 /workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.610257076 Jun 21 08:26:27 PM PDT 24 Jun 21 10:06:37 PM PDT 24 27019485100 ps
T1271 /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.382272236 Jun 21 07:59:41 PM PDT 24 Jun 21 08:11:10 PM PDT 24 4852240490 ps
T732 /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.3155811418 Jun 21 08:33:31 PM PDT 24 Jun 21 08:40:58 PM PDT 24 4673268704 ps
T1272 /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.3529419157 Jun 21 08:16:02 PM PDT 24 Jun 21 09:40:38 PM PDT 24 46481549632 ps
T740 /workspace/coverage/default/94.chip_sw_all_escalation_resets.3917191967 Jun 21 08:36:30 PM PDT 24 Jun 21 08:48:17 PM PDT 24 5216248504 ps
T1273 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.729373670 Jun 21 08:02:50 PM PDT 24 Jun 21 09:15:44 PM PDT 24 15549168040 ps
T1274 /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3669967880 Jun 21 08:06:04 PM PDT 24 Jun 21 08:14:52 PM PDT 24 18354881408 ps
T1275 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.953947556 Jun 21 08:02:28 PM PDT 24 Jun 21 08:28:46 PM PDT 24 6572386248 ps
T1276 /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.1099878479 Jun 21 08:05:30 PM PDT 24 Jun 21 08:11:53 PM PDT 24 3973639024 ps
T1277 /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1379621784 Jun 21 08:36:17 PM PDT 24 Jun 21 08:43:19 PM PDT 24 3961797928 ps
T1278 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1609737077 Jun 21 08:20:31 PM PDT 24 Jun 21 08:29:39 PM PDT 24 4840045804 ps
T1279 /workspace/coverage/default/1.chip_sw_inject_scramble_seed.116794759 Jun 21 08:04:11 PM PDT 24 Jun 21 11:45:56 PM PDT 24 65505212430 ps
T1280 /workspace/coverage/default/0.chip_sw_gpio_smoketest.1014747366 Jun 21 08:02:37 PM PDT 24 Jun 21 08:06:36 PM PDT 24 3143329981 ps
T131 /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.2627073638 Jun 21 08:10:18 PM PDT 24 Jun 21 08:22:12 PM PDT 24 7595094460 ps
T1281 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.737501904 Jun 21 08:19:06 PM PDT 24 Jun 21 08:23:09 PM PDT 24 2801312119 ps
T767 /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1116938820 Jun 21 08:34:36 PM PDT 24 Jun 21 08:41:39 PM PDT 24 3628520390 ps
T1282 /workspace/coverage/default/44.chip_sw_all_escalation_resets.526876305 Jun 21 08:31:24 PM PDT 24 Jun 21 08:40:20 PM PDT 24 4723175816 ps
T1283 /workspace/coverage/default/1.chip_sw_aon_timer_irq.3263827836 Jun 21 08:07:34 PM PDT 24 Jun 21 08:14:36 PM PDT 24 3589502430 ps
T1284 /workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.510787195 Jun 21 07:57:49 PM PDT 24 Jun 21 08:02:32 PM PDT 24 3009709178 ps
T449 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.1163532380 Jun 21 08:21:21 PM PDT 24 Jun 21 08:47:31 PM PDT 24 25981123716 ps
T298 /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.3261742829 Jun 21 08:21:14 PM PDT 24 Jun 21 08:24:28 PM PDT 24 2534994764 ps
T1285 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.2342855584 Jun 21 08:01:38 PM PDT 24 Jun 21 08:08:58 PM PDT 24 7657034848 ps
T1286 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1321106881 Jun 21 08:21:06 PM PDT 24 Jun 21 08:33:11 PM PDT 24 4045005648 ps
T1287 /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.603265647 Jun 21 08:28:19 PM PDT 24 Jun 21 08:31:51 PM PDT 24 2229628894 ps
T1288 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2491255892 Jun 21 08:19:12 PM PDT 24 Jun 21 08:31:25 PM PDT 24 4579515248 ps
T1289 /workspace/coverage/default/3.chip_sw_uart_tx_rx.2619581822 Jun 21 08:23:50 PM PDT 24 Jun 21 08:36:00 PM PDT 24 4666190020 ps
T1290 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.155313197 Jun 21 07:59:11 PM PDT 24 Jun 21 08:03:32 PM PDT 24 3378393458 ps
T1291 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.1240114152 Jun 21 08:09:34 PM PDT 24 Jun 21 08:47:59 PM PDT 24 12170145910 ps
T1292 /workspace/coverage/default/3.chip_tap_straps_prod.1055545534 Jun 21 08:24:11 PM PDT 24 Jun 21 08:41:59 PM PDT 24 11411743710 ps
T1293 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.1622825972 Jun 21 08:05:56 PM PDT 24 Jun 21 08:12:53 PM PDT 24 6431542537 ps
T1294 /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.3180483360 Jun 21 08:16:01 PM PDT 24 Jun 21 08:27:22 PM PDT 24 3277144440 ps
T1295 /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.2211939743 Jun 21 08:12:25 PM PDT 24 Jun 21 08:46:44 PM PDT 24 18771408479 ps
T458 /workspace/coverage/default/0.chip_jtag_mem_access.3168537464 Jun 21 07:52:06 PM PDT 24 Jun 21 08:15:19 PM PDT 24 13465430601 ps
T379 /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.223513011 Jun 21 08:21:00 PM PDT 24 Jun 21 08:31:06 PM PDT 24 5725651384 ps
T338 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.4152100110 Jun 21 08:16:39 PM PDT 24 Jun 21 08:31:41 PM PDT 24 4703663468 ps
T810 /workspace/coverage/default/8.chip_sw_all_escalation_resets.2951419522 Jun 21 08:27:10 PM PDT 24 Jun 21 08:36:40 PM PDT 24 5689442264 ps
T1296 /workspace/coverage/default/2.chip_sw_kmac_app_rom.4277354233 Jun 21 08:18:54 PM PDT 24 Jun 21 08:23:17 PM PDT 24 2332615384 ps
T47 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1243066521 Jun 21 08:05:30 PM PDT 24 Jun 21 08:15:41 PM PDT 24 5485929858 ps
T1297 /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.1184642851 Jun 21 08:33:26 PM PDT 24 Jun 21 08:39:39 PM PDT 24 3788129848 ps
T313 /workspace/coverage/default/29.chip_sw_all_escalation_resets.1336912225 Jun 21 08:29:56 PM PDT 24 Jun 21 08:40:01 PM PDT 24 5379056568 ps
T1298 /workspace/coverage/default/1.chip_sival_flash_info_access.233172278 Jun 21 08:04:27 PM PDT 24 Jun 21 08:10:32 PM PDT 24 3627557932 ps
T1299 /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.3217757738 Jun 21 08:24:00 PM PDT 24 Jun 21 08:29:38 PM PDT 24 3243533816 ps
T1300 /workspace/coverage/default/2.rom_e2e_asm_init_rma.613467893 Jun 21 08:29:29 PM PDT 24 Jun 21 09:21:35 PM PDT 24 15920740154 ps
T1301 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.3085694618 Jun 21 08:00:02 PM PDT 24 Jun 21 09:10:42 PM PDT 24 15994157130 ps
T1302 /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.2053881051 Jun 21 08:19:45 PM PDT 24 Jun 21 08:55:11 PM PDT 24 11266786584 ps
T1303 /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.4139372414 Jun 21 08:06:20 PM PDT 24 Jun 21 08:16:00 PM PDT 24 6271025192 ps
T1304 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1991608440 Jun 21 08:00:08 PM PDT 24 Jun 21 08:30:53 PM PDT 24 12206872056 ps
T1305 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1676219654 Jun 21 08:16:48 PM PDT 24 Jun 21 08:52:19 PM PDT 24 21836773830 ps
T38 /workspace/coverage/default/1.chip_sw_gpio.84080538 Jun 21 08:03:21 PM PDT 24 Jun 21 08:10:13 PM PDT 24 3102964890 ps
T806 /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.2528759131 Jun 21 08:33:08 PM PDT 24 Jun 21 08:39:07 PM PDT 24 3297676424 ps
T1306 /workspace/coverage/default/0.rom_e2e_asm_init_prod.4049656371 Jun 21 08:06:01 PM PDT 24 Jun 21 09:17:44 PM PDT 24 16481295236 ps
T1307 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1684222333 Jun 21 08:16:06 PM PDT 24 Jun 21 08:27:17 PM PDT 24 4174567552 ps
T822 /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.3114360682 Jun 21 08:30:35 PM PDT 24 Jun 21 08:36:57 PM PDT 24 3371016868 ps
T1308 /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.4239951943 Jun 21 08:04:44 PM PDT 24 Jun 21 08:09:41 PM PDT 24 2851319736 ps
T779 /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.133713240 Jun 21 08:26:34 PM PDT 24 Jun 21 08:33:35 PM PDT 24 3766890376 ps
T363 /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.3701996702 Jun 21 08:20:29 PM PDT 24 Jun 21 08:24:56 PM PDT 24 2593605216 ps
T352 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.3620354953 Jun 21 08:16:36 PM PDT 24 Jun 21 08:30:15 PM PDT 24 5223603984 ps
T1309 /workspace/coverage/default/0.chip_sw_csrng_smoketest.4141072830 Jun 21 08:03:07 PM PDT 24 Jun 21 08:07:23 PM PDT 24 3190130952 ps
T704 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.1835050859 Jun 21 08:18:21 PM PDT 24 Jun 21 08:23:46 PM PDT 24 2957118946 ps
T1310 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.2177894908 Jun 21 08:08:17 PM PDT 24 Jun 21 08:13:20 PM PDT 24 2783470440 ps
T1311 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.659861093 Jun 21 08:11:13 PM PDT 24 Jun 21 08:22:57 PM PDT 24 5259039360 ps
T1312 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.579447575 Jun 21 08:17:08 PM PDT 24 Jun 21 08:25:17 PM PDT 24 5329308841 ps
T1313 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.3739767715 Jun 21 08:01:46 PM PDT 24 Jun 21 09:10:22 PM PDT 24 19058611953 ps
T74 /workspace/coverage/cover_reg_top/45.xbar_access_same_device.1405229406 Jun 21 07:40:59 PM PDT 24 Jun 21 07:42:01 PM PDT 24 1534509251 ps
T75 /workspace/coverage/cover_reg_top/84.xbar_stress_all.3036550850 Jun 21 07:47:46 PM PDT 24 Jun 21 07:51:42 PM PDT 24 2899865858 ps
T76 /workspace/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.564620412 Jun 21 07:46:07 PM PDT 24 Jun 21 07:47:12 PM PDT 24 3591737931 ps
T78 /workspace/coverage/cover_reg_top/27.xbar_access_same_device.843153321 Jun 21 07:36:56 PM PDT 24 Jun 21 07:38:17 PM PDT 24 1911312321 ps
T79 /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.2634188267 Jun 21 07:43:18 PM PDT 24 Jun 21 07:50:58 PM PDT 24 8380998168 ps
T249 /workspace/coverage/cover_reg_top/91.xbar_stress_all.35654394 Jun 21 07:49:05 PM PDT 24 Jun 21 07:54:23 PM PDT 24 3955470337 ps
T892 /workspace/coverage/cover_reg_top/71.xbar_smoke_zero_delays.4200067594 Jun 21 07:45:26 PM PDT 24 Jun 21 07:45:36 PM PDT 24 35332028 ps
T239 /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.349273367 Jun 21 07:44:16 PM PDT 24 Jun 21 07:46:59 PM PDT 24 1033318892 ps
T240 /workspace/coverage/cover_reg_top/21.xbar_random_slow_rsp.2862209025 Jun 21 07:35:19 PM PDT 24 Jun 21 07:51:42 PM PDT 24 57979103470 ps
T474 /workspace/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.1986010025 Jun 21 07:45:34 PM PDT 24 Jun 21 07:45:43 PM PDT 24 43727076 ps
T693 /workspace/coverage/cover_reg_top/15.xbar_smoke_zero_delays.3945496787 Jun 21 07:33:14 PM PDT 24 Jun 21 07:33:22 PM PDT 24 52371701 ps
T559 /workspace/coverage/cover_reg_top/23.xbar_unmapped_addr.1653405485 Jun 21 07:35:51 PM PDT 24 Jun 21 07:36:09 PM PDT 24 121260130 ps
T558 /workspace/coverage/cover_reg_top/40.xbar_access_same_device.95671548 Jun 21 07:40:07 PM PDT 24 Jun 21 07:41:25 PM PDT 24 1978590169 ps
T451 /workspace/coverage/cover_reg_top/86.xbar_stress_all.858594706 Jun 21 07:48:09 PM PDT 24 Jun 21 07:54:26 PM PDT 24 9247898502 ps
T475 /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.1378765821 Jun 21 07:43:34 PM PDT 24 Jun 21 07:56:40 PM PDT 24 15987079221 ps
T1314 /workspace/coverage/cover_reg_top/29.xbar_smoke_zero_delays.1746109109 Jun 21 07:37:23 PM PDT 24 Jun 21 07:37:31 PM PDT 24 52250122 ps
T476 /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_error.2027697156 Jun 21 07:29:54 PM PDT 24 Jun 21 07:33:59 PM PDT 24 3491440682 ps
T675 /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.3604397653 Jun 21 07:43:01 PM PDT 24 Jun 21 07:43:33 PM PDT 24 106338298 ps
T447 /workspace/coverage/cover_reg_top/59.xbar_stress_all.3746507278 Jun 21 07:43:35 PM PDT 24 Jun 21 07:46:08 PM PDT 24 1909420402 ps
T662 /workspace/coverage/cover_reg_top/94.xbar_smoke_zero_delays.955413078 Jun 21 07:49:30 PM PDT 24 Jun 21 07:49:37 PM PDT 24 42603463 ps
T641 /workspace/coverage/cover_reg_top/86.xbar_smoke.575799381 Jun 21 07:48:03 PM PDT 24 Jun 21 07:48:12 PM PDT 24 177044836 ps
T1315 /workspace/coverage/cover_reg_top/5.xbar_smoke.1209210531 Jun 21 07:29:57 PM PDT 24 Jun 21 07:30:09 PM PDT 24 215677650 ps
T877 /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.790906435 Jun 21 07:44:23 PM PDT 24 Jun 21 07:45:59 PM PDT 24 276172852 ps
T532 /workspace/coverage/cover_reg_top/85.xbar_random_zero_delays.2004650731 Jun 21 07:47:53 PM PDT 24 Jun 21 07:48:20 PM PDT 24 316796056 ps
T480 /workspace/coverage/cover_reg_top/36.xbar_stress_all.4119868406 Jun 21 07:39:11 PM PDT 24 Jun 21 07:42:20 PM PDT 24 2224112660 ps
T664 /workspace/coverage/cover_reg_top/59.xbar_smoke_large_delays.978691208 Jun 21 07:43:27 PM PDT 24 Jun 21 07:45:08 PM PDT 24 9438489718 ps
T454 /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.1277587248 Jun 21 07:47:14 PM PDT 24 Jun 21 07:50:13 PM PDT 24 510455063 ps
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