Unified Coverage Report :: Module :: prim_lc_or_hardened

Module : prim_lc_or_hardened

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_lc_or_hardened_0.1/rtl/prim_lc_or_hardened.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.83	99.34	100.00			100.00	100.00	u_pinmux_strap_sampling

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_lc_sync_a	100.00	100.00					100.00
u_prim_lc_sync_b	100.00	100.00					100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_lc_or_hardened

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	60	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_or_hardened_0.1/rtl/prim_lc_or_hardened.sv' or '../src/lowrisc_prim_lc_or_hardened_0.1/rtl/prim_lc_or_hardened.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	4	4
60	1	1

---

Cond Coverage for Module : prim_lc_or_hardened

	Total	Covered	Percent
Conditions	28	28	100.00
Logical	28	28	100.00
Non-Logical	0	0
Event	0	0

 LINE       56
 EXPRESSION ((lc_en_a_copies[0] == ActVal) || (lc_en_b_copies[0] == ActVal))
             --------------1--------------    --------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T5,T6,T17
1	0	Covered	T5,T6,T17

 LINE       56
 SUB-EXPRESSION (lc_en_a_copies[0] == ActVal)
                --------------1--------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T17

 LINE       56
 SUB-EXPRESSION (lc_en_b_copies[0] == ActVal)
                --------------1--------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T17

 LINE       56
 EXPRESSION ((lc_en_a_copies[1] == ActVal) || (lc_en_b_copies[1] == ActVal))
             --------------1--------------    --------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T5,T6,T17
1	0	Covered	T5,T6,T17

 LINE       56
 SUB-EXPRESSION (lc_en_a_copies[1] == ActVal)
                --------------1--------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T17

 LINE       56
 SUB-EXPRESSION (lc_en_b_copies[1] == ActVal)
                --------------1--------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T17

 LINE       56
 EXPRESSION ((lc_en_a_copies[2] == ActVal) || (lc_en_b_copies[2] == ActVal))
             --------------1--------------    --------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T5,T6,T17
1	0	Covered	T5,T6,T17

 LINE       56
 SUB-EXPRESSION (lc_en_a_copies[2] == ActVal)
                --------------1--------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T17

 LINE       56
 SUB-EXPRESSION (lc_en_b_copies[2] == ActVal)
                --------------1--------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T17

 LINE       56
 EXPRESSION ((lc_en_a_copies[3] == ActVal) || (lc_en_b_copies[3] == ActVal))
             --------------1--------------    --------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T5,T6,T17
1	0	Covered	T5,T6,T17

 LINE       56
 SUB-EXPRESSION (lc_en_a_copies[3] == ActVal)
                --------------1--------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T17

 LINE       56
 SUB-EXPRESSION (lc_en_b_copies[3] == ActVal)
                --------------1--------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T17

---

Assert Coverage for Module : prim_lc_or_hardened

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FunctionCheck_A	119157130	118501742	0	0
OutputsKnown_A	119157130	118501742	0	0

FunctionCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119157130	118501742	0	0
T4	14560	13594	0	0
T5	64165	63207	0	0
T6	80534	80211	0	0
T17	56829	56462	0	0
T18	169503	168416	0	0
T32	24693	24336	0	0
T58	122544	121900	0	0
T73	42017	41042	0	0
T75	56897	56451	0	0
T83	19296	18836	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119157130	118501742	0	0
T4	14560	13594	0	0
T5	64165	63207	0	0
T6	80534	80211	0	0
T17	56829	56462	0	0
T18	169503	168416	0	0
T32	24693	24336	0	0
T58	122544	121900	0	0
T73	42017	41042	0	0
T75	56897	56451	0	0
T83	19296	18836	0	0