Unified Coverage Report :: Module :: prim_lc_sync

Module : prim_lc_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en	100.00	100.00					100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en	100.00	100.00					100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en	100.00	100.00					100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en	100.00	100.00					100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a	100.00	100.00					100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b	100.00	100.00					100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync	100.00	100.00					100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.83	99.34	100.00			100.00	100.00	u_pinmux_strap_sampling

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.83	99.34	100.00			100.00	100.00	u_pinmux_strap_sampling

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.83	99.34	100.00			100.00	100.00	u_pinmux_strap_sampling

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.83	99.34	100.00			100.00	100.00	u_pinmux_strap_sampling

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_prim_lc_or_hardened

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_prim_lc_or_hardened

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.83	99.34	100.00			100.00	100.00	u_pinmux_strap_sampling

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.55	92.94	89.29	86.88		100.00	63.64	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.55	92.94	89.29	86.88		100.00	63.64	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=1,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en

SCORE	LINE
100.00	100.00

tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en

SCORE	LINE
100.00	100.00

tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en

SCORE	LINE
100.00	100.00

tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync

SCORE	LINE
100.00	100.00

tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=3,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84		unreachable
85		unreachable
87		unreachable
93	1	1
106	3	3

---

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=4,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a

SCORE	LINE
100.00	100.00

tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84		unreachable
85		unreachable
87		unreachable
93	1	1
106	4	4

---

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=2,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	2	2

---

Assert Coverage for Module : prim_lc_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	8892	8892	0	0
OutputsKnown_A	1786370078	1781574774	0	0
gen_flops.OutputDelay_A	1428898688	1426027678	0	17730
gen_no_flops.OutputDelay_A	357471390	355505226	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8892	8892	0	0
T4	9	9	0	0
T5	9	9	0	0
T6	9	9	0	0
T17	9	9	0	0
T18	9	9	0	0
T32	9	9	0	0
T58	9	9	0	0
T73	9	9	0	0
T75	9	9	0	0
T83	9	9	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1786370078	1781574774	0	0
T4	203042	196046	0	0
T5	969699	962781	0	0
T6	1229056	1226685	0	0
T17	862145	859350	0	0
T18	2587133	2579298	0	0
T32	358853	356244	0	0
T58	1864250	1859392	0	0
T73	618717	611580	0	0
T75	862523	859181	0	0
T83	280436	277092	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1428898688	1426027678	0	17730
T4	159362	155216	0	18
T5	777204	773112	0	18
T6	987454	986028	0	18
T17	691658	689916	0	18
T18	2078624	2074002	0	18
T32	284774	283212	0	18
T58	1496618	1493620	0	18
T73	492666	488398	0	18
T75	691832	689780	0	18
T83	222548	220560	0	18

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357471390	355505226	0	0
T4	43680	40782	0	0
T5	192495	189621	0	0
T6	241602	240633	0	0
T17	170487	169386	0	0
T18	508509	505248	0	0
T32	74079	73008	0	0
T58	367632	365700	0	0
T73	126051	123126	0	0
T75	170691	169353	0	0
T83	57888	56508	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	2	2

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	988	988	0	0
OutputsKnown_A	119157130	118501742	0	0
gen_flops.OutputDelay_A	119157130	118494958	0	2955

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	988	988	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T32	1	1	0	0
T58	1	1	0	0
T73	1	1	0	0
T75	1	1	0	0
T83	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119157130	118501742	0	0
T4	14560	13594	0	0
T5	64165	63207	0	0
T6	80534	80211	0	0
T17	56829	56462	0	0
T18	169503	168416	0	0
T32	24693	24336	0	0
T58	122544	121900	0	0
T73	42017	41042	0	0
T75	56897	56451	0	0
T83	19296	18836	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119157130	118494958	0	2955
T4	14560	13586	0	3
T5	64165	63199	0	3
T6	80534	80207	0	3
T17	56829	56454	0	3
T18	169503	168408	0	3
T32	24693	24332	0	3
T58	122544	121888	0	3
T73	42017	41034	0	3
T75	56897	56443	0	3
T83	19296	18832	0	3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	988	988	0	0
OutputsKnown_A	119157130	118501742	0	0
gen_flops.OutputDelay_A	119157130	118494958	0	2955

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	988	988	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T32	1	1	0	0
T58	1	1	0	0
T73	1	1	0	0
T75	1	1	0	0
T83	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119157130	118501742	0	0
T4	14560	13594	0	0
T5	64165	63207	0	0
T6	80534	80211	0	0
T17	56829	56462	0	0
T18	169503	168416	0	0
T32	24693	24336	0	0
T58	122544	121900	0	0
T73	42017	41042	0	0
T75	56897	56451	0	0
T83	19296	18836	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119157130	118494958	0	2955
T4	14560	13586	0	3
T5	64165	63199	0	3
T6	80534	80207	0	3
T17	56829	56454	0	3
T18	169503	168408	0	3
T32	24693	24332	0	3
T58	122544	121888	0	3
T73	42017	41034	0	3
T75	56897	56443	0	3
T83	19296	18832	0	3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	988	988	0	0
OutputsKnown_A	119157130	118501742	0	0
gen_flops.OutputDelay_A	119157130	118494958	0	2955

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	988	988	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T32	1	1	0	0
T58	1	1	0	0
T73	1	1	0	0
T75	1	1	0	0
T83	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119157130	118501742	0	0
T4	14560	13594	0	0
T5	64165	63207	0	0
T6	80534	80211	0	0
T17	56829	56462	0	0
T18	169503	168416	0	0
T32	24693	24336	0	0
T58	122544	121900	0	0
T73	42017	41042	0	0
T75	56897	56451	0	0
T83	19296	18836	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119157130	118494958	0	2955
T4	14560	13586	0	3
T5	64165	63199	0	3
T6	80534	80207	0	3
T17	56829	56454	0	3
T18	169503	168408	0	3
T32	24693	24332	0	3
T58	122544	121888	0	3
T73	42017	41034	0	3
T75	56897	56443	0	3
T83	19296	18832	0	3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	988	988	0	0
OutputsKnown_A	119157130	118501742	0	0
gen_flops.OutputDelay_A	119157130	118494958	0	2955

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	988	988	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T32	1	1	0	0
T58	1	1	0	0
T73	1	1	0	0
T75	1	1	0	0
T83	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119157130	118501742	0	0
T4	14560	13594	0	0
T5	64165	63207	0	0
T6	80534	80211	0	0
T17	56829	56462	0	0
T18	169503	168416	0	0
T32	24693	24336	0	0
T58	122544	121900	0	0
T73	42017	41042	0	0
T75	56897	56451	0	0
T83	19296	18836	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119157130	118494958	0	2955
T4	14560	13586	0	3
T5	64165	63199	0	3
T6	80534	80207	0	3
T17	56829	56454	0	3
T18	169503	168408	0	3
T32	24693	24332	0	3
T58	122544	121888	0	3
T73	42017	41034	0	3
T75	56897	56443	0	3
T83	19296	18832	0	3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84		unreachable
85		unreachable
87		unreachable
93	1	1
106	4	4

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	988	988	0	0
OutputsKnown_A	119157130	118501742	0	0
gen_no_flops.OutputDelay_A	119157130	118501742	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	988	988	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T32	1	1	0	0
T58	1	1	0	0
T73	1	1	0	0
T75	1	1	0	0
T83	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119157130	118501742	0	0
T4	14560	13594	0	0
T5	64165	63207	0	0
T6	80534	80211	0	0
T17	56829	56462	0	0
T18	169503	168416	0	0
T32	24693	24336	0	0
T58	122544	121900	0	0
T73	42017	41042	0	0
T75	56897	56451	0	0
T83	19296	18836	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119157130	118501742	0	0
T4	14560	13594	0	0
T5	64165	63207	0	0
T6	80534	80211	0	0
T17	56829	56462	0	0
T18	169503	168416	0	0
T32	24693	24336	0	0
T58	122544	121900	0	0
T73	42017	41042	0	0
T75	56897	56451	0	0
T83	19296	18836	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84		unreachable
85		unreachable
87		unreachable
93	1	1
106	4	4

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	988	988	0	0
OutputsKnown_A	119157130	118501742	0	0
gen_no_flops.OutputDelay_A	119157130	118501742	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	988	988	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T32	1	1	0	0
T58	1	1	0	0
T73	1	1	0	0
T75	1	1	0	0
T83	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119157130	118501742	0	0
T4	14560	13594	0	0
T5	64165	63207	0	0
T6	80534	80211	0	0
T17	56829	56462	0	0
T18	169503	168416	0	0
T32	24693	24336	0	0
T58	122544	121900	0	0
T73	42017	41042	0	0
T75	56897	56451	0	0
T83	19296	18836	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119157130	118501742	0	0
T4	14560	13594	0	0
T5	64165	63207	0	0
T6	80534	80211	0	0
T17	56829	56462	0	0
T18	169503	168416	0	0
T32	24693	24336	0	0
T58	122544	121900	0	0
T73	42017	41042	0	0
T75	56897	56451	0	0
T83	19296	18836	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84		unreachable
85		unreachable
87		unreachable
93	1	1
106	3	3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	988	988	0	0
OutputsKnown_A	119157130	118501742	0	0
gen_no_flops.OutputDelay_A	119157130	118501742	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	988	988	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T32	1	1	0	0
T58	1	1	0	0
T73	1	1	0	0
T75	1	1	0	0
T83	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119157130	118501742	0	0
T4	14560	13594	0	0
T5	64165	63207	0	0
T6	80534	80211	0	0
T17	56829	56462	0	0
T18	169503	168416	0	0
T32	24693	24336	0	0
T58	122544	121900	0	0
T73	42017	41042	0	0
T75	56897	56451	0	0
T83	19296	18836	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119157130	118501742	0	0
T4	14560	13594	0	0
T5	64165	63207	0	0
T6	80534	80211	0	0
T17	56829	56462	0	0
T18	169503	168416	0	0
T32	24693	24336	0	0
T58	122544	121900	0	0
T73	42017	41042	0	0
T75	56897	56451	0	0
T83	19296	18836	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	988	988	0	0
OutputsKnown_A	476135084	476031290	0	0
gen_flops.OutputDelay_A	476135084	476023923	0	2955

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	988	988	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T32	1	1	0	0
T58	1	1	0	0
T73	1	1	0	0
T75	1	1	0	0
T83	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	476031290	0	0
T4	50561	50444	0	0
T5	260272	260166	0	0
T6	332659	332604	0	0
T17	232171	232058	0	0
T18	700306	700193	0	0
T32	93001	92946	0	0
T58	503221	503046	0	0
T73	162299	162143	0	0
T75	232122	232012	0	0
T83	72682	72620	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	476023923	0	2955
T4	50561	50436	0	3
T5	260272	260158	0	3
T6	332659	332600	0	3
T17	232171	232050	0	3
T18	700306	700185	0	3
T32	93001	92942	0	3
T58	503221	503034	0	3
T73	162299	162131	0	3
T75	232122	232004	0	3
T83	72682	72616	0	3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	988	988	0	0
OutputsKnown_A	476135084	476031290	0	0
gen_flops.OutputDelay_A	476135084	476023923	0	2955

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	988	988	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T32	1	1	0	0
T58	1	1	0	0
T73	1	1	0	0
T75	1	1	0	0
T83	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	476031290	0	0
T4	50561	50444	0	0
T5	260272	260166	0	0
T6	332659	332604	0	0
T17	232171	232058	0	0
T18	700306	700193	0	0
T32	93001	92946	0	0
T58	503221	503046	0	0
T73	162299	162143	0	0
T75	232122	232012	0	0
T83	72682	72620	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	476023923	0	2955
T4	50561	50436	0	3
T5	260272	260158	0	3
T6	332659	332600	0	3
T17	232171	232050	0	3
T18	700306	700185	0	3
T32	93001	92942	0	3
T58	503221	503034	0	3
T73	162299	162131	0	3
T75	232122	232004	0	3
T83	72682	72616	0	3