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Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.u_dst_update_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 100.00 50.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 100.00 50.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.50 88.00 72.09 73.91 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_nrz_hs_protocol.ack_sync 100.00 100.00 100.00
gen_nrz_hs_protocol.req_sync 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data.u_prim_sync_reqack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.67 100.00 66.67 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.67 100.00 66.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_sync_reqack_data


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_nrz_hs_protocol.ack_sync 100.00 100.00 100.00
gen_nrz_hs_protocol.req_sync 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data.u_prim_sync_reqack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.67 100.00 66.67 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.67 100.00 66.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_sync_reqack_data


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_nrz_hs_protocol.ack_sync 100.00 100.00 100.00
gen_nrz_hs_protocol.req_sync 100.00 100.00 100.00

Go back
Module Instances:
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.u_dst_update_sync
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data.u_prim_sync_reqack
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data.u_prim_sync_reqack
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.u_dst_update_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN5500
CONT_ASSIGN19411100.00
CONT_ASSIGN19511100.00
ALWAYS2191212100.00
ALWAYS2631212100.00
ALWAYS30755100.00
ALWAYS31655100.00
CONT_ASSIGN33500
ALWAYS33900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
55 unreachable
194 1 1
195 1 1
219 1 1
222 1 1
223 1 1
225 1 1
229 1 1
230 1 1
233 1 1
234 1 1
MISSING_ELSE
241 1 1
242 1 1
245 1 1
246 1 1
MISSING_ELSE
263 1 1
266 1 1
267 1 1
269 1 1
273 1 1
274 1 1
277 1 1
278 1 1
MISSING_ELSE
285 1 1
286 1 1
289 1 1
290 1 1
MISSING_ELSE
307 1 1
308 1 1
309 1 1
311 1 1
312 1 1
316 1 1
317 1 1
318 1 1
320 1 1
321 1 1
335 unreachable
339 unreachable
340 unreachable
341 unreachable
342 unreachable
==> MISSING_ELSE


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.u_dst_update_sync
TotalCoveredPercent
Conditions6350.00
Logical6350.00
Non-Logical00
Event00

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.u_dst_update_sync
Line No.TotalCoveredPercent
Branches 12 12 100.00
CASE 225 4 4 100.00
CASE 269 4 4 100.00
IF 307 2 2 100.00
IF 316 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs) -2-: 233 if (gen_nrz_hs_protocol.src_handshake) -3-: 245 if (gen_nrz_hs_protocol.src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T1,T2,T3
ODD - 1 Covered T1,T7,T13
ODD - 0 Covered T1,T2,T3


LineNo. Expression -1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs) -2-: 277 if (gen_nrz_hs_protocol.dst_handshake) -3-: 289 if (gen_nrz_hs_protocol.dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T1,T7,T13
ODD - 1 Covered T1,T7,T13
ODD - 0 Covered T1,T2,T3


LineNo. Expression -1-: 307 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


LineNo. Expression -1-: 316 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.u_dst_update_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 119157130 48 0 0
SyncReqAckHoldReq 1533639 48 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 119157130 48 0 0
T1 43554 3 0 0
T2 0 1 0 0
T3 0 1 0 0
T7 0 6 0 0
T10 0 1 0 0
T11 0 3 0 0
T12 0 11 0 0
T13 0 3 0 0
T16 0 1 0 0
T96 0 3 0 0
T97 275875 0 0 0
T98 169469 0 0 0
T99 83889 0 0 0
T100 47458 0 0 0
T101 49220 0 0 0
T102 43697 0 0 0
T103 54074 0 0 0
T104 72705 0 0 0
T105 38795 0 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 1533639 48 0 0
T1 1302 3 0 0
T2 0 1 0 0
T3 0 1 0 0
T7 0 6 0 0
T10 0 1 0 0
T11 0 3 0 0
T12 0 11 0 0
T13 0 3 0 0
T16 0 1 0 0
T96 0 3 0 0
T97 3504 0 0 0
T98 2195 0 0 0
T99 978 0 0 0
T100 508 0 0 0
T101 602 0 0 0
T102 1363 0 0 0
T103 777 0 0 0
T104 1466 0 0 0
T105 548 0 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data.u_prim_sync_reqack
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN5500
CONT_ASSIGN19411100.00
CONT_ASSIGN19511100.00
ALWAYS2191212100.00
ALWAYS2631212100.00
ALWAYS30755100.00
ALWAYS31655100.00
CONT_ASSIGN33500
ALWAYS33900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
55 unreachable
194 1 1
195 1 1
219 1 1
222 1 1
223 1 1
225 1 1
229 1 1
230 1 1
233 1 1
234 1 1
MISSING_ELSE
241 1 1
242 1 1
245 1 1
246 1 1
MISSING_ELSE
263 1 1
266 1 1
267 1 1
269 1 1
273 1 1
274 1 1
277 1 1
278 1 1
MISSING_ELSE
285 1 1
286 1 1
289 1 1
290 1 1
MISSING_ELSE
307 1 1
308 1 1
309 1 1
311 1 1
312 1 1
316 1 1
317 1 1
318 1 1
320 1 1
321 1 1
335 unreachable
339 unreachable
340 unreachable
341 unreachable
342 unreachable
==> MISSING_ELSE


Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data.u_prim_sync_reqack
TotalCoveredPercent
Conditions6466.67
Logical6466.67
Non-Logical00
Event00

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT232,T233,T146
11CoveredT232,T233,T234

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT232,T233,T146
11CoveredT232,T233,T234

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data.u_prim_sync_reqack
Line No.TotalCoveredPercent
Branches 12 12 100.00
CASE 225 4 4 100.00
CASE 269 4 4 100.00
IF 307 2 2 100.00
IF 316 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs) -2-: 233 if (gen_nrz_hs_protocol.src_handshake) -3-: 245 if (gen_nrz_hs_protocol.src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T232,T233,T234
EVEN 0 - Covered T232,T233,T146
ODD - 1 Covered T232,T233,T234
ODD - 0 Covered T232,T233,T234


LineNo. Expression -1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs) -2-: 277 if (gen_nrz_hs_protocol.dst_handshake) -3-: 289 if (gen_nrz_hs_protocol.dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T232,T233,T234
EVEN 0 - Covered T232,T233,T146
ODD - 1 Covered T232,T233,T234
ODD - 0 Covered T232,T233,T234


LineNo. Expression -1-: 307 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


LineNo. Expression -1-: 316 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data.u_prim_sync_reqack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 117834277 47 0 0
SyncReqAckHoldReq 476135084 47 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 117834277 47 0 0
T27 68069 0 0 0
T63 44293 0 0 0
T69 329062 0 0 0
T135 619586 0 0 0
T139 18209 0 0 0
T141 252677 0 0 0
T224 122419 0 0 0
T232 22604 8 0 0
T233 0 2 0 0
T234 0 8 0 0
T289 71587 0 0 0
T314 0 8 0 0
T315 0 10 0 0
T316 0 11 0 0
T317 18806 0 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 476135084 47 0 0
T27 280441 0 0 0
T63 181388 0 0 0
T69 136941 0 0 0
T135 257986 0 0 0
T139 74292 0 0 0
T141 103713 0 0 0
T224 505312 0 0 0
T232 92599 8 0 0
T233 0 2 0 0
T234 0 8 0 0
T289 296683 0 0 0
T314 0 8 0 0
T315 0 10 0 0
T316 0 11 0 0
T317 76778 0 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data.u_prim_sync_reqack
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN5500
CONT_ASSIGN19411100.00
CONT_ASSIGN19511100.00
ALWAYS2191212100.00
ALWAYS2631212100.00
ALWAYS30755100.00
ALWAYS31655100.00
CONT_ASSIGN33500
ALWAYS33900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
55 unreachable
194 1 1
195 1 1
219 1 1
222 1 1
223 1 1
225 1 1
229 1 1
230 1 1
233 1 1
234 1 1
MISSING_ELSE
241 1 1
242 1 1
245 1 1
246 1 1
MISSING_ELSE
263 1 1
266 1 1
267 1 1
269 1 1
273 1 1
274 1 1
277 1 1
278 1 1
MISSING_ELSE
285 1 1
286 1 1
289 1 1
290 1 1
MISSING_ELSE
307 1 1
308 1 1
309 1 1
311 1 1
312 1 1
316 1 1
317 1 1
318 1 1
320 1 1
321 1 1
335 unreachable
339 unreachable
340 unreachable
341 unreachable
342 unreachable
==> MISSING_ELSE


Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data.u_prim_sync_reqack
TotalCoveredPercent
Conditions6466.67
Logical6466.67
Non-Logical00
Event00

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT4,T5,T6
11CoveredT5,T6,T17

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT4,T5,T6
11CoveredT5,T6,T17

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data.u_prim_sync_reqack
Line No.TotalCoveredPercent
Branches 12 12 100.00
CASE 225 4 4 100.00
CASE 269 4 4 100.00
IF 307 2 2 100.00
IF 316 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs) -2-: 233 if (gen_nrz_hs_protocol.src_handshake) -3-: 245 if (gen_nrz_hs_protocol.src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T5,T6,T17
EVEN 0 - Covered T4,T5,T6
ODD - 1 Covered T6,T17,T32
ODD - 0 Covered T5,T6,T17


LineNo. Expression -1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs) -2-: 277 if (gen_nrz_hs_protocol.dst_handshake) -3-: 289 if (gen_nrz_hs_protocol.dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T5,T6,T17
EVEN 0 - Covered T4,T5,T6
ODD - 1 Covered T6,T17,T32
ODD - 0 Covered T5,T6,T17


LineNo. Expression -1-: 307 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


LineNo. Expression -1-: 316 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data.u_prim_sync_reqack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 476135084 3981 0 0
SyncReqAckHoldReq 476135084 3981 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 476135084 3981 0 0
T5 260272 2 0 0
T6 332659 2 0 0
T17 232171 4 0 0
T18 700306 0 0 0
T32 93001 2 0 0
T58 503221 3 0 0
T73 162299 2 0 0
T75 232122 4 0 0
T83 72682 2 0 0
T144 285046 4 0 0
T292 0 2 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 476135084 3981 0 0
T5 260272 2 0 0
T6 332659 2 0 0
T17 232171 4 0 0
T18 700306 0 0 0
T32 93001 2 0 0
T58 503221 3 0 0
T73 162299 2 0 0
T75 232122 4 0 0
T83 72682 2 0 0
T144 285046 4 0 0
T292 0 2 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%