Unified Coverage Report :: Module :: prim_sync_reqack_data

Module : prim_sync_reqack_data

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data	100.00	100.00					100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	100.00	66.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.55	92.94	89.29	86.88		100.00	63.64	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_sync_reqack	91.67	100.00	66.67			100.00	100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	100.00	66.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	84.62			100.00	100.00	u_edn_if

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_sync_reqack	91.67	100.00	66.67			100.00	100.00

Line Coverage for Module : prim_sync_reqack_data

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	153	0	0
CONT_ASSIGN	156	0	0
ALWAYS	159	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
153		unreachable
156		unreachable
159		unreachable
160		unreachable
162		unreachable

---

Assert Coverage for Module : prim_sync_reqack_data

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	952270168	4028	0	0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	952270168	4028	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA

Name	Attempts	Real Successes	Failures	Incomplete
Total	952270168	4028	0	0
T5	260272	2	0	0
T6	332659	2	0	0
T17	232171	4	0	0
T18	700306	0	0	0
T27	280441	0	0	0
T32	93001	2	0	0
T58	503221	3	0	0
T63	181388	0	0	0
T69	136941	0	0	0
T73	162299	2	0	0
T75	232122	4	0	0
T83	72682	2	0	0
T135	257986	0	0	0
T139	74292	0	0	0
T141	103713	0	0	0
T144	285046	4	0	0
T224	505312	0	0	0
T232	92599	8	0	0
T233	0	2	0	0
T234	0	8	0	0
T289	296683	0	0	0
T292	0	2	0	0
T314	0	8	0	0
T315	0	10	0	0
T316	0	11	0	0
T317	76778	0	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB

Name	Attempts	Real Successes	Failures	Incomplete
Total	952270168	4028	0	0
T5	260272	2	0	0
T6	332659	2	0	0
T17	232171	4	0	0
T18	700306	0	0	0
T27	280441	0	0	0
T32	93001	2	0	0
T58	503221	3	0	0
T63	181388	0	0	0
T69	136941	0	0	0
T73	162299	2	0	0
T75	232122	4	0	0
T83	72682	2	0	0
T135	257986	0	0	0
T139	74292	0	0	0
T141	103713	0	0	0
T144	285046	4	0	0
T224	505312	0	0	0
T232	92599	8	0	0
T233	0	2	0	0
T234	0	8	0	0
T289	296683	0	0	0
T292	0	2	0	0
T314	0	8	0	0
T315	0	10	0	0
T316	0	11	0	0
T317	76778	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	153	0	0
CONT_ASSIGN	156	0	0
ALWAYS	159	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
153		unreachable
156		unreachable
159		unreachable
160		unreachable
162		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	476135084	47	0	0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	476135084	47	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	47	0	0
T27	280441	0	0	0
T63	181388	0	0	0
T69	136941	0	0	0
T135	257986	0	0	0
T139	74292	0	0	0
T141	103713	0	0	0
T224	505312	0	0	0
T232	92599	8	0	0
T233	0	2	0	0
T234	0	8	0	0
T289	296683	0	0	0
T314	0	8	0	0
T315	0	10	0	0
T316	0	11	0	0
T317	76778	0	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	47	0	0
T27	280441	0	0	0
T63	181388	0	0	0
T69	136941	0	0	0
T135	257986	0	0	0
T139	74292	0	0	0
T141	103713	0	0	0
T224	505312	0	0	0
T232	92599	8	0	0
T233	0	2	0	0
T234	0	8	0	0
T289	296683	0	0	0
T314	0	8	0	0
T315	0	10	0	0
T316	0	11	0	0
T317	76778	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	153	0	0
CONT_ASSIGN	156	0	0
ALWAYS	159	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
153		unreachable
156		unreachable
159		unreachable
160		unreachable
162		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	476135084	3981	0	0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	476135084	3981	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	3981	0	0
T5	260272	2	0	0
T6	332659	2	0	0
T17	232171	4	0	0
T18	700306	0	0	0
T32	93001	2	0	0
T58	503221	3	0	0
T73	162299	2	0	0
T75	232122	4	0	0
T83	72682	2	0	0
T144	285046	4	0	0
T292	0	2	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	3981	0	0
T5	260272	2	0	0
T6	332659	2	0	0
T17	232171	4	0	0
T18	700306	0	0	0
T32	93001	2	0	0
T58	503221	3	0	0
T73	162299	2	0	0
T75	232122	4	0	0
T83	72682	2	0	0
T144	285046	4	0	0
T292	0	2	0	0