Unified Coverage Report :: Module :: rv_core_ibex

Module : rv_core_ibex

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.33	92.94	89.29	85.81		100.00	63.64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex	86.55	92.94	89.29	86.88		100.00	63.64

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.55	92.94	89.29	86.88		100.00	63.64

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.41	93.60	74.94	89.62		92.47	91.43

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.59	90.68		87.09			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
fifo_d	100.00	100.00	100.00			100.00	100.00
fifo_i	93.75	75.00	100.00			100.00	100.00
gen_alert_senders[0].u_alert_sender	75.00			75.00
gen_alert_senders[1].u_alert_sender	75.00			75.00
gen_alert_senders[2].u_alert_sender	100.00			100.00
gen_alert_senders[3].u_alert_sender	75.00			75.00
tl_adapter_host_d_ibex	91.79	95.35	81.82			90.00	100.00
tl_adapter_host_i_ibex	87.90	90.48	72.22			88.89	100.00
u_alert_nmi_sync	100.00	100.00				100.00
u_core	95.91			95.91
u_core_sleeping_buf	100.00	100.00
u_dbus_trans	96.36	100.00	92.59			100.00	92.86
u_edn_if	89.08	100.00	86.44			94.87	75.00
u_ibus_trans	96.36	100.00	92.59			100.00	92.86
u_intr_timer_sync	100.00	100.00				100.00
u_lc_sync	100.00	100.00				100.00	100.00
u_prim_buf_irq	100.00	100.00
u_prim_esc_receiver	100.00			100.00
u_prim_lc_sender	100.00	100.00				100.00
u_prim_sync_reqack_data	91.67	100.00	66.67			100.00	100.00
u_pwrmgr_sync	100.00	100.00				100.00	100.00
u_reg_cfg	88.20	91.31	71.55			89.92	100.00
u_sim_win_rsp	89.32	77.27	80.00			100.00	100.00
u_tlul_req_buf	100.00	100.00
u_tlul_rsp_buf	100.00	100.00
u_wdog_nmi_sync	100.00	100.00				100.00

Line Coverage for Module : rv_core_ibex

	Line No.	Total	Covered	Percent
TOTAL		85	79	92.94
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	216	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	348	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
ALWAYS	492	3	3	100.00
CONT_ASSIGN	512	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	514	1	1	100.00
CONT_ASSIGN	515	1	1	100.00
ALWAYS	518	8	8	100.00
CONT_ASSIGN	702	1	1	100.00
CONT_ASSIGN	702	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	708	1	1	100.00
CONT_ASSIGN	708	1	1	100.00
CONT_ASSIGN	709	1	1	100.00
CONT_ASSIGN	709	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	717	1	1	100.00
CONT_ASSIGN	718	1	1	100.00
CONT_ASSIGN	719	1	1	100.00
CONT_ASSIGN	722	1	1	100.00
CONT_ASSIGN	724	1	1	100.00
CONT_ASSIGN	726	1	1	100.00
CONT_ASSIGN	728	1	1	100.00
CONT_ASSIGN	735	1	1	100.00
CONT_ASSIGN	737	1	1	100.00
CONT_ASSIGN	739	1	1	100.00
CONT_ASSIGN	741	1	1	100.00
CONT_ASSIGN	751	1	0	0.00
CONT_ASSIGN	752	1	0	0.00
CONT_ASSIGN	753	1	1	100.00
CONT_ASSIGN	754	1	1	100.00
CONT_ASSIGN	757	1	1	100.00
CONT_ASSIGN	760	1	0	0.00
ALWAYS	792	11	11	100.00
ALWAYS	808	7	7	100.00
CONT_ASSIGN	819	1	1	100.00
CONT_ASSIGN	838	1	1	100.00
CONT_ASSIGN	839	1	1	100.00
CONT_ASSIGN	840	1	1	100.00
CONT_ASSIGN	843	1	0	0.00
CONT_ASSIGN	847	0	0
CONT_ASSIGN	886	1	1	100.00
ALWAYS	945	0	0
CONT_ASSIGN	986	1	0	0.00
CONT_ASSIGN	988	1	0	0.00
CONT_ASSIGN	990	1	1	100.00
CONT_ASSIGN	992	1	1	100.00
CONT_ASSIGN	994	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
202	1	1
203	1	1
216	1	1
217	1	1
218	1	1
225	1	1
263	1	1
265	1	1
268	1	1
342	1	1
348	1	1
363	1	1
492	1	1
493	1	1
495	1	1
512	1	1
513	1	1
514	1	1
515	1	1
518	1	1
519	1	1
520	1	1
521	1	1
522	1	1
523	1	1
524	1	1
525	1	1
			MISSING_ELSE
702	2	2
703	2	2
704	2	2
708	2	2
709	2	2
710	2	2
717	1	1
718	1	1
719	1	1
722	1	1
724	1	1
726	1	1
728	1	1
735	1	1
737	1	1
739	1	1
741	1	1
751	0	1
752	0	1
753	1	1
754	1	1
757	1	1
760	0	1
792	1	1
793	1	1
794	1	1
796	1	1
797	1	1
798	1	1
799	1	1
800	1	1
801	1	1
802	1	1
803	1	1
			MISSING_ELSE
808	1	1
809	1	1
810	1	1
811	1	1
813	1	1
814	1	1
815	1	1
819	1	1
838	1	1
839	1	1
840	1	1
843	0	1
847		unreachable
886	1	1
945		unreachable
946		unreachable
947		unreachable
948		unreachable
			==> MISSING_ELSE
986	0	1
988	0	1
990	1	1
992	1	1
994	1	1

---

Cond Coverage for Module : rv_core_ibex

	Total	Covered	Percent
Conditions	28	25	89.29
Logical	28	25	89.29
Non-Logical	0	0
Event	0	0

 LINE       216
 EXPRESSION (ibus_intg_err | dbus_intg_err | alert_major_bus)
             ------1------   ------2------   -------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T5,T6
0	0	1	Covered	T107,T91,T277
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       217
 EXPRESSION (alert_major_internal | double_fault)
             ----------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T273,T278,T279
1	0	Covered	T5,T150,T136

 LINE       348
 EXPRESSION (fatal_core_err ? Off : local_fetch_enable_q)
             -------1------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T150,T273

 LINE       735
 EXPRESSION (reg2hw.alert_test.fatal_sw_err.q & reg2hw.alert_test.fatal_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T72,T123
1	0	Covered	T5,T6,T17
1	1	Covered	T72,T111,T112

 LINE       737
 EXPRESSION (reg2hw.alert_test.recov_sw_err.q & reg2hw.alert_test.recov_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T72,T111,T112
1	0	Covered	T5,T6,T17
1	1	Covered	T5,T72,T123

 LINE       739
 EXPRESSION (reg2hw.alert_test.fatal_hw_err.q & reg2hw.alert_test.fatal_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T72,T123
1	0	Covered	T5,T6,T17
1	1	Covered	T72,T111,T112

 LINE       741
 EXPRESSION (reg2hw.alert_test.recov_hw_err.q & reg2hw.alert_test.recov_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T72,T123
1	0	Covered	T5,T6,T17
1	1	Covered	T72,T111,T112

 LINE       753
 EXPRESSION (intg_err | fatal_intg_err | fatal_core_err)
             ----1---   -------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T5,T6
0	0	1	Covered	T5,T150,T273
0	1	0	Covered	T107,T91,T277
1	0	0	Covered	T280,T281,T282

 LINE       800
 EXPRESSION (edn_req && edn_ack)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T17
1	1	Covered	T5,T6,T17

---

Toggle Coverage for Module : rv_core_ibex

	Total	Covered	Percent
Totals	123	90	73.17
Total Bits	1628	1397	85.81
Total Bits 0->1	814	699	85.87
Total Bits 1->0	814	698	85.75

Ports	123	90	73.17
Port Bits	1628	1397	85.81
Port Bits 0->1	814	699	85.87
Port Bits 1->0	814	698	85.75

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T5,T17	Yes	T4,T5,T6	INPUT
clk_edn_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_edn_ni	Yes	Yes	T4,T5,T17	Yes	T4,T5,T6	INPUT
clk_esc_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_esc_ni	Yes	Yes	T4,T5,T17	Yes	T4,T5,T6	INPUT
rst_cpu_n_o	Yes	Yes	T4,T5,T17	Yes	T4,T5,T6	OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.rf_cfg.test	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.test	No	No		No		INPUT
hart_id_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
boot_addr_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_o.d_ready	No	No		No		OUTPUT
corei_tl_h_o.a_user.data_intg[6:0]	No	No		No		OUTPUT
corei_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
corei_tl_h_o.a_user.instr_type[3:0]	No	No		No		OUTPUT
corei_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_data[31:0]	No	No		No		OUTPUT
corei_tl_h_o.a_mask[3:0]	No	No		No		OUTPUT
corei_tl_h_o.a_address[1:0]	No	No		No		OUTPUT
corei_tl_h_o.a_address[16:2]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	OUTPUT
corei_tl_h_o.a_address[18:17]	No	No		No		OUTPUT
corei_tl_h_o.a_address[19]	No	No		Yes	T283,T284,T285	OUTPUT
corei_tl_h_o.a_address[27:20]	No	No		No		OUTPUT
corei_tl_h_o.a_address[29:28]	Yes	Yes	T107,*T277,*T146	Yes	T107,T22,T277	OUTPUT
corei_tl_h_o.a_address[31:30]	No	No		No		OUTPUT
corei_tl_h_o.a_source[2:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
corei_tl_h_o.a_source[5:3]	No	No		No		OUTPUT
corei_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_size[1:0]	No	No		No		OUTPUT
corei_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_opcode[2:0]	No	No		No		OUTPUT
corei_tl_h_o.a_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
corei_tl_h_i.a_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
corei_tl_h_i.d_error	Yes	Yes	T17,T75,T106	Yes	T17,T75,T106	INPUT
corei_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
corei_tl_h_i.d_user.rsp_intg[5:0]	Yes	Yes	*T17,*T75,*T107	Yes	T17,T75,T107	INPUT
corei_tl_h_i.d_user.rsp_intg[6]	No	No		No		INPUT
corei_tl_h_i.d_data[31:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
corei_tl_h_i.d_sink	No	No		No		INPUT
corei_tl_h_i.d_source[2:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
corei_tl_h_i.d_source[5:3]	No	No		No		INPUT
corei_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_size[0]	No	No		No		INPUT
corei_tl_h_i.d_size[1]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
corei_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_opcode[0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
corei_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
cored_tl_h_o.d_ready	Yes	Yes	T18,T20,T81	Yes	T18,T20,T81	OUTPUT
cored_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
cored_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
cored_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T20,T108,T109	Yes	T20,T108,T109	OUTPUT
cored_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_data[31:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
cored_tl_h_o.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
cored_tl_h_o.a_address[31:0]	Yes	Yes	T20,T108,T109	Yes	T20,T108,T109	OUTPUT
cored_tl_h_o.a_source[5:0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	OUTPUT
cored_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_size[1:0]	Yes	Yes	T20,T108,T55	Yes	T20,T108,T55	OUTPUT
cored_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_opcode[0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	OUTPUT
cored_tl_h_o.a_opcode[1]	No	No		No		OUTPUT
cored_tl_h_o.a_opcode[2]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
cored_tl_h_o.a_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
cored_tl_h_i.a_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
cored_tl_h_i.d_error	Yes	Yes	T17,T75,T110	Yes	T17,T75,T110	INPUT
cored_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
cored_tl_h_i.d_user.rsp_intg[5:0]	Yes	Yes	*T5,*T6,T17	Yes	T5,T6,T17	INPUT
cored_tl_h_i.d_user.rsp_intg[6]	No	No		No		INPUT
cored_tl_h_i.d_data[31:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
cored_tl_h_i.d_sink	No	No		No		INPUT
cored_tl_h_i.d_source[5:0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
cored_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_size[1:0]	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	INPUT
cored_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_opcode[0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
cored_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
irq_software_i	Yes	Yes	T157,T286,T287	Yes	T157,T286,T287	INPUT
irq_timer_i	Yes	Yes	T119,T124,T288	Yes	T119,T124,T288	INPUT
irq_external_i	Yes	Yes	T6,T17,T32	Yes	T6,T17,T32	INPUT
esc_tx_i.esc_n	Yes	Yes	T5,T17,T75	Yes	T5,T17,T75	INPUT
esc_tx_i.esc_p	Yes	Yes	T5,T17,T75	Yes	T5,T17,T75	INPUT
esc_rx_o.resp_n	Yes	Yes	T5,T17,T75	Yes	T5,T17,T75	OUTPUT
esc_rx_o.resp_p	Yes	Yes	T5,T17,T75	Yes	T5,T17,T75	OUTPUT
nmi_wdog_i	Yes	Yes	T289,T290,T291	Yes	T289,T290,T291	INPUT
debug_req_i	Yes	Yes	T22,T23,T24	Yes	T22,T23,T24	INPUT
crash_dump_o.current.exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.last_data_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.next_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.current_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_valid	Unreachable	Unreachable		Unreachable		OUTPUT
lc_cpu_en_i[3:0]	Yes	Yes	T5,T17,T18	Yes	T5,T6,T17	INPUT
pwrmgr_cpu_en_i[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T6	INPUT
pwrmgr_o.core_sleeping	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
cfg_tl_d_i.a_user.cmd_intg[0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
cfg_tl_d_i.a_user.cmd_intg[1]	No	No		No		INPUT
cfg_tl_d_i.a_user.cmd_intg[6:2]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
cfg_tl_d_i.a_user.instr_type[0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
cfg_tl_d_i.a_user.instr_type[2:1]	No	No		No		INPUT
cfg_tl_d_i.a_user.instr_type[3]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
cfg_tl_d_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_data[31:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
cfg_tl_d_i.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
cfg_tl_d_i.a_address[1:0]	No	No		No		INPUT
cfg_tl_d_i.a_address[7:2]	Yes	Yes	*T5,T6,T17	Yes	T5,T6,T17	INPUT
cfg_tl_d_i.a_address[15:8]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[20:16]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
cfg_tl_d_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[24]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
cfg_tl_d_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[30]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
cfg_tl_d_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_source[0]	No	No		No		INPUT
cfg_tl_d_i.a_source[1]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
cfg_tl_d_i.a_source[5:2]	No	No		No		INPUT
cfg_tl_d_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_size[0]	No	No		No		INPUT
cfg_tl_d_i.a_size[1]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
cfg_tl_d_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_opcode[1:0]	No	No		No		INPUT
cfg_tl_d_i.a_opcode[2]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
cfg_tl_d_i.a_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
cfg_tl_d_o.a_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
cfg_tl_d_o.d_error	No	No		No		OUTPUT
cfg_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T6,T17,T32	Yes	T6,T17,T32	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[1:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
cfg_tl_d_o.d_user.rsp_intg[5:4]	Yes	Yes	T5,T17,T58	Yes	T5,T6,T17	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
cfg_tl_d_o.d_data[31:0]	Yes	Yes	T6,T17,T32	Yes	T6,T17,T32	OUTPUT
cfg_tl_d_o.d_sink	No	No		No		OUTPUT
cfg_tl_d_o.d_source[0]	No	No		No		OUTPUT
cfg_tl_d_o.d_source[1]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	OUTPUT
cfg_tl_d_o.d_source[5:2]	No	No		No		OUTPUT
cfg_tl_d_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_size[0]	No	No		No		OUTPUT
cfg_tl_d_o.d_size[1]	Yes	Yes	T5,T17,T58	Yes	T5,T6,T17	OUTPUT
cfg_tl_d_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_opcode[0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	OUTPUT
cfg_tl_d_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
edn_o.edn_req	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_i.edn_bus[31:0]	Yes	Yes	T75,T144,T107	Yes	T75,T144,T292	INPUT
edn_i.edn_fips	Yes	Yes	T135,T141,T161	Yes	T129,T135,T141	INPUT
edn_i.edn_ack	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
clk_otp_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_otp_ni	Yes	Yes	T4,T5,T17	Yes	T4,T5,T6	INPUT
icache_otp_key_o.req	Yes	Yes	T232,T233,T146	Yes	T232,T233,T146	OUTPUT
icache_otp_key_i.seed_valid	Yes	Yes	T5,T17,T58	Yes	T5,T6,T17	INPUT
icache_otp_key_i.nonce[127:0]	Yes	Yes	T17,T58,T73	Yes	T6,T17,T83	INPUT
icache_otp_key_i.key[127:0]	Yes	Yes	T6,T17,T32	Yes	T17,T58,T73	INPUT
icache_otp_key_i.ack	Yes	Yes	T232,T233,T234	Yes	T232,T233,T234	INPUT
fpga_info_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T72,T30,T111	Yes	T72,T30,T111	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T30,T31,T82	Yes	T30,T31,T82	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T30,T31,T82	Yes	T30,T31,T82	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T5,T72,T293	Yes	T5,T72,T293	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T293,T28,T30	Yes	T28,T30,T31	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T28,T30,T31	Yes	T293,T28,T30	INPUT
alert_rx_i[2].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T107,T72,T273	Yes	T107,T72,T273	INPUT
alert_rx_i[2].ping_n	Yes	Yes	T28,T30,T31	Yes	T28,T30,T31	INPUT
alert_rx_i[2].ping_p	Yes	Yes	T28,T30,T31	Yes	T28,T30,T31	INPUT
alert_rx_i[3].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[3].ack_p	Yes	Yes	T72,T28,T30	Yes	T72,T28,T30	INPUT
alert_rx_i[3].ping_n	Yes	Yes	T28,T30,T31	Yes	T28,T30,T31	INPUT
alert_rx_i[3].ping_p	Yes	Yes	T28,T30,T31	Yes	T28,T30,T31	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T72,T30,T111	Yes	T72,T30,T111	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T5,T72,T293	Yes	T5,T72,T293	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T107,T72,T273	Yes	T107,T72,T273	OUTPUT
alert_tx_o[3].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[3].alert_p	Yes	Yes	T72,T28,T30	Yes	T72,T28,T30	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : rv_core_ibex

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	348	2	2	100.00
IF	492	2	2	100.00
IF	518	3	3	100.00
IF	796	3	3	100.00
IF	808	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	348	(fatal_core_err) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T150,T273
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	492	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	518	if ((!rst_ni))
-2-:	522	if (double_fault)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T273,T278,T279
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	796	if (reg2hw.rnd_data.re)
-2-:	800	if ((edn_req && edn_ack))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T17,T32
0	1	Covered	T5,T6,T17
0	0	Covered	T5,T6,T17

	LineNo.	Expression
-1-:	808	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Module : rv_core_ibex

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	14	63.64
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	14	63.64

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FpvSecCmIbexFetchEnable0_A	476135084	5	0	0
FpvSecCmIbexFetchEnable1_A	476135084	24336258	0	70
FpvSecCmIbexFetchEnable2_A	476135084	64353208	0	58
FpvSecCmIbexFetchEnable3Rev_A	476135084	407289842	0	1970
FpvSecCmIbexFetchEnable3_A	476135084	407291673	0	1885
FpvSecCmIbexInstrIntgErrCheck_A	476135084	0	0	0
FpvSecCmIbexLoadRespIntgErrCheck_A	476135084	592	0	0
FpvSecCmIbexLockstepResetCountAlertCheck_A	476135084	0	0	0
FpvSecCmIbexPcMismatchCheck_A	476135084	0	0	0
FpvSecCmIbexRfEccErrCheck_A	476135084	0	0	0
FpvSecCmIbexStoreRespIntgErrCheck_A	476135084	0	0	0
FpvSecCmRegWeOnehotCheck_A	476135084	5	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A	476135084	0	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A	476135084	0	0	0
FpvSecCmRvCoreRegWeOnehotCheck_A	476135084	0	0	0
g_instr_intg_err_assert_signals.AssertConnected_A	988	988	0	0
g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A	988	988	0	0
g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A	988	988	0	0
g_pc_mismatch_alert_o_assert_signals.AssertConnected_A	988	988	0	0
g_rf_ecc_err_comb_assert_signals.AssertConnected_A	988	988	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A	476135084	194	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A	476135084	197	0	0

FpvSecCmIbexFetchEnable0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	5	0	0
T34	107803	0	0	0
T71	140111	0	0	0
T163	153759	0	0	0
T193	319690	0	0	0
T218	238261	0	0	0
T231	320369	0	0	0
T273	245379	1	0	0
T278	0	1	0	0
T279	0	1	0	0
T290	477570	0	0	0
T294	0	1	0	0
T295	0	1	0	0
T296	154334	0	0	0
T297	347890	0	0	0

FpvSecCmIbexFetchEnable1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	24336258	0	70
T4	50561	50440	0	2
T5	260272	62903	0	0
T6	332659	9923	0	0
T17	232171	41116	0	0
T18	700306	10127	0	2
T20	0	0	0	2
T32	93001	9923	0	0
T58	503221	29773	0	0
T73	162299	29773	0	0
T75	232122	41100	0	0
T81	0	0	0	2
T83	72682	9931	0	0
T215	0	0	0	2
T216	0	0	0	2
T228	0	0	0	2
T298	0	0	0	2
T299	0	0	0	2
T300	0	0	0	2

FpvSecCmIbexFetchEnable2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	64353208	0	58
T4	50561	46820	0	2
T5	260272	69555	0	0
T6	332659	34775	0	0
T17	232171	69555	0	0
T18	700306	34979	0	2
T20	0	0	0	2
T32	93001	34775	0	0
T34	0	0	0	2
T58	503221	104333	0	0
T73	162299	104331	0	0
T75	232122	69555	0	0
T81	0	0	0	2
T83	72682	34775	0	0
T113	0	0	0	2
T116	0	0	0	2
T228	0	0	0	2
T229	0	0	0	2
T301	0	0	0	2

FpvSecCmIbexFetchEnable3Rev_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	407289842	0	1970
T5	260272	147549	0	2
T6	332659	297826	0	2
T17	232171	141240	0	2
T18	700306	665209	0	2
T32	93001	58168	0	2
T58	503221	398704	0	2
T73	162299	57806	0	2
T75	232122	141198	0	2
T83	72682	37842	0	2
T144	285046	179027	0	2

FpvSecCmIbexFetchEnable3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	407291673	0	1885
T5	260272	147551	0	2
T6	332659	297827	0	2
T17	232171	141242	0	2
T18	700306	665210	0	0
T32	93001	58169	0	2
T58	503221	398707	0	2
T73	162299	57806	0	2
T75	232122	141200	0	2
T83	72682	37843	0	2
T144	285046	179031	0	2
T292	0	0	0	2

FpvSecCmIbexInstrIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	0	0	0

FpvSecCmIbexLoadRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	592	0	0
T33	171791	0	0	0
T91	0	32	0	0
T106	226981	0	0	0
T107	286908	1	0	0
T110	260670	0	0	0
T117	249599	0	0	0
T119	190511	0	0	0
T128	98871	0	0	0
T129	396881	0	0	0
T134	78023	0	0	0
T148	0	32	0	0
T261	188385	0	0	0
T277	0	1	0	0
T302	0	100	0	0
T303	0	32	0	0
T304	0	1	0	0
T305	0	31	0	0
T306	0	32	0	0
T307	0	32	0	0

FpvSecCmIbexLockstepResetCountAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	0	0	0

FpvSecCmIbexPcMismatchCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	0	0	0

FpvSecCmIbexRfEccErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	0	0	0

FpvSecCmIbexStoreRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	5	0	0
T124	185720	0	0	0
T130	90406	0	0	0
T149	754155	0	0	0
T174	333379	0	0	0
T225	426250	0	0	0
T280	131243	1	0	0
T281	0	1	0	0
T282	0	1	0	0
T308	0	1	0	0
T309	0	1	0	0
T310	125644	0	0	0
T311	205848	0	0	0
T312	60960	0	0	0
T313	283562	0	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	0	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	0	0	0

FpvSecCmRvCoreRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	0	0	0

g_instr_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	988	988	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T32	1	1	0	0
T58	1	1	0	0
T73	1	1	0	0
T75	1	1	0	0
T83	1	1	0	0

g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	988	988	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T32	1	1	0	0
T58	1	1	0	0
T73	1	1	0	0
T75	1	1	0	0
T83	1	1	0	0

g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	988	988	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T32	1	1	0	0
T58	1	1	0	0
T73	1	1	0	0
T75	1	1	0	0
T83	1	1	0	0

g_pc_mismatch_alert_o_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	988	988	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T32	1	1	0	0
T58	1	1	0	0
T73	1	1	0	0
T75	1	1	0	0
T83	1	1	0	0

g_rf_ecc_err_comb_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	988	988	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T32	1	1	0	0
T58	1	1	0	0
T73	1	1	0	0
T75	1	1	0	0
T83	1	1	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	194	0	0
T27	280441	0	0	0
T63	181388	0	0	0
T69	136941	0	0	0
T135	257986	0	0	0
T139	74292	0	0	0
T141	103713	0	0	0
T224	505312	0	0	0
T232	92599	34	0	0
T233	0	8	0	0
T234	0	33	0	0
T289	296683	0	0	0
T314	0	35	0	0
T315	0	40	0	0
T316	0	44	0	0
T317	76778	0	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	197	0	0
T27	280441	0	0	0
T63	181388	0	0	0
T69	136941	0	0	0
T135	257986	0	0	0
T139	74292	0	0	0
T141	103713	0	0	0
T146	0	16	0	0
T147	0	16	0	0
T224	505312	0	0	0
T232	92599	42	0	0
T233	0	2	0	0
T234	0	42	0	0
T289	296683	0	0	0
T314	0	42	0	0
T315	0	10	0	0
T316	0	11	0	0
T317	76778	0	0	0
T318	0	16	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Line No.	Total	Covered	Percent
TOTAL		85	79	92.94
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	216	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	348	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
ALWAYS	492	3	3	100.00
CONT_ASSIGN	512	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	514	1	1	100.00
CONT_ASSIGN	515	1	1	100.00
ALWAYS	518	8	8	100.00
CONT_ASSIGN	702	1	1	100.00
CONT_ASSIGN	702	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	708	1	1	100.00
CONT_ASSIGN	708	1	1	100.00
CONT_ASSIGN	709	1	1	100.00
CONT_ASSIGN	709	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	717	1	1	100.00
CONT_ASSIGN	718	1	1	100.00
CONT_ASSIGN	719	1	1	100.00
CONT_ASSIGN	722	1	1	100.00
CONT_ASSIGN	724	1	1	100.00
CONT_ASSIGN	726	1	1	100.00
CONT_ASSIGN	728	1	1	100.00
CONT_ASSIGN	735	1	1	100.00
CONT_ASSIGN	737	1	1	100.00
CONT_ASSIGN	739	1	1	100.00
CONT_ASSIGN	741	1	1	100.00
CONT_ASSIGN	751	1	0	0.00
CONT_ASSIGN	752	1	0	0.00
CONT_ASSIGN	753	1	1	100.00
CONT_ASSIGN	754	1	1	100.00
CONT_ASSIGN	757	1	1	100.00
CONT_ASSIGN	760	1	0	0.00
ALWAYS	792	11	11	100.00
ALWAYS	808	7	7	100.00
CONT_ASSIGN	819	1	1	100.00
CONT_ASSIGN	838	1	1	100.00
CONT_ASSIGN	839	1	1	100.00
CONT_ASSIGN	840	1	1	100.00
CONT_ASSIGN	843	1	0	0.00
CONT_ASSIGN	847	0	0
CONT_ASSIGN	886	1	1	100.00
ALWAYS	945	0	0
CONT_ASSIGN	986	1	0	0.00
CONT_ASSIGN	988	1	0	0.00
CONT_ASSIGN	990	1	1	100.00
CONT_ASSIGN	992	1	1	100.00
CONT_ASSIGN	994	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
202	1	1
203	1	1
216	1	1
217	1	1
218	1	1
225	1	1
263	1	1
265	1	1
268	1	1
342	1	1
348	1	1
363	1	1
492	1	1
493	1	1
495	1	1
512	1	1
513	1	1
514	1	1
515	1	1
518	1	1
519	1	1
520	1	1
521	1	1
522	1	1
523	1	1
524	1	1
525	1	1
			MISSING_ELSE
702	2	2
703	2	2
704	2	2
708	2	2
709	2	2
710	2	2
717	1	1
718	1	1
719	1	1
722	1	1
724	1	1
726	1	1
728	1	1
735	1	1
737	1	1
739	1	1
741	1	1
751	0	1
752	0	1
753	1	1
754	1	1
757	1	1
760	0	1
792	1	1
793	1	1
794	1	1
796	1	1
797	1	1
798	1	1
799	1	1
800	1	1
801	1	1
802	1	1
803	1	1
			MISSING_ELSE
808	1	1
809	1	1
810	1	1
811	1	1
813	1	1
814	1	1
815	1	1
819	1	1
838	1	1
839	1	1
840	1	1
843	0	1
847		unreachable
886	1	1
945		unreachable
946		unreachable
947		unreachable
948		unreachable
			==> MISSING_ELSE
986	0	1
988	0	1
990	1	1
992	1	1
994	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Total	Covered	Percent
Conditions	28	25	89.29
Logical	28	25	89.29
Non-Logical	0	0
Event	0	0

 LINE       216
 EXPRESSION (ibus_intg_err | dbus_intg_err | alert_major_bus)
             ------1------   ------2------   -------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T5,T6
0	0	1	Covered	T107,T91,T277
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       217
 EXPRESSION (alert_major_internal | double_fault)
             ----------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T273,T278,T279
1	0	Covered	T5,T150,T136

 LINE       348
 EXPRESSION (fatal_core_err ? Off : local_fetch_enable_q)
             -------1------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T150,T273

 LINE       735
 EXPRESSION (reg2hw.alert_test.fatal_sw_err.q & reg2hw.alert_test.fatal_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T72,T123
1	0	Covered	T5,T6,T17
1	1	Covered	T72,T111,T112

 LINE       737
 EXPRESSION (reg2hw.alert_test.recov_sw_err.q & reg2hw.alert_test.recov_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T72,T111,T112
1	0	Covered	T5,T6,T17
1	1	Covered	T5,T72,T123

 LINE       739
 EXPRESSION (reg2hw.alert_test.fatal_hw_err.q & reg2hw.alert_test.fatal_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T72,T123
1	0	Covered	T5,T6,T17
1	1	Covered	T72,T111,T112

 LINE       741
 EXPRESSION (reg2hw.alert_test.recov_hw_err.q & reg2hw.alert_test.recov_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T72,T123
1	0	Covered	T5,T6,T17
1	1	Covered	T72,T111,T112

 LINE       753
 EXPRESSION (intg_err | fatal_intg_err | fatal_core_err)
             ----1---   -------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T5,T6
0	0	1	Covered	T5,T150,T273
0	1	0	Covered	T107,T91,T277
1	0	0	Covered	T280,T281,T282

 LINE       800
 EXPRESSION (edn_req && edn_ack)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T17
1	1	Covered	T5,T6,T17

---

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Total	Covered	Percent
Totals	119	90	75.63
Total Bits	1608	1397	86.88
Total Bits 0->1	804	699	86.94
Total Bits 1->0	804	698	86.82

Ports	119	90	75.63
Port Bits	1608	1397	86.88
Port Bits 0->1	804	699	86.94
Port Bits 1->0	804	698	86.82

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T5,T17	Yes	T4,T5,T6	INPUT
clk_edn_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_edn_ni	Yes	Yes	T4,T5,T17	Yes	T4,T5,T6	INPUT
clk_esc_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_esc_ni	Yes	Yes	T4,T5,T17	Yes	T4,T5,T6	INPUT
rst_cpu_n_o	Yes	Yes	T4,T5,T17	Yes	T4,T5,T6	OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.rf_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.rf_cfg.test	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.test	No	No		No		INPUT
hart_id_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
boot_addr_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_o.d_ready	No	No		No		OUTPUT
corei_tl_h_o.a_user.data_intg[6:0]	No	No		No		OUTPUT
corei_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
corei_tl_h_o.a_user.instr_type[3:0]	No	No		No		OUTPUT
corei_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_data[31:0]	No	No		No		OUTPUT
corei_tl_h_o.a_mask[3:0]	No	No		No		OUTPUT
corei_tl_h_o.a_address[1:0]	No	No		No		OUTPUT
corei_tl_h_o.a_address[16:2]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	OUTPUT
corei_tl_h_o.a_address[18:17]	No	No		No		OUTPUT
corei_tl_h_o.a_address[19]	No	No		Yes	T283,T284,T285	OUTPUT
corei_tl_h_o.a_address[27:20]	No	No		No		OUTPUT
corei_tl_h_o.a_address[29:28]	Yes	Yes	T107,*T277,*T146	Yes	T107,T22,T277	OUTPUT
corei_tl_h_o.a_address[31:30]	No	No		No		OUTPUT
corei_tl_h_o.a_source[2:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
corei_tl_h_o.a_source[5:3]	No	No		No		OUTPUT
corei_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_size[1:0]	No	No		No		OUTPUT
corei_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_opcode[2:0]	No	No		No		OUTPUT
corei_tl_h_o.a_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
corei_tl_h_i.a_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
corei_tl_h_i.d_error	Yes	Yes	T17,T75,T106	Yes	T17,T75,T106	INPUT
corei_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
corei_tl_h_i.d_user.rsp_intg[5:0]	Yes	Yes	*T17,*T75,*T107	Yes	T17,T75,T107	INPUT
corei_tl_h_i.d_user.rsp_intg[6]	No	No		No		INPUT
corei_tl_h_i.d_data[31:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
corei_tl_h_i.d_sink	No	No		No		INPUT
corei_tl_h_i.d_source[2:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
corei_tl_h_i.d_source[5:3]	No	No		No		INPUT
corei_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_size[0]	No	No		No		INPUT
corei_tl_h_i.d_size[1]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
corei_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_opcode[0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
corei_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
cored_tl_h_o.d_ready	Yes	Yes	T18,T20,T81	Yes	T18,T20,T81	OUTPUT
cored_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
cored_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
cored_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T20,T108,T109	Yes	T20,T108,T109	OUTPUT
cored_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_data[31:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
cored_tl_h_o.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
cored_tl_h_o.a_address[31:0]	Yes	Yes	T20,T108,T109	Yes	T20,T108,T109	OUTPUT
cored_tl_h_o.a_source[5:0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	OUTPUT
cored_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_size[1:0]	Yes	Yes	T20,T108,T55	Yes	T20,T108,T55	OUTPUT
cored_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_opcode[0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	OUTPUT
cored_tl_h_o.a_opcode[1]	No	No		No		OUTPUT
cored_tl_h_o.a_opcode[2]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
cored_tl_h_o.a_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
cored_tl_h_i.a_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
cored_tl_h_i.d_error	Yes	Yes	T17,T75,T110	Yes	T17,T75,T110	INPUT
cored_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
cored_tl_h_i.d_user.rsp_intg[5:0]	Yes	Yes	*T5,*T6,T17	Yes	T5,T6,T17	INPUT
cored_tl_h_i.d_user.rsp_intg[6]	No	No		No		INPUT
cored_tl_h_i.d_data[31:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
cored_tl_h_i.d_sink	No	No		No		INPUT
cored_tl_h_i.d_source[5:0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
cored_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_size[1:0]	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	INPUT
cored_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_opcode[0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
cored_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
irq_software_i	Yes	Yes	T157,T286,T287	Yes	T157,T286,T287	INPUT
irq_timer_i	Yes	Yes	T119,T124,T288	Yes	T119,T124,T288	INPUT
irq_external_i	Yes	Yes	T6,T17,T32	Yes	T6,T17,T32	INPUT
esc_tx_i.esc_n	Yes	Yes	T5,T17,T75	Yes	T5,T17,T75	INPUT
esc_tx_i.esc_p	Yes	Yes	T5,T17,T75	Yes	T5,T17,T75	INPUT
esc_rx_o.resp_n	Yes	Yes	T5,T17,T75	Yes	T5,T17,T75	OUTPUT
esc_rx_o.resp_p	Yes	Yes	T5,T17,T75	Yes	T5,T17,T75	OUTPUT
nmi_wdog_i	Yes	Yes	T289,T290,T291	Yes	T289,T290,T291	INPUT
debug_req_i	Yes	Yes	T22,T23,T24	Yes	T22,T23,T24	INPUT
crash_dump_o.current.exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.last_data_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.next_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.current_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_valid	Unreachable	Unreachable		Unreachable		OUTPUT
lc_cpu_en_i[3:0]	Yes	Yes	T5,T17,T18	Yes	T5,T6,T17	INPUT
pwrmgr_cpu_en_i[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T6	INPUT
pwrmgr_o.core_sleeping	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
cfg_tl_d_i.a_user.cmd_intg[0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
cfg_tl_d_i.a_user.cmd_intg[1]	No	No		No		INPUT
cfg_tl_d_i.a_user.cmd_intg[6:2]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
cfg_tl_d_i.a_user.instr_type[0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
cfg_tl_d_i.a_user.instr_type[2:1]	No	No		No		INPUT
cfg_tl_d_i.a_user.instr_type[3]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
cfg_tl_d_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_data[31:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
cfg_tl_d_i.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
cfg_tl_d_i.a_address[1:0]	No	No		No		INPUT
cfg_tl_d_i.a_address[7:2]	Yes	Yes	*T5,T6,T17	Yes	T5,T6,T17	INPUT
cfg_tl_d_i.a_address[15:8]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[20:16]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
cfg_tl_d_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[24]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
cfg_tl_d_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[30]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
cfg_tl_d_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_source[0]	No	No		No		INPUT
cfg_tl_d_i.a_source[1]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
cfg_tl_d_i.a_source[5:2]	No	No		No		INPUT
cfg_tl_d_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_size[0]	No	No		No		INPUT
cfg_tl_d_i.a_size[1]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
cfg_tl_d_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_opcode[1:0]	No	No		No		INPUT
cfg_tl_d_i.a_opcode[2]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
cfg_tl_d_i.a_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
cfg_tl_d_o.a_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
cfg_tl_d_o.d_error	No	No		No		OUTPUT
cfg_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T6,T17,T32	Yes	T6,T17,T32	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[1:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
cfg_tl_d_o.d_user.rsp_intg[5:4]	Yes	Yes	T5,T17,T58	Yes	T5,T6,T17	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
cfg_tl_d_o.d_data[31:0]	Yes	Yes	T6,T17,T32	Yes	T6,T17,T32	OUTPUT
cfg_tl_d_o.d_sink	No	No		No		OUTPUT
cfg_tl_d_o.d_source[0]	No	No		No		OUTPUT
cfg_tl_d_o.d_source[1]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	OUTPUT
cfg_tl_d_o.d_source[5:2]	No	No		No		OUTPUT
cfg_tl_d_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_size[0]	No	No		No		OUTPUT
cfg_tl_d_o.d_size[1]	Yes	Yes	T5,T17,T58	Yes	T5,T6,T17	OUTPUT
cfg_tl_d_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_opcode[0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	OUTPUT
cfg_tl_d_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
edn_o.edn_req	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_i.edn_bus[31:0]	Yes	Yes	T75,T144,T107	Yes	T75,T144,T292	INPUT
edn_i.edn_fips	Yes	Yes	T135,T141,T161	Yes	T129,T135,T141	INPUT
edn_i.edn_ack	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
clk_otp_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_otp_ni	Yes	Yes	T4,T5,T17	Yes	T4,T5,T6	INPUT
icache_otp_key_o.req	Yes	Yes	T232,T233,T146	Yes	T232,T233,T146	OUTPUT
icache_otp_key_i.seed_valid	Yes	Yes	T5,T17,T58	Yes	T5,T6,T17	INPUT
icache_otp_key_i.nonce[127:0]	Yes	Yes	T17,T58,T73	Yes	T6,T17,T83	INPUT
icache_otp_key_i.key[127:0]	Yes	Yes	T6,T17,T32	Yes	T17,T58,T73	INPUT
icache_otp_key_i.ack	Yes	Yes	T232,T233,T234	Yes	T232,T233,T234	INPUT
fpga_info_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T72,T30,T111	Yes	T72,T30,T111	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T30,T31,T82	Yes	T30,T31,T82	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T30,T31,T82	Yes	T30,T31,T82	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T5,T72,T293	Yes	T5,T72,T293	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T293,T28,T30	Yes	T28,T30,T31	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T28,T30,T31	Yes	T293,T28,T30	INPUT
alert_rx_i[2].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T107,T72,T273	Yes	T107,T72,T273	INPUT
alert_rx_i[2].ping_n	Yes	Yes	T28,T30,T31	Yes	T28,T30,T31	INPUT
alert_rx_i[2].ping_p	Yes	Yes	T28,T30,T31	Yes	T28,T30,T31	INPUT
alert_rx_i[3].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[3].ack_p	Yes	Yes	T72,T28,T30	Yes	T72,T28,T30	INPUT
alert_rx_i[3].ping_n	Yes	Yes	T28,T30,T31	Yes	T28,T30,T31	INPUT
alert_rx_i[3].ping_p	Yes	Yes	T28,T30,T31	Yes	T28,T30,T31	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T72,T30,T111	Yes	T72,T30,T111	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T5,T72,T293	Yes	T5,T72,T293	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T107,T72,T273	Yes	T107,T72,T273	OUTPUT
alert_tx_o[3].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[3].alert_p	Yes	Yes	T72,T28,T30	Yes	T72,T28,T30	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	348	2	2	100.00
IF	492	2	2	100.00
IF	518	3	3	100.00
IF	796	3	3	100.00
IF	808	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	348	(fatal_core_err) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T150,T273
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	492	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	518	if ((!rst_ni))
-2-:	522	if (double_fault)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T273,T278,T279
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	796	if (reg2hw.rnd_data.re)
-2-:	800	if ((edn_req && edn_ack))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T17,T32
0	1	Covered	T5,T6,T17
0	0	Covered	T5,T6,T17

	LineNo.	Expression
-1-:	808	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	14	63.64
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	14	63.64

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FpvSecCmIbexFetchEnable0_A	476135084	5	0	0
FpvSecCmIbexFetchEnable1_A	476135084	24336258	0	70
FpvSecCmIbexFetchEnable2_A	476135084	64353208	0	58
FpvSecCmIbexFetchEnable3Rev_A	476135084	407289842	0	1970
FpvSecCmIbexFetchEnable3_A	476135084	407291673	0	1885
FpvSecCmIbexInstrIntgErrCheck_A	476135084	0	0	0
FpvSecCmIbexLoadRespIntgErrCheck_A	476135084	592	0	0
FpvSecCmIbexLockstepResetCountAlertCheck_A	476135084	0	0	0
FpvSecCmIbexPcMismatchCheck_A	476135084	0	0	0
FpvSecCmIbexRfEccErrCheck_A	476135084	0	0	0
FpvSecCmIbexStoreRespIntgErrCheck_A	476135084	0	0	0
FpvSecCmRegWeOnehotCheck_A	476135084	5	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A	476135084	0	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A	476135084	0	0	0
FpvSecCmRvCoreRegWeOnehotCheck_A	476135084	0	0	0
g_instr_intg_err_assert_signals.AssertConnected_A	988	988	0	0
g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A	988	988	0	0
g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A	988	988	0	0
g_pc_mismatch_alert_o_assert_signals.AssertConnected_A	988	988	0	0
g_rf_ecc_err_comb_assert_signals.AssertConnected_A	988	988	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A	476135084	194	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A	476135084	197	0	0

FpvSecCmIbexFetchEnable0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	5	0	0
T34	107803	0	0	0
T71	140111	0	0	0
T163	153759	0	0	0
T193	319690	0	0	0
T218	238261	0	0	0
T231	320369	0	0	0
T273	245379	1	0	0
T278	0	1	0	0
T279	0	1	0	0
T290	477570	0	0	0
T294	0	1	0	0
T295	0	1	0	0
T296	154334	0	0	0
T297	347890	0	0	0

FpvSecCmIbexFetchEnable1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	24336258	0	70
T4	50561	50440	0	2
T5	260272	62903	0	0
T6	332659	9923	0	0
T17	232171	41116	0	0
T18	700306	10127	0	2
T20	0	0	0	2
T32	93001	9923	0	0
T58	503221	29773	0	0
T73	162299	29773	0	0
T75	232122	41100	0	0
T81	0	0	0	2
T83	72682	9931	0	0
T215	0	0	0	2
T216	0	0	0	2
T228	0	0	0	2
T298	0	0	0	2
T299	0	0	0	2
T300	0	0	0	2

FpvSecCmIbexFetchEnable2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	64353208	0	58
T4	50561	46820	0	2
T5	260272	69555	0	0
T6	332659	34775	0	0
T17	232171	69555	0	0
T18	700306	34979	0	2
T20	0	0	0	2
T32	93001	34775	0	0
T34	0	0	0	2
T58	503221	104333	0	0
T73	162299	104331	0	0
T75	232122	69555	0	0
T81	0	0	0	2
T83	72682	34775	0	0
T113	0	0	0	2
T116	0	0	0	2
T228	0	0	0	2
T229	0	0	0	2
T301	0	0	0	2

FpvSecCmIbexFetchEnable3Rev_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	407289842	0	1970
T5	260272	147549	0	2
T6	332659	297826	0	2
T17	232171	141240	0	2
T18	700306	665209	0	2
T32	93001	58168	0	2
T58	503221	398704	0	2
T73	162299	57806	0	2
T75	232122	141198	0	2
T83	72682	37842	0	2
T144	285046	179027	0	2

FpvSecCmIbexFetchEnable3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	407291673	0	1885
T5	260272	147551	0	2
T6	332659	297827	0	2
T17	232171	141242	0	2
T18	700306	665210	0	0
T32	93001	58169	0	2
T58	503221	398707	0	2
T73	162299	57806	0	2
T75	232122	141200	0	2
T83	72682	37843	0	2
T144	285046	179031	0	2
T292	0	0	0	2

FpvSecCmIbexInstrIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	0	0	0

FpvSecCmIbexLoadRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	592	0	0
T33	171791	0	0	0
T91	0	32	0	0
T106	226981	0	0	0
T107	286908	1	0	0
T110	260670	0	0	0
T117	249599	0	0	0
T119	190511	0	0	0
T128	98871	0	0	0
T129	396881	0	0	0
T134	78023	0	0	0
T148	0	32	0	0
T261	188385	0	0	0
T277	0	1	0	0
T302	0	100	0	0
T303	0	32	0	0
T304	0	1	0	0
T305	0	31	0	0
T306	0	32	0	0
T307	0	32	0	0

FpvSecCmIbexLockstepResetCountAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	0	0	0

FpvSecCmIbexPcMismatchCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	0	0	0

FpvSecCmIbexRfEccErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	0	0	0

FpvSecCmIbexStoreRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	5	0	0
T124	185720	0	0	0
T130	90406	0	0	0
T149	754155	0	0	0
T174	333379	0	0	0
T225	426250	0	0	0
T280	131243	1	0	0
T281	0	1	0	0
T282	0	1	0	0
T308	0	1	0	0
T309	0	1	0	0
T310	125644	0	0	0
T311	205848	0	0	0
T312	60960	0	0	0
T313	283562	0	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	0	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	0	0	0

FpvSecCmRvCoreRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	0	0	0

g_instr_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	988	988	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T32	1	1	0	0
T58	1	1	0	0
T73	1	1	0	0
T75	1	1	0	0
T83	1	1	0	0

g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	988	988	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T32	1	1	0	0
T58	1	1	0	0
T73	1	1	0	0
T75	1	1	0	0
T83	1	1	0	0

g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	988	988	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T32	1	1	0	0
T58	1	1	0	0
T73	1	1	0	0
T75	1	1	0	0
T83	1	1	0	0

g_pc_mismatch_alert_o_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	988	988	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T32	1	1	0	0
T58	1	1	0	0
T73	1	1	0	0
T75	1	1	0	0
T83	1	1	0	0

g_rf_ecc_err_comb_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	988	988	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T32	1	1	0	0
T58	1	1	0	0
T73	1	1	0	0
T75	1	1	0	0
T83	1	1	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	194	0	0
T27	280441	0	0	0
T63	181388	0	0	0
T69	136941	0	0	0
T135	257986	0	0	0
T139	74292	0	0	0
T141	103713	0	0	0
T224	505312	0	0	0
T232	92599	34	0	0
T233	0	8	0	0
T234	0	33	0	0
T289	296683	0	0	0
T314	0	35	0	0
T315	0	40	0	0
T316	0	44	0	0
T317	76778	0	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	197	0	0
T27	280441	0	0	0
T63	181388	0	0	0
T69	136941	0	0	0
T135	257986	0	0	0
T139	74292	0	0	0
T141	103713	0	0	0
T146	0	16	0	0
T147	0	16	0	0
T224	505312	0	0	0
T232	92599	42	0	0
T233	0	2	0	0
T234	0	42	0	0
T289	296683	0	0	0
T314	0	42	0	0
T315	0	10	0	0
T316	0	11	0	0
T317	76778	0	0	0
T318	0	16	0	0