Module Definition
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Module : prim_reg_cdc
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.25 100.00 89.01 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc 44.06 45.45 30.77 50.00 50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc 44.06 45.45 30.77 50.00 50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc 44.06 45.45 30.77 50.00 50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc 44.06 45.45 30.77 50.00 50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc 45.45 45.45 36.36 50.00 50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc 45.45 45.45 36.36 50.00 50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc 45.45 45.45 36.36 50.00 50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc 45.45 45.45 36.36 50.00 50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc 45.45 45.45 36.36 50.00 50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc 45.45 45.45 36.36 50.00 50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc 45.45 45.45 36.36 50.00 50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc 45.45 45.45 36.36 50.00 50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc 45.45 45.45 36.36 50.00 50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc 45.45 45.45 36.36 50.00 50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc 45.45 45.45 36.36 50.00 50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc 95.45 90.91 90.91 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc 95.45 90.91 90.91 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc 95.45 90.91 90.91 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc 96.43 100.00 85.71 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc 98.08 100.00 92.31 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc 98.08 100.00 92.31 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc 98.08 100.00 92.31 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc 98.08 100.00 92.31 100.00 100.00

Line Coverage for Module : prim_reg_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=2,ResetVal=0,BitMask=3,DstWrReq=0,TxnWidth=3 + DataWidth=11,ResetVal=0,BitMask=1793,DstWrReq=1,TxnWidth=3 + DataWidth=4,ResetVal=9,BitMask=15,DstWrReq=1,TxnWidth=3 + DataWidth=20,ResetVal,BitMask=1048575,DstWrReq=0,TxnWidth=3 + DataWidth=18,ResetVal=118010,BitMask=262143,DstWrReq=0,TxnWidth=3 + DataWidth=16,ResetVal,BitMask=65535,DstWrReq=0,TxnWidth=3 + DataWidth=12,ResetVal=0,BitMask=4095,DstWrReq=0,TxnWidth=3 + DataWidth=8,ResetVal,BitMask=255,DstWrReq=0,TxnWidth=3 + DataWidth=14,ResetVal=0,BitMask=16383,DstWrReq=0,TxnWidth=3 + DataWidth=17,ResetVal=2000,BitMask=131071,DstWrReq=0,TxnWidth=3 + DataWidth=7,ResetVal=0,BitMask=119,DstWrReq=0,TxnWidth=3 + DataWidth=5,ResetVal=0,BitMask=31,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal,BitMask,DstWrReq=0,TxnWidth=3 + DataWidth=4,ResetVal=0,BitMask=15,DstWrReq=0,TxnWidth=3 + DataWidth=28,ResetVal=0,BitMask=268374015,DstWrReq=1,TxnWidth=3 + DataWidth=9,ResetVal=0,BitMask=511,DstWrReq=0,TxnWidth=3 + DataWidth=9,ResetVal=0,BitMask=511,DstWrReq=1,TxnWidth=3 + DataWidth=5,ResetVal=0,BitMask=31,DstWrReq=1,TxnWidth=3 + DataWidth=6,ResetVal=0,BitMask=63,DstWrReq=0,TxnWidth=3 + DataWidth=8,ResetVal=0,BitMask=255,DstWrReq=1,TxnWidth=3 + DataWidth=13,ResetVal=0,BitMask=8191,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=1,TxnWidth=3 )
Cond Coverage for Module self-instances :
SCORECOND
45.45 36.36
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

SCORECOND
97.73 90.91
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

SCORECOND
45.45 36.36
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

SCORECOND
45.45 36.36
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

SCORECOND
45.45 36.36
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

SCORECOND
45.45 36.36
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

SCORECOND
45.45 36.36
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

SCORECOND
45.45 36.36
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

SCORECOND
95.45 90.91
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

SCORECOND
95.45 90.91
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

SCORECOND
45.45 36.36
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

SCORECOND
45.45 36.36
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

SCORECOND
97.73 90.91
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

SCORECOND
95.45 90.91
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

SCORECOND
45.45 36.36
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

SCORECOND
45.45 36.36
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

SCORECOND
96.43 85.71
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

TotalCoveredPercent
Conditions141285.71
Logical141285.71
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT4,T5,T6
01Unreachable
10CoveredT8,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT8,T1,T2
11CoveredT8,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT1,T2,T3
10CoveredT8,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT8,T1,T2
11CoveredT8,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT4,T5,T6
10Not Covered
11CoveredT1,T2,T3

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=0,TxnWidth=3 + DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=1,TxnWidth=3 )
Cond Coverage for Module self-instances :
SCORECOND
98.08 92.31
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

SCORECOND
98.08 92.31
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

SCORECOND
44.06 30.77
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

SCORECOND
44.06 30.77
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

SCORECOND
98.08 92.31
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

SCORECOND
98.08 92.31
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

SCORECOND
44.06 30.77
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

SCORECOND
44.06 30.77
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

TotalCoveredPercent
Conditions131292.31
Logical131292.31
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT4,T5,T6
01Unreachable
10CoveredT1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---
-1--2-StatusTests
0-CoveredT1,T2,T3
1-CoveredT1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT4,T5,T6
01Unreachable
10CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT4,T5,T6
10Unreachable
11Unreachable

Branch Coverage for Module : prim_reg_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T6
0 1 - Covered T8,T1,T2
0 0 1 Covered T8,T1,T2
0 0 0 Covered T4,T5,T6


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T6
0 1 - Covered T8,T1,T2
0 0 1 Covered T8,T1,T2
0 0 0 Covered T4,T5,T6


Assert Coverage for Module : prim_reg_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 2147483647 31105 0 0
DstReqKnown_A 38340975 33626875 0 0
SrcAckBusyChk_A 2147483647 76 0 0
SrcBusyKnown_A 2147483647 2147483647 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 31105 0 0
T1 43554 1862 0 0
T2 0 1144 0 0
T3 46606 1150 0 0
T7 0 3787 0 0
T8 0 335 0 0
T9 0 478 0 0
T10 21987 1764 0 0
T11 0 1966 0 0
T12 0 3260 0 0
T13 0 2108 0 0
T14 0 4120 0 0
T15 0 3472 0 0
T16 0 1260 0 0
T19 0 327 0 0
T96 0 1951 0 0
T97 275875 0 0 0
T98 169469 0 0 0
T99 83889 0 0 0
T100 47458 0 0 0
T101 49220 0 0 0
T102 43697 0 0 0
T103 54074 0 0 0
T104 72705 0 0 0
T105 38795 0 0 0
T213 9677 0 0 0
T340 30334 0 0 0
T376 54157 0 0 0
T431 0 2121 0 0
T432 64450 0 0 0
T433 58300 0 0 0
T434 323314 0 0 0
T435 332182 0 0 0
T436 249888 0 0 0
T437 239606 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 38340975 33626875 0 0
T4 10450 4675 0 0
T5 19175 14850 0 0
T6 24575 20275 0 0
T17 21850 17550 0 0
T18 41400 35575 0 0
T32 12325 8025 0 0
T58 35275 30875 0 0
T73 25150 20600 0 0
T75 21125 16800 0 0
T83 9625 5300 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 76 0 0
T1 43554 5 0 0
T2 0 3 0 0
T3 46606 3 0 0
T7 0 10 0 0
T8 0 1 0 0
T9 0 1 0 0
T10 21987 3 0 0
T11 0 4 0 0
T12 0 8 0 0
T13 0 5 0 0
T14 0 10 0 0
T15 0 10 0 0
T16 0 3 0 0
T96 0 5 0 0
T97 275875 0 0 0
T98 169469 0 0 0
T99 83889 0 0 0
T100 47458 0 0 0
T101 49220 0 0 0
T102 43697 0 0 0
T103 54074 0 0 0
T104 72705 0 0 0
T105 38795 0 0 0
T213 9677 0 0 0
T340 30334 0 0 0
T376 54157 0 0 0
T431 0 5 0 0
T432 64450 0 0 0
T433 58300 0 0 0
T434 323314 0 0 0
T435 332182 0 0 0
T436 249888 0 0 0
T437 239606 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T4 364000 339850 0 0
T5 1604125 1580175 0 0
T6 2013350 2005275 0 0
T17 1420725 1411550 0 0
T18 4237575 4210400 0 0
T32 617325 608400 0 0
T58 3063600 3047500 0 0
T73 1050425 1026050 0 0
T75 1422425 1411275 0 0
T83 482400 470900 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%