Unified Coverage Report :: Module :: rv_core_ibex

Module : rv_core_ibex

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.49	96.47	89.29	98.53		100.00	68.18

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex	90.74	96.47	89.29	99.75		100.00	68.18

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.74	96.47	89.29	99.75		100.00	68.18

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.50	97.67	95.75	98.30		98.66	92.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
fifo_d	100.00	100.00	100.00			100.00	100.00
fifo_i	93.75	75.00	100.00			100.00	100.00
gen_alert_senders[0].u_alert_sender	100.00			100.00
gen_alert_senders[1].u_alert_sender	100.00			100.00
gen_alert_senders[2].u_alert_sender	100.00			100.00
gen_alert_senders[3].u_alert_sender	75.00			75.00
tl_adapter_host_d_ibex	92.37	97.67	81.82			90.00	100.00
tl_adapter_host_i_ibex	87.90	90.48	72.22			88.89	100.00
u_alert_nmi_sync	100.00	100.00				100.00
u_core	95.91			95.91
u_core_sleeping_buf	100.00	100.00
u_dbus_trans	96.36	100.00	92.59			100.00	92.86
u_edn_if	89.08	100.00	86.44			94.87	75.00
u_ibus_trans	96.36	100.00	92.59			100.00	92.86
u_intr_timer_sync	100.00	100.00				100.00
u_lc_sync	100.00	100.00				100.00	100.00
u_prim_buf_irq	100.00	100.00
u_prim_esc_receiver	100.00			100.00
u_prim_lc_sender	100.00	100.00				100.00
u_prim_sync_reqack_data	91.67	100.00	66.67			100.00	100.00
u_pwrmgr_sync	100.00	100.00				100.00	100.00
u_reg_cfg	99.20	98.69	98.55			99.58	100.00
u_sim_win_rsp	89.32	77.27	80.00			100.00	100.00
u_tlul_req_buf	100.00	100.00
u_tlul_rsp_buf	100.00	100.00
u_wdog_nmi_sync	100.00	100.00				100.00

Line Coverage for Module : rv_core_ibex

	Line No.	Total	Covered	Percent
TOTAL		85	82	96.47
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	216	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	348	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
ALWAYS	492	3	3	100.00
CONT_ASSIGN	512	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	514	1	1	100.00
CONT_ASSIGN	515	1	1	100.00
ALWAYS	518	8	8	100.00
CONT_ASSIGN	702	1	1	100.00
CONT_ASSIGN	702	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	708	1	1	100.00
CONT_ASSIGN	708	1	1	100.00
CONT_ASSIGN	709	1	1	100.00
CONT_ASSIGN	709	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	717	1	1	100.00
CONT_ASSIGN	718	1	1	100.00
CONT_ASSIGN	719	1	1	100.00
CONT_ASSIGN	722	1	1	100.00
CONT_ASSIGN	724	1	1	100.00
CONT_ASSIGN	726	1	1	100.00
CONT_ASSIGN	728	1	1	100.00
CONT_ASSIGN	735	1	1	100.00
CONT_ASSIGN	737	1	1	100.00
CONT_ASSIGN	739	1	1	100.00
CONT_ASSIGN	741	1	1	100.00
CONT_ASSIGN	751	1	1	100.00
CONT_ASSIGN	752	1	1	100.00
CONT_ASSIGN	753	1	1	100.00
CONT_ASSIGN	754	1	1	100.00
CONT_ASSIGN	757	1	1	100.00
CONT_ASSIGN	760	1	1	100.00
ALWAYS	792	11	11	100.00
ALWAYS	808	7	7	100.00
CONT_ASSIGN	819	1	1	100.00
CONT_ASSIGN	838	1	1	100.00
CONT_ASSIGN	839	1	1	100.00
CONT_ASSIGN	840	1	1	100.00
CONT_ASSIGN	843	1	0	0.00
CONT_ASSIGN	847	0	0
CONT_ASSIGN	886	1	1	100.00
ALWAYS	945	0	0
CONT_ASSIGN	986	1	0	0.00
CONT_ASSIGN	988	1	0	0.00
CONT_ASSIGN	990	1	1	100.00
CONT_ASSIGN	992	1	1	100.00
CONT_ASSIGN	994	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
202	1	1
203	1	1
216	1	1
217	1	1
218	1	1
225	1	1
263	1	1
265	1	1
268	1	1
342	1	1
348	1	1
363	1	1
492	1	1
493	1	1
495	1	1
512	1	1
513	1	1
514	1	1
515	1	1
518	1	1
519	1	1
520	1	1
521	1	1
522	1	1
523	1	1
524	1	1
525	1	1
			MISSING_ELSE
702	2	2
703	2	2
704	2	2
708	2	2
709	2	2
710	2	2
717	1	1
718	1	1
719	1	1
722	1	1
724	1	1
726	1	1
728	1	1
735	1	1
737	1	1
739	1	1
741	1	1
751	1	1
752	1	1
753	1	1
754	1	1
757	1	1
760	1	1
792	1	1
793	1	1
794	1	1
796	1	1
797	1	1
798	1	1
799	1	1
800	1	1
801	1	1
802	1	1
803	1	1
			MISSING_ELSE
808	1	1
809	1	1
810	1	1
811	1	1
813	1	1
814	1	1
815	1	1
819	1	1
838	1	1
839	1	1
840	1	1
843	0	1
847		unreachable
886	1	1
945		unreachable
946		unreachable
947		unreachable
948		unreachable
			==> MISSING_ELSE
986	0	1
988	0	1
990	1	1
992	1	1
994	1	1

---

Cond Coverage for Module : rv_core_ibex

	Total	Covered	Percent
Conditions	28	25	89.29
Logical	28	25	89.29
Non-Logical	0	0
Event	0	0

 LINE       216
 EXPRESSION (ibus_intg_err | dbus_intg_err | alert_major_bus)
             ------1------   ------2------   -------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T5,T6
0	0	1	Covered	T174,T112,T170
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       217
 EXPRESSION (alert_major_internal | double_fault)
             ----------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T218,T237,T238
1	0	Covered	T83,T57,T239

 LINE       348
 EXPRESSION (fatal_core_err ? Off : local_fetch_enable_q)
             -------1------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T83,T57,T239

 LINE       735
 EXPRESSION (reg2hw.alert_test.fatal_sw_err.q & reg2hw.alert_test.fatal_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T57,T186,T59
1	0	Covered	T4,T5,T18
1	1	Covered	T59,T60,T7

 LINE       737
 EXPRESSION (reg2hw.alert_test.recov_sw_err.q & reg2hw.alert_test.recov_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T59,T60,T7
1	0	Covered	T4,T5,T18
1	1	Covered	T57,T186,T59

 LINE       739
 EXPRESSION (reg2hw.alert_test.fatal_hw_err.q & reg2hw.alert_test.fatal_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T57,T186,T59
1	0	Covered	T4,T5,T18
1	1	Covered	T59,T60,T7

 LINE       741
 EXPRESSION (reg2hw.alert_test.recov_hw_err.q & reg2hw.alert_test.recov_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T57,T186,T59
1	0	Covered	T4,T5,T18
1	1	Covered	T59,T60,T7

 LINE       753
 EXPRESSION (intg_err | fatal_intg_err | fatal_core_err)
             ----1---   -------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T5,T6
0	0	1	Covered	T83,T57,T239
0	1	0	Covered	T174,T112,T170
1	0	0	Covered	T240

 LINE       800
 EXPRESSION (edn_req && edn_ack)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T19
1	1	Covered	T4,T5,T18

---

Toggle Coverage for Module : rv_core_ibex

	Total	Covered	Percent
Totals	123	117	95.12
Total Bits	1628	1604	98.53
Total Bits 0->1	814	802	98.53
Total Bits 1->0	814	802	98.53

Ports	123	117	95.12
Port Bits	1628	1604	98.53
Port Bits 0->1	814	802	98.53
Port Bits 1->0	814	802	98.53

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T5,T45	Yes	T4,T5,T6	INPUT
clk_edn_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_edn_ni	Yes	Yes	T4,T5,T45	Yes	T4,T5,T6	INPUT
clk_esc_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_esc_ni	Yes	Yes	T4,T5,T45	Yes	T4,T5,T6	INPUT
rst_cpu_n_o	Yes	Yes	T4,T5,T45	Yes	T4,T5,T6	OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.rf_cfg.test	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.test	No	No		No		INPUT
hart_id_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
boot_addr_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_o.d_ready	Yes	Yes	T70,T72,T77	Yes	T70,T71,T72	OUTPUT
corei_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
corei_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
corei_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	OUTPUT
corei_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_data[31:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
corei_tl_h_o.a_mask[3:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
corei_tl_h_o.a_address[31:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
corei_tl_h_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	OUTPUT
corei_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
corei_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_opcode[2:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
corei_tl_h_o.a_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
corei_tl_h_i.a_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
corei_tl_h_i.d_error	Yes	Yes	T217,T73,T218	Yes	T217,T73,T218	INPUT
corei_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
corei_tl_h_i.d_user.rsp_intg[6:0]	Yes	Yes	T217,T73,T218	Yes	T217,T73,T218	INPUT
corei_tl_h_i.d_data[31:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
corei_tl_h_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
corei_tl_h_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	INPUT
corei_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
corei_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	INPUT
corei_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
cored_tl_h_o.d_ready	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
cored_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
cored_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
cored_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T75,T7,T71	Yes	T75,T7,T71	OUTPUT
cored_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_data[31:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
cored_tl_h_o.a_mask[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
cored_tl_h_o.a_address[31:0]	Yes	Yes	T75,T7,T70	Yes	T75,T7,T70	OUTPUT
cored_tl_h_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	OUTPUT
cored_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_size[1:0]	Yes	Yes	T75,T7,T70	Yes	T75,T7,T70	OUTPUT
cored_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_opcode[2:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
cored_tl_h_o.a_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
cored_tl_h_i.a_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
cored_tl_h_i.d_error	Yes	Yes	T4,T5,T62	Yes	T4,T5,T62	INPUT
cored_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
cored_tl_h_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
cored_tl_h_i.d_data[31:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
cored_tl_h_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
cored_tl_h_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	INPUT
cored_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
cored_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	INPUT
cored_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
irq_software_i	Yes	Yes	T241,T242,T243	Yes	T241,T242,T243	INPUT
irq_timer_i	Yes	Yes	T152,T153,T244	Yes	T152,T153,T244	INPUT
irq_external_i	Yes	Yes	T4,T5,T19	Yes	T4,T5,T19	INPUT
esc_tx_i.esc_n	Yes	Yes	T4,T5,T62	Yes	T4,T5,T62	INPUT
esc_tx_i.esc_p	Yes	Yes	T4,T5,T62	Yes	T4,T5,T62	INPUT
esc_rx_o.resp_n	Yes	Yes	T4,T5,T62	Yes	T4,T5,T62	OUTPUT
esc_rx_o.resp_p	Yes	Yes	T4,T5,T62	Yes	T4,T5,T62	OUTPUT
nmi_wdog_i	Yes	Yes	T4,T62,T245	Yes	T4,T62,T245	INPUT
debug_req_i	Yes	Yes	T73,T246,T247	Yes	T73,T246,T247	INPUT
crash_dump_o.current.exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.last_data_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.next_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.current_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_valid	Unreachable	Unreachable		Unreachable		OUTPUT
lc_cpu_en_i[3:0]	Yes	Yes	T4,T5,T45	Yes	T4,T5,T18	INPUT
pwrmgr_cpu_en_i[3:0]	Yes	Yes	T4,T5,T45	Yes	T4,T5,T6	INPUT
pwrmgr_o.core_sleeping	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.d_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
cfg_tl_d_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
cfg_tl_d_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
cfg_tl_d_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_data[31:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
cfg_tl_d_i.a_mask[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
cfg_tl_d_i.a_address[7:0]	Yes	Yes	*T71,*T72,*T77	Yes	T71,T72,T77	INPUT
cfg_tl_d_i.a_address[15:8]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[20:16]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
cfg_tl_d_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[24]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	INPUT
cfg_tl_d_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[30]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	INPUT
cfg_tl_d_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_source[5:0]	Yes	Yes	*T7,*T71,*T72	Yes	T7,T71,T72	INPUT
cfg_tl_d_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_size[1:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
cfg_tl_d_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_opcode[2:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
cfg_tl_d_i.a_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
cfg_tl_d_o.a_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
cfg_tl_d_o.d_error	Yes	Yes	T7,T70,T71	Yes	T7,T71,T72	OUTPUT
cfg_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T19	Yes	T4,T5,T19	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
cfg_tl_d_o.d_data[31:0]	Yes	Yes	T4,T5,T19	Yes	T4,T5,T19	OUTPUT
cfg_tl_d_o.d_sink	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	OUTPUT
cfg_tl_d_o.d_source[5:0]	Yes	Yes	*T7,*T70,*T71	Yes	T7,T70,T71	OUTPUT
cfg_tl_d_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
cfg_tl_d_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	OUTPUT
cfg_tl_d_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
edn_o.edn_req	Yes	Yes	T4,T5,T18	Yes	T4,T5,T6	OUTPUT
edn_i.edn_bus[31:0]	Yes	Yes	T4,T5,T19	Yes	T4,T5,T19	INPUT
edn_i.edn_fips	Yes	Yes	T248,T249,T250	Yes	T248,T249,T250	INPUT
edn_i.edn_ack	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
clk_otp_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_otp_ni	Yes	Yes	T4,T5,T45	Yes	T4,T5,T6	INPUT
icache_otp_key_o.req	Yes	Yes	T171,T172,T173	Yes	T171,T172,T173	OUTPUT
icache_otp_key_i.seed_valid	Yes	Yes	T4,T5,T45	Yes	T4,T5,T18	INPUT
icache_otp_key_i.nonce[127:0]	Yes	Yes	T5,T19,T45	Yes	T5,T19,T45	INPUT
icache_otp_key_i.key[127:0]	Yes	Yes	T4,T18,T19	Yes	T4,T45,T20	INPUT
icache_otp_key_i.ack	Yes	Yes	T171,T172,T173	Yes	T171,T172,T173	INPUT
fpga_info_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T78,T59,T60	Yes	T78,T59,T60	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T78,T79,T251	Yes	T78,T79,T80	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T78,T79,T80	Yes	T78,T79,T251	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T78,T57,T186	Yes	T78,T57,T186	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
alert_rx_i[2].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T78,T174,T112	Yes	T78,T174,T112	INPUT
alert_rx_i[2].ping_n	Yes	Yes	T78,T79,T156	Yes	T78,T79,T156	INPUT
alert_rx_i[2].ping_p	Yes	Yes	T78,T79,T156	Yes	T78,T79,T156	INPUT
alert_rx_i[3].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[3].ack_p	Yes	Yes	T78,T59,T60	Yes	T78,T59,T60	INPUT
alert_rx_i[3].ping_n	Yes	Yes	T78,T79,T80	Yes	T78,T79,T252	INPUT
alert_rx_i[3].ping_p	Yes	Yes	T78,T79,T252	Yes	T78,T79,T80	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T78,T59,T60	Yes	T78,T59,T60	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T78,T57,T186	Yes	T78,T57,T186	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T78,T174,T112	Yes	T78,T174,T112	OUTPUT
alert_tx_o[3].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[3].alert_p	Yes	Yes	T78,T59,T60	Yes	T78,T59,T60	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : rv_core_ibex

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	348	2	2	100.00
IF	492	2	2	100.00
IF	518	3	3	100.00
IF	796	3	3	100.00
IF	808	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	348	(fatal_core_err) ? 

Branches:

-1-	Status	Tests
1	Covered	T83,T57,T239
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	492	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	518	if ((!rst_ni))
-2-:	522	if (double_fault)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T218,T237,T238
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	796	if (reg2hw.rnd_data.re)
-2-:	800	if ((edn_req && edn_ack))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T19
0	1	Covered	T4,T5,T18
0	0	Covered	T4,T5,T18

	LineNo.	Expression
-1-:	808	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Module : rv_core_ibex

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	15	68.18
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	15	68.18

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FpvSecCmIbexFetchEnable0_A	470871947	8	0	0
FpvSecCmIbexFetchEnable1_A	470871947	24321341	0	66
FpvSecCmIbexFetchEnable2_A	470871947	63992051	0	56
FpvSecCmIbexFetchEnable3Rev_A	470871947	402051164	0	1974
FpvSecCmIbexFetchEnable3_A	470871947	402052972	0	1896
FpvSecCmIbexInstrIntgErrCheck_A	470871947	389	0	0
FpvSecCmIbexLoadRespIntgErrCheck_A	470871947	583	0	0
FpvSecCmIbexLockstepResetCountAlertCheck_A	470871947	0	0	0
FpvSecCmIbexPcMismatchCheck_A	470871947	0	0	0
FpvSecCmIbexRfEccErrCheck_A	470871947	0	0	0
FpvSecCmIbexStoreRespIntgErrCheck_A	470871947	0	0	0
FpvSecCmRegWeOnehotCheck_A	470871947	1	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A	470871947	0	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A	470871947	0	0	0
FpvSecCmRvCoreRegWeOnehotCheck_A	470871947	0	0	0
g_instr_intg_err_assert_signals.AssertConnected_A	991	991	0	0
g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A	991	991	0	0
g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A	991	991	0	0
g_pc_mismatch_alert_o_assert_signals.AssertConnected_A	991	991	0	0
g_rf_ecc_err_comb_assert_signals.AssertConnected_A	991	991	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A	470871947	191	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A	470871947	196	0	0

FpvSecCmIbexFetchEnable0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470871947	8	0	0
T31	199716	0	0	0
T59	93302	0	0	0
T115	52448	0	0	0
T116	39520	0	0	0
T186	228984	0	0	0
T205	571637	0	0	0
T207	305210	0	0	0
T218	276573	1	0	0
T237	0	1	0	0
T238	0	1	0	0
T253	0	1	0	0
T254	0	1	0	0
T255	0	1	0	0
T256	0	1	0	0
T257	0	1	0	0
T258	138278	0	0	0
T259	76614	0	0	0

FpvSecCmIbexFetchEnable1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470871947	24321341	0	66
T4	592568	101040	0	0
T5	239282	40603	0	0
T6	38991	38931	0	2
T18	83411	9919	0	0
T19	99076	9931	0	0
T20	171780	19850	0	0
T21	0	0	0	2
T45	372865	19846	0	0
T62	605119	101023	0	0
T82	276695	41104	0	0
T83	168879	19862	0	0
T115	0	0	0	2
T116	0	0	0	2
T169	0	0	0	2
T260	0	0	0	2
T261	0	0	0	2
T262	0	0	0	2
T263	0	0	0	2
T264	0	0	0	2

FpvSecCmIbexFetchEnable2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470871947	63992051	0	56
T4	592568	177420	0	0
T5	239282	69555	0	0
T6	38991	34775	0	0
T18	83411	34771	0	0
T19	99076	34775	0	0
T20	171780	69550	0	0
T21	0	0	0	2
T23	0	0	0	2
T45	372865	69555	0	0
T62	605119	177428	0	0
T82	276695	69556	0	0
T83	168879	69555	0	0
T115	0	0	0	2
T169	0	0	0	2
T260	0	0	0	2
T262	0	0	0	2
T263	0	0	0	2
T264	0	0	0	2
T265	0	0	0	2
T266	0	0	0	2

FpvSecCmIbexFetchEnable3Rev_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470871947	402051164	0	1974
T4	592568	363447	0	2
T5	239282	148860	0	2
T6	38991	0	0	2
T18	83411	48583	0	2
T19	99076	64240	0	2
T20	171780	102111	0	0
T45	372865	303194	0	2
T58	0	161703	0	2
T62	605119	375992	0	2
T82	276695	185772	0	2
T83	168879	99198	0	2

FpvSecCmIbexFetchEnable3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470871947	402052972	0	1896
T4	592568	363453	0	2
T5	239282	148862	0	2
T6	38991	0	0	0
T18	83411	48583	0	2
T19	99076	64241	0	2
T20	171780	102113	0	0
T45	372865	303196	0	2
T58	0	161703	0	2
T62	605119	375998	0	2
T82	276695	185774	0	2
T83	168879	99200	0	2
T171	0	0	0	2

FpvSecCmIbexInstrIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470871947	389	0	0
T197	750902	0	0	0
T262	72313	0	0	0
T267	265213	78	0	0
T268	0	78	0	0
T269	0	78	0	0
T270	0	77	0	0
T271	0	78	0	0
T272	68244	0	0	0
T273	280835	0	0	0
T274	125248	0	0	0
T275	97574	0	0	0
T276	225335	0	0	0
T277	66345	0	0	0
T278	342904	0	0	0

FpvSecCmIbexLoadRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470871947	583	0	0
T54	131806	0	0	0
T111	75241	0	0	0
T112	0	31	0	0
T113	0	31	0	0
T114	0	31	0	0
T117	569221	0	0	0
T120	311524	0	0	0
T122	425159	0	0	0
T145	227788	0	0	0
T170	0	32	0	0
T174	153420	98	0	0
T209	163739	0	0	0
T279	0	99	0	0
T280	0	1	0	0
T281	0	32	0	0
T282	0	32	0	0
T283	0	100	0	0
T284	88250	0	0	0
T285	377311	0	0	0

FpvSecCmIbexLockstepResetCountAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470871947	0	0	0

FpvSecCmIbexPcMismatchCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470871947	0	0	0

FpvSecCmIbexRfEccErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470871947	0	0	0

FpvSecCmIbexStoreRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470871947	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470871947	1	0	0
T175	397721	0	0	0
T232	158036	0	0	0
T240	156619	1	0	0
T286	161757	0	0	0
T287	111724	0	0	0
T288	359534	0	0	0
T289	198983	0	0	0
T290	148030	0	0	0
T291	271546	0	0	0
T292	93076	0	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470871947	0	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470871947	0	0	0

FpvSecCmRvCoreRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470871947	0	0	0

g_instr_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	991	991	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T45	1	1	0	0
T62	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0

g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	991	991	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T45	1	1	0	0
T62	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0

g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	991	991	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T45	1	1	0	0
T62	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0

g_pc_mismatch_alert_o_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	991	991	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T45	1	1	0	0
T62	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0

g_rf_ecc_err_comb_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	991	991	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T45	1	1	0	0
T62	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470871947	191	0	0
T29	215315	0	0	0
T32	88342	0	0	0
T78	480277	0	0	0
T110	334244	0	0	0
T124	149992	0	0	0
T164	122534	0	0	0
T171	106290	34	0	0
T172	0	38	0	0
T173	0	33	0	0
T187	177412	0	0	0
T293	0	34	0	0
T294	0	16	0	0
T295	0	36	0	0
T296	279292	0	0	0
T297	145080	0	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470871947	196	0	0
T29	215315	0	0	0
T32	88342	0	0	0
T78	480277	0	0	0
T110	334244	0	0	0
T124	149992	0	0	0
T164	122534	0	0	0
T171	106290	42	0	0
T172	0	9	0	0
T173	0	42	0	0
T187	177412	0	0	0
T293	0	42	0	0
T294	0	4	0	0
T295	0	9	0	0
T296	279292	0	0	0
T297	145080	0	0	0
T298	0	16	0	0
T299	0	16	0	0
T300	0	16	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Line No.	Total	Covered	Percent
TOTAL		85	82	96.47
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	216	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	348	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
ALWAYS	492	3	3	100.00
CONT_ASSIGN	512	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	514	1	1	100.00
CONT_ASSIGN	515	1	1	100.00
ALWAYS	518	8	8	100.00
CONT_ASSIGN	702	1	1	100.00
CONT_ASSIGN	702	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	708	1	1	100.00
CONT_ASSIGN	708	1	1	100.00
CONT_ASSIGN	709	1	1	100.00
CONT_ASSIGN	709	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	717	1	1	100.00
CONT_ASSIGN	718	1	1	100.00
CONT_ASSIGN	719	1	1	100.00
CONT_ASSIGN	722	1	1	100.00
CONT_ASSIGN	724	1	1	100.00
CONT_ASSIGN	726	1	1	100.00
CONT_ASSIGN	728	1	1	100.00
CONT_ASSIGN	735	1	1	100.00
CONT_ASSIGN	737	1	1	100.00
CONT_ASSIGN	739	1	1	100.00
CONT_ASSIGN	741	1	1	100.00
CONT_ASSIGN	751	1	1	100.00
CONT_ASSIGN	752	1	1	100.00
CONT_ASSIGN	753	1	1	100.00
CONT_ASSIGN	754	1	1	100.00
CONT_ASSIGN	757	1	1	100.00
CONT_ASSIGN	760	1	1	100.00
ALWAYS	792	11	11	100.00
ALWAYS	808	7	7	100.00
CONT_ASSIGN	819	1	1	100.00
CONT_ASSIGN	838	1	1	100.00
CONT_ASSIGN	839	1	1	100.00
CONT_ASSIGN	840	1	1	100.00
CONT_ASSIGN	843	1	0	0.00
CONT_ASSIGN	847	0	0
CONT_ASSIGN	886	1	1	100.00
ALWAYS	945	0	0
CONT_ASSIGN	986	1	0	0.00
CONT_ASSIGN	988	1	0	0.00
CONT_ASSIGN	990	1	1	100.00
CONT_ASSIGN	992	1	1	100.00
CONT_ASSIGN	994	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
202	1	1
203	1	1
216	1	1
217	1	1
218	1	1
225	1	1
263	1	1
265	1	1
268	1	1
342	1	1
348	1	1
363	1	1
492	1	1
493	1	1
495	1	1
512	1	1
513	1	1
514	1	1
515	1	1
518	1	1
519	1	1
520	1	1
521	1	1
522	1	1
523	1	1
524	1	1
525	1	1
			MISSING_ELSE
702	2	2
703	2	2
704	2	2
708	2	2
709	2	2
710	2	2
717	1	1
718	1	1
719	1	1
722	1	1
724	1	1
726	1	1
728	1	1
735	1	1
737	1	1
739	1	1
741	1	1
751	1	1
752	1	1
753	1	1
754	1	1
757	1	1
760	1	1
792	1	1
793	1	1
794	1	1
796	1	1
797	1	1
798	1	1
799	1	1
800	1	1
801	1	1
802	1	1
803	1	1
			MISSING_ELSE
808	1	1
809	1	1
810	1	1
811	1	1
813	1	1
814	1	1
815	1	1
819	1	1
838	1	1
839	1	1
840	1	1
843	0	1
847		unreachable
886	1	1
945		unreachable
946		unreachable
947		unreachable
948		unreachable
			==> MISSING_ELSE
986	0	1
988	0	1
990	1	1
992	1	1
994	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Total	Covered	Percent
Conditions	28	25	89.29
Logical	28	25	89.29
Non-Logical	0	0
Event	0	0

 LINE       216
 EXPRESSION (ibus_intg_err | dbus_intg_err | alert_major_bus)
             ------1------   ------2------   -------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T5,T6
0	0	1	Covered	T174,T112,T170
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       217
 EXPRESSION (alert_major_internal | double_fault)
             ----------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T218,T237,T238
1	0	Covered	T83,T57,T239

 LINE       348
 EXPRESSION (fatal_core_err ? Off : local_fetch_enable_q)
             -------1------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T83,T57,T239

 LINE       735
 EXPRESSION (reg2hw.alert_test.fatal_sw_err.q & reg2hw.alert_test.fatal_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T57,T186,T59
1	0	Covered	T4,T5,T18
1	1	Covered	T59,T60,T7

 LINE       737
 EXPRESSION (reg2hw.alert_test.recov_sw_err.q & reg2hw.alert_test.recov_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T59,T60,T7
1	0	Covered	T4,T5,T18
1	1	Covered	T57,T186,T59

 LINE       739
 EXPRESSION (reg2hw.alert_test.fatal_hw_err.q & reg2hw.alert_test.fatal_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T57,T186,T59
1	0	Covered	T4,T5,T18
1	1	Covered	T59,T60,T7

 LINE       741
 EXPRESSION (reg2hw.alert_test.recov_hw_err.q & reg2hw.alert_test.recov_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T57,T186,T59
1	0	Covered	T4,T5,T18
1	1	Covered	T59,T60,T7

 LINE       753
 EXPRESSION (intg_err | fatal_intg_err | fatal_core_err)
             ----1---   -------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T5,T6
0	0	1	Covered	T83,T57,T239
0	1	0	Covered	T174,T112,T170
1	0	0	Covered	T240

 LINE       800
 EXPRESSION (edn_req && edn_ack)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T19
1	1	Covered	T4,T5,T18

---

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Total	Covered	Percent
Totals	119	117	98.32
Total Bits	1608	1604	99.75
Total Bits 0->1	804	802	99.75
Total Bits 1->0	804	802	99.75

Ports	119	117	98.32
Port Bits	1608	1604	99.75
Port Bits 0->1	804	802	99.75
Port Bits 1->0	804	802	99.75

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T5,T45	Yes	T4,T5,T6	INPUT
clk_edn_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_edn_ni	Yes	Yes	T4,T5,T45	Yes	T4,T5,T6	INPUT
clk_esc_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_esc_ni	Yes	Yes	T4,T5,T45	Yes	T4,T5,T6	INPUT
rst_cpu_n_o	Yes	Yes	T4,T5,T45	Yes	T4,T5,T6	OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.rf_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.rf_cfg.test	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.test	No	No		No		INPUT
hart_id_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
boot_addr_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_o.d_ready	Yes	Yes	T70,T72,T77	Yes	T70,T71,T72	OUTPUT
corei_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
corei_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
corei_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	OUTPUT
corei_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_data[31:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
corei_tl_h_o.a_mask[3:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
corei_tl_h_o.a_address[31:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
corei_tl_h_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	OUTPUT
corei_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
corei_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_opcode[2:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
corei_tl_h_o.a_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
corei_tl_h_i.a_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
corei_tl_h_i.d_error	Yes	Yes	T217,T73,T218	Yes	T217,T73,T218	INPUT
corei_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
corei_tl_h_i.d_user.rsp_intg[6:0]	Yes	Yes	T217,T73,T218	Yes	T217,T73,T218	INPUT
corei_tl_h_i.d_data[31:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
corei_tl_h_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
corei_tl_h_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	INPUT
corei_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
corei_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	INPUT
corei_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
cored_tl_h_o.d_ready	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
cored_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
cored_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
cored_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T75,T7,T71	Yes	T75,T7,T71	OUTPUT
cored_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_data[31:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
cored_tl_h_o.a_mask[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
cored_tl_h_o.a_address[31:0]	Yes	Yes	T75,T7,T70	Yes	T75,T7,T70	OUTPUT
cored_tl_h_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	OUTPUT
cored_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_size[1:0]	Yes	Yes	T75,T7,T70	Yes	T75,T7,T70	OUTPUT
cored_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_opcode[2:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
cored_tl_h_o.a_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
cored_tl_h_i.a_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
cored_tl_h_i.d_error	Yes	Yes	T4,T5,T62	Yes	T4,T5,T62	INPUT
cored_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
cored_tl_h_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
cored_tl_h_i.d_data[31:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
cored_tl_h_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
cored_tl_h_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	INPUT
cored_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
cored_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	INPUT
cored_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
irq_software_i	Yes	Yes	T241,T242,T243	Yes	T241,T242,T243	INPUT
irq_timer_i	Yes	Yes	T152,T153,T244	Yes	T152,T153,T244	INPUT
irq_external_i	Yes	Yes	T4,T5,T19	Yes	T4,T5,T19	INPUT
esc_tx_i.esc_n	Yes	Yes	T4,T5,T62	Yes	T4,T5,T62	INPUT
esc_tx_i.esc_p	Yes	Yes	T4,T5,T62	Yes	T4,T5,T62	INPUT
esc_rx_o.resp_n	Yes	Yes	T4,T5,T62	Yes	T4,T5,T62	OUTPUT
esc_rx_o.resp_p	Yes	Yes	T4,T5,T62	Yes	T4,T5,T62	OUTPUT
nmi_wdog_i	Yes	Yes	T4,T62,T245	Yes	T4,T62,T245	INPUT
debug_req_i	Yes	Yes	T73,T246,T247	Yes	T73,T246,T247	INPUT
crash_dump_o.current.exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.last_data_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.next_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.current_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_valid	Unreachable	Unreachable		Unreachable		OUTPUT
lc_cpu_en_i[3:0]	Yes	Yes	T4,T5,T45	Yes	T4,T5,T18	INPUT
pwrmgr_cpu_en_i[3:0]	Yes	Yes	T4,T5,T45	Yes	T4,T5,T6	INPUT
pwrmgr_o.core_sleeping	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.d_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
cfg_tl_d_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
cfg_tl_d_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
cfg_tl_d_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_data[31:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
cfg_tl_d_i.a_mask[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
cfg_tl_d_i.a_address[7:0]	Yes	Yes	*T71,*T72,*T77	Yes	T71,T72,T77	INPUT
cfg_tl_d_i.a_address[15:8]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[20:16]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
cfg_tl_d_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[24]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	INPUT
cfg_tl_d_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[30]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	INPUT
cfg_tl_d_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_source[5:0]	Yes	Yes	*T7,*T71,*T72	Yes	T7,T71,T72	INPUT
cfg_tl_d_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_size[1:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
cfg_tl_d_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_opcode[2:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
cfg_tl_d_i.a_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
cfg_tl_d_o.a_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
cfg_tl_d_o.d_error	Yes	Yes	T7,T70,T71	Yes	T7,T71,T72	OUTPUT
cfg_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T19	Yes	T4,T5,T19	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
cfg_tl_d_o.d_data[31:0]	Yes	Yes	T4,T5,T19	Yes	T4,T5,T19	OUTPUT
cfg_tl_d_o.d_sink	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	OUTPUT
cfg_tl_d_o.d_source[5:0]	Yes	Yes	*T7,*T70,*T71	Yes	T7,T70,T71	OUTPUT
cfg_tl_d_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
cfg_tl_d_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	OUTPUT
cfg_tl_d_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
edn_o.edn_req	Yes	Yes	T4,T5,T18	Yes	T4,T5,T6	OUTPUT
edn_i.edn_bus[31:0]	Yes	Yes	T4,T5,T19	Yes	T4,T5,T19	INPUT
edn_i.edn_fips	Yes	Yes	T248,T249,T250	Yes	T248,T249,T250	INPUT
edn_i.edn_ack	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
clk_otp_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_otp_ni	Yes	Yes	T4,T5,T45	Yes	T4,T5,T6	INPUT
icache_otp_key_o.req	Yes	Yes	T171,T172,T173	Yes	T171,T172,T173	OUTPUT
icache_otp_key_i.seed_valid	Yes	Yes	T4,T5,T45	Yes	T4,T5,T18	INPUT
icache_otp_key_i.nonce[127:0]	Yes	Yes	T5,T19,T45	Yes	T5,T19,T45	INPUT
icache_otp_key_i.key[127:0]	Yes	Yes	T4,T18,T19	Yes	T4,T45,T20	INPUT
icache_otp_key_i.ack	Yes	Yes	T171,T172,T173	Yes	T171,T172,T173	INPUT
fpga_info_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T78,T59,T60	Yes	T78,T59,T60	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T78,T79,T251	Yes	T78,T79,T80	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T78,T79,T80	Yes	T78,T79,T251	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T78,T57,T186	Yes	T78,T57,T186	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
alert_rx_i[2].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T78,T174,T112	Yes	T78,T174,T112	INPUT
alert_rx_i[2].ping_n	Yes	Yes	T78,T79,T156	Yes	T78,T79,T156	INPUT
alert_rx_i[2].ping_p	Yes	Yes	T78,T79,T156	Yes	T78,T79,T156	INPUT
alert_rx_i[3].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[3].ack_p	Yes	Yes	T78,T59,T60	Yes	T78,T59,T60	INPUT
alert_rx_i[3].ping_n	Yes	Yes	T78,T79,T80	Yes	T78,T79,T252	INPUT
alert_rx_i[3].ping_p	Yes	Yes	T78,T79,T252	Yes	T78,T79,T80	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T78,T59,T60	Yes	T78,T59,T60	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T78,T57,T186	Yes	T78,T57,T186	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T78,T174,T112	Yes	T78,T174,T112	OUTPUT
alert_tx_o[3].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[3].alert_p	Yes	Yes	T78,T59,T60	Yes	T78,T59,T60	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	348	2	2	100.00
IF	492	2	2	100.00
IF	518	3	3	100.00
IF	796	3	3	100.00
IF	808	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	348	(fatal_core_err) ? 

Branches:

-1-	Status	Tests
1	Covered	T83,T57,T239
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	492	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	518	if ((!rst_ni))
-2-:	522	if (double_fault)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T218,T237,T238
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	796	if (reg2hw.rnd_data.re)
-2-:	800	if ((edn_req && edn_ack))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T19
0	1	Covered	T4,T5,T18
0	0	Covered	T4,T5,T18

	LineNo.	Expression
-1-:	808	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	15	68.18
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	15	68.18

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FpvSecCmIbexFetchEnable0_A	470871947	8	0	0
FpvSecCmIbexFetchEnable1_A	470871947	24321341	0	66
FpvSecCmIbexFetchEnable2_A	470871947	63992051	0	56
FpvSecCmIbexFetchEnable3Rev_A	470871947	402051164	0	1974
FpvSecCmIbexFetchEnable3_A	470871947	402052972	0	1896
FpvSecCmIbexInstrIntgErrCheck_A	470871947	389	0	0
FpvSecCmIbexLoadRespIntgErrCheck_A	470871947	583	0	0
FpvSecCmIbexLockstepResetCountAlertCheck_A	470871947	0	0	0
FpvSecCmIbexPcMismatchCheck_A	470871947	0	0	0
FpvSecCmIbexRfEccErrCheck_A	470871947	0	0	0
FpvSecCmIbexStoreRespIntgErrCheck_A	470871947	0	0	0
FpvSecCmRegWeOnehotCheck_A	470871947	1	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A	470871947	0	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A	470871947	0	0	0
FpvSecCmRvCoreRegWeOnehotCheck_A	470871947	0	0	0
g_instr_intg_err_assert_signals.AssertConnected_A	991	991	0	0
g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A	991	991	0	0
g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A	991	991	0	0
g_pc_mismatch_alert_o_assert_signals.AssertConnected_A	991	991	0	0
g_rf_ecc_err_comb_assert_signals.AssertConnected_A	991	991	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A	470871947	191	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A	470871947	196	0	0

FpvSecCmIbexFetchEnable0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470871947	8	0	0
T31	199716	0	0	0
T59	93302	0	0	0
T115	52448	0	0	0
T116	39520	0	0	0
T186	228984	0	0	0
T205	571637	0	0	0
T207	305210	0	0	0
T218	276573	1	0	0
T237	0	1	0	0
T238	0	1	0	0
T253	0	1	0	0
T254	0	1	0	0
T255	0	1	0	0
T256	0	1	0	0
T257	0	1	0	0
T258	138278	0	0	0
T259	76614	0	0	0

FpvSecCmIbexFetchEnable1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470871947	24321341	0	66
T4	592568	101040	0	0
T5	239282	40603	0	0
T6	38991	38931	0	2
T18	83411	9919	0	0
T19	99076	9931	0	0
T20	171780	19850	0	0
T21	0	0	0	2
T45	372865	19846	0	0
T62	605119	101023	0	0
T82	276695	41104	0	0
T83	168879	19862	0	0
T115	0	0	0	2
T116	0	0	0	2
T169	0	0	0	2
T260	0	0	0	2
T261	0	0	0	2
T262	0	0	0	2
T263	0	0	0	2
T264	0	0	0	2

FpvSecCmIbexFetchEnable2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470871947	63992051	0	56
T4	592568	177420	0	0
T5	239282	69555	0	0
T6	38991	34775	0	0
T18	83411	34771	0	0
T19	99076	34775	0	0
T20	171780	69550	0	0
T21	0	0	0	2
T23	0	0	0	2
T45	372865	69555	0	0
T62	605119	177428	0	0
T82	276695	69556	0	0
T83	168879	69555	0	0
T115	0	0	0	2
T169	0	0	0	2
T260	0	0	0	2
T262	0	0	0	2
T263	0	0	0	2
T264	0	0	0	2
T265	0	0	0	2
T266	0	0	0	2

FpvSecCmIbexFetchEnable3Rev_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470871947	402051164	0	1974
T4	592568	363447	0	2
T5	239282	148860	0	2
T6	38991	0	0	2
T18	83411	48583	0	2
T19	99076	64240	0	2
T20	171780	102111	0	0
T45	372865	303194	0	2
T58	0	161703	0	2
T62	605119	375992	0	2
T82	276695	185772	0	2
T83	168879	99198	0	2

FpvSecCmIbexFetchEnable3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470871947	402052972	0	1896
T4	592568	363453	0	2
T5	239282	148862	0	2
T6	38991	0	0	0
T18	83411	48583	0	2
T19	99076	64241	0	2
T20	171780	102113	0	0
T45	372865	303196	0	2
T58	0	161703	0	2
T62	605119	375998	0	2
T82	276695	185774	0	2
T83	168879	99200	0	2
T171	0	0	0	2

FpvSecCmIbexInstrIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470871947	389	0	0
T197	750902	0	0	0
T262	72313	0	0	0
T267	265213	78	0	0
T268	0	78	0	0
T269	0	78	0	0
T270	0	77	0	0
T271	0	78	0	0
T272	68244	0	0	0
T273	280835	0	0	0
T274	125248	0	0	0
T275	97574	0	0	0
T276	225335	0	0	0
T277	66345	0	0	0
T278	342904	0	0	0

FpvSecCmIbexLoadRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470871947	583	0	0
T54	131806	0	0	0
T111	75241	0	0	0
T112	0	31	0	0
T113	0	31	0	0
T114	0	31	0	0
T117	569221	0	0	0
T120	311524	0	0	0
T122	425159	0	0	0
T145	227788	0	0	0
T170	0	32	0	0
T174	153420	98	0	0
T209	163739	0	0	0
T279	0	99	0	0
T280	0	1	0	0
T281	0	32	0	0
T282	0	32	0	0
T283	0	100	0	0
T284	88250	0	0	0
T285	377311	0	0	0

FpvSecCmIbexLockstepResetCountAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470871947	0	0	0

FpvSecCmIbexPcMismatchCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470871947	0	0	0

FpvSecCmIbexRfEccErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470871947	0	0	0

FpvSecCmIbexStoreRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470871947	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470871947	1	0	0
T175	397721	0	0	0
T232	158036	0	0	0
T240	156619	1	0	0
T286	161757	0	0	0
T287	111724	0	0	0
T288	359534	0	0	0
T289	198983	0	0	0
T290	148030	0	0	0
T291	271546	0	0	0
T292	93076	0	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470871947	0	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470871947	0	0	0

FpvSecCmRvCoreRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470871947	0	0	0

g_instr_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	991	991	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T45	1	1	0	0
T62	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0

g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	991	991	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T45	1	1	0	0
T62	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0

g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	991	991	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T45	1	1	0	0
T62	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0

g_pc_mismatch_alert_o_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	991	991	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T45	1	1	0	0
T62	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0

g_rf_ecc_err_comb_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	991	991	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T45	1	1	0	0
T62	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470871947	191	0	0
T29	215315	0	0	0
T32	88342	0	0	0
T78	480277	0	0	0
T110	334244	0	0	0
T124	149992	0	0	0
T164	122534	0	0	0
T171	106290	34	0	0
T172	0	38	0	0
T173	0	33	0	0
T187	177412	0	0	0
T293	0	34	0	0
T294	0	16	0	0
T295	0	36	0	0
T296	279292	0	0	0
T297	145080	0	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470871947	196	0	0
T29	215315	0	0	0
T32	88342	0	0	0
T78	480277	0	0	0
T110	334244	0	0	0
T124	149992	0	0	0
T164	122534	0	0	0
T171	106290	42	0	0
T172	0	9	0	0
T173	0	42	0	0
T187	177412	0	0	0
T293	0	42	0	0
T294	0	4	0	0
T295	0	9	0	0
T296	279292	0	0	0
T297	145080	0	0	0
T298	0	16	0	0
T299	0	16	0	0
T300	0	16	0	0