Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_packer_fifo
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
ALWAYS | 82 | 7 | 7 | 100.00 |
CONT_ASSIGN | 94 | 0 | 0 | |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 127 | 3 | 3 | 100.00 |
CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
CONT_ASSIGN | 142 | 1 | 1 | 100.00 |
CONT_ASSIGN | 147 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
82 |
1 |
1 |
83 |
1 |
1 |
84 |
1 |
1 |
85 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
89 |
1 |
1 |
94 |
|
unreachable |
96 |
1 |
1 |
127 |
1 |
1 |
128 |
1 |
1 |
130 |
1 |
1 |
136 |
1 |
1 |
137 |
1 |
1 |
138 |
1 |
1 |
139 |
1 |
1 |
140 |
1 |
1 |
142 |
1 |
1 |
147 |
1 |
1 |
151 |
1 |
1 |
156 |
1 |
1 |
157 |
1 |
1 |
158 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_packer_fifo
| Total | Covered | Percent |
Conditions | 40 | 36 | 90.00 |
Logical | 40 | 36 | 90.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 137
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T4,T6,T18 |
LINE 137
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T4,T5,T6 |
1 | 1 | Covered | T4,T6,T18 |
LINE 137
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T6,T18 |
LINE 138
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Unreachable | |
LINE 139
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T4,T6,T18 |
LINE 140
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Unreachable | |
1 | 1 | Covered | T4,T6,T18 |
LINE 142
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
------1-----
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 142
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
----1----
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T6,T18 |
LINE 142
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
------------1------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Not Covered | |
LINE 147
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
------1-----
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 147
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
------------1------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Not Covered | |
LINE 151
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 151
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T6,T18 |
LINE 156
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T6,T18 |
1 | 0 | Covered | T4,T5,T6 |
1 | 1 | Covered | T4,T5,T6 |
LINE 156
SUB-EXPRESSION (depth_q == '0)
-------1-------
-1- | Status | Tests |
0 | Covered | T4,T6,T18 |
1 | Covered | T4,T5,T6 |
LINE 158
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T4,T6,T18 |
LINE 158
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
-1- | Status | Tests |
0 | Covered | T4,T6,T18 |
1 | Covered | T4,T5,T6 |
LINE 158
SUB-EXPRESSION (depth_q == '0)
-------1-------
-1- | Status | Tests |
0 | Covered | T4,T6,T18 |
1 | Covered | T4,T5,T6 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_packer_fifo
| Line No. | Total | Covered | Percent |
Branches |
|
14 |
12 |
85.71 |
TERNARY |
142 |
4 |
3 |
75.00 |
TERNARY |
147 |
3 |
2 |
66.67 |
TERNARY |
151 |
3 |
3 |
100.00 |
IF |
82 |
2 |
2 |
100.00 |
IF |
127 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 142 (clear_status) ?
-2-: 142 (load_data) ?
-3-: 142 (gen_unpack_mode.pull_data) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T4,T6,T18 |
0 |
0 |
1 |
Not Covered |
|
0 |
0 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 147 (clear_status) ?
-2-: 147 (gen_unpack_mode.pull_data) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T4,T5,T6 |
0 |
1 |
Not Covered |
|
0 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 151 (clear_data) ?
-2-: 151 (load_data) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T4,T5,T6 |
0 |
1 |
Covered |
T4,T6,T18 |
0 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 82 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 127 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_packer_fifo
Assertion Details
DataOStableWhenPending_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460254785 |
0 |
0 |
972 |
ValidOPairedWithReadyI_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460254785 |
0 |
0 |
0 |