Module Definition
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Module : prim_edn_req
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.15 100.00 84.62 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_edn_req_0.1/rtl/prim_edn_req.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if 96.15 100.00 84.62 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.15 100.00 84.62 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.08 100.00 86.44 94.87 75.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.74 96.47 89.29 99.75 100.00 68.18 u_rv_core_ibex


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_packer_fifo 68.93 100.00 90.00 85.71 0.00
u_prim_sync_reqack_data 91.67 100.00 66.67 100.00 100.00

Line Coverage for Module : prim_edn_req
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN13911100.00
ALWAYS14333100.00
CONT_ASSIGN14911100.00
ALWAYS16300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_edn_req_0.1/rtl/prim_edn_req.sv' or '../src/lowrisc_prim_edn_req_0.1/rtl/prim_edn_req.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
139 1 1
143 1 1
144 1 1
146 1 1
149 1 1
163 unreachable
164 unreachable
165 unreachable
166 unreachable
167 unreachable
168 unreachable
==> MISSING_ELSE


Cond Coverage for Module : prim_edn_req
TotalCoveredPercent
Conditions131184.62
Logical131184.62
Non-Logical00
Event00

 LINE       54
 EXPRESSION (req_i & ((~ack_o)))
             --1--   -----2----
-1--2-StatusTests
01CoveredT4,T6,T18
10CoveredT4,T6,T18
11CoveredT4,T5,T6

 LINE       139
 EXPRESSION ((req_i && ack_o) ? 1'b1 : (word_ack ? (fips_q & word_fips) : fips_q))
             --------1-------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T6,T18

 LINE       139
 SUB-EXPRESSION (req_i && ack_o)
                 --1--    --2--
-1--2-StatusTests
01Not Covered
10CoveredT4,T5,T6
11CoveredT4,T6,T18

 LINE       139
 SUB-EXPRESSION (word_ack ? (fips_q & word_fips) : fips_q)
                 ----1---
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T6,T18

 LINE       139
 SUB-EXPRESSION (fips_q & word_fips)
                 ---1--   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT4,T6,T18
11CoveredT85,T102,T244

Branch Coverage for Module : prim_edn_req
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 139 3 3 100.00
IF 143 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_edn_req_0.1/rtl/prim_edn_req.sv' or '../src/lowrisc_prim_edn_req_0.1/rtl/prim_edn_req.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 139 ((req_i && ack_o)) ? -2-: 139 (word_ack) ?

Branches:
-1--2-StatusTests
1 - Covered T4,T6,T18
0 1 Covered T4,T6,T18
0 0 Covered T4,T5,T6


LineNo. Expression -1-: 143 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


Assert Coverage for Module : prim_edn_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataOutputDiffFromPrev_A 459604051 68568871 0 0
DataOutputValid_A 460254785 3896 0 0


DataOutputDiffFromPrev_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459604051 68568871 0 0
T53 139484 103221 0 0
T54 0 103190 0 0
T55 0 103172 0 0
T61 269670 0 0 0
T62 250641 0 0 0
T85 169620 122524 0 0
T86 133994 0 0 0
T87 235330 0 0 0
T88 594387 0 0 0
T89 208181 0 0 0
T90 196560 0 0 0
T123 402829 0 0 0
T199 0 433106 0 0
T367 0 103220 0 0
T368 0 103172 0 0
T396 0 765666 0 0
T397 0 996761 0 0
T398 0 997426 0 0

DataOutputValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 460254785 3896 0 0
T4 106658 1 0 0
T5 208140 0 0 0
T6 154966 2 0 0
T18 438609 4 0 0
T19 246835 4 0 0
T20 397861 2 0 0
T75 0 2 0 0
T80 181788 1 0 0
T81 73297 1 0 0
T82 759423 2 0 0
T83 261768 3 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN13911100.00
ALWAYS14333100.00
CONT_ASSIGN14911100.00
ALWAYS16300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_edn_req_0.1/rtl/prim_edn_req.sv' or '../src/lowrisc_prim_edn_req_0.1/rtl/prim_edn_req.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
139 1 1
143 1 1
144 1 1
146 1 1
149 1 1
163 unreachable
164 unreachable
165 unreachable
166 unreachable
167 unreachable
168 unreachable
==> MISSING_ELSE


Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if
TotalCoveredPercent
Conditions131184.62
Logical131184.62
Non-Logical00
Event00

 LINE       54
 EXPRESSION (req_i & ((~ack_o)))
             --1--   -----2----
-1--2-StatusTests
01CoveredT4,T6,T18
10CoveredT4,T6,T18
11CoveredT4,T5,T6

 LINE       139
 EXPRESSION ((req_i && ack_o) ? 1'b1 : (word_ack ? (fips_q & word_fips) : fips_q))
             --------1-------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T6,T18

 LINE       139
 SUB-EXPRESSION (req_i && ack_o)
                 --1--    --2--
-1--2-StatusTests
01Not Covered
10CoveredT4,T5,T6
11CoveredT4,T6,T18

 LINE       139
 SUB-EXPRESSION (word_ack ? (fips_q & word_fips) : fips_q)
                 ----1---
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T6,T18

 LINE       139
 SUB-EXPRESSION (fips_q & word_fips)
                 ---1--   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT4,T6,T18
11CoveredT85,T102,T244

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 139 3 3 100.00
IF 143 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_edn_req_0.1/rtl/prim_edn_req.sv' or '../src/lowrisc_prim_edn_req_0.1/rtl/prim_edn_req.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 139 ((req_i && ack_o)) ? -2-: 139 (word_ack) ?

Branches:
-1--2-StatusTests
1 - Covered T4,T6,T18
0 1 Covered T4,T6,T18
0 0 Covered T4,T5,T6


LineNo. Expression -1-: 143 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataOutputDiffFromPrev_A 459604051 68568871 0 0
DataOutputValid_A 460254785 3896 0 0


DataOutputDiffFromPrev_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459604051 68568871 0 0
T53 139484 103221 0 0
T54 0 103190 0 0
T55 0 103172 0 0
T61 269670 0 0 0
T62 250641 0 0 0
T85 169620 122524 0 0
T86 133994 0 0 0
T87 235330 0 0 0
T88 594387 0 0 0
T89 208181 0 0 0
T90 196560 0 0 0
T123 402829 0 0 0
T199 0 433106 0 0
T367 0 103220 0 0
T368 0 103172 0 0
T396 0 765666 0 0
T397 0 996761 0 0
T398 0 997426 0 0

DataOutputValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 460254785 3896 0 0
T4 106658 1 0 0
T5 208140 0 0 0
T6 154966 2 0 0
T18 438609 4 0 0
T19 246835 4 0 0
T20 397861 2 0 0
T75 0 2 0 0
T80 181788 1 0 0
T81 73297 1 0 0
T82 759423 2 0 0
T83 261768 3 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%