SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data | 100.00 | 100.00 | 100.00 | ||||
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
91.67 | 100.00 | 66.67 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
90.74 | 96.47 | 89.29 | 99.75 | 100.00 | 68.18 | u_rv_core_ibex |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
u_prim_sync_reqack | 91.67 | 100.00 | 66.67 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
91.67 | 100.00 | 66.67 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.15 | 100.00 | 84.62 | 100.00 | 100.00 | u_edn_if |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
u_prim_sync_reqack | 91.67 | 100.00 | 66.67 | 100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 1 | 1 | 100.00 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 153 | 0 | 0 | |
CONT_ASSIGN | 156 | 0 | 0 | |
ALWAYS | 159 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
93 | 1 | 1 | |
153 | unreachable | ||
156 | unreachable | ||
159 | unreachable | ||
160 | unreachable | ||
162 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA | 920509570 | 3935 | 0 | 0 |
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB | 920509570 | 3935 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 920509570 | 3935 | 0 | 0 |
T4 | 106658 | 1 | 0 | 0 |
T5 | 208140 | 0 | 0 | 0 |
T6 | 154966 | 2 | 0 | 0 |
T18 | 438609 | 4 | 0 | 0 |
T19 | 246835 | 4 | 0 | 0 |
T20 | 397861 | 2 | 0 | 0 |
T27 | 204182 | 0 | 0 | 0 |
T75 | 0 | 2 | 0 | 0 |
T80 | 181788 | 1 | 0 | 0 |
T81 | 73297 | 1 | 0 | 0 |
T82 | 759423 | 2 | 0 | 0 |
T83 | 261768 | 3 | 0 | 0 |
T156 | 137867 | 0 | 0 | 0 |
T170 | 86625 | 8 | 0 | 0 |
T172 | 0 | 5 | 0 | 0 |
T173 | 0 | 5 | 0 | 0 |
T209 | 255084 | 0 | 0 | 0 |
T212 | 246084 | 0 | 0 | 0 |
T232 | 255830 | 0 | 0 | 0 |
T270 | 234813 | 0 | 0 | 0 |
T281 | 0 | 5 | 0 | 0 |
T282 | 0 | 8 | 0 | 0 |
T283 | 0 | 8 | 0 | 0 |
T284 | 154451 | 0 | 0 | 0 |
T285 | 77691 | 0 | 0 | 0 |
T286 | 90055 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 920509570 | 3935 | 0 | 0 |
T4 | 106658 | 1 | 0 | 0 |
T5 | 208140 | 0 | 0 | 0 |
T6 | 154966 | 2 | 0 | 0 |
T18 | 438609 | 4 | 0 | 0 |
T19 | 246835 | 4 | 0 | 0 |
T20 | 397861 | 2 | 0 | 0 |
T27 | 204182 | 0 | 0 | 0 |
T75 | 0 | 2 | 0 | 0 |
T80 | 181788 | 1 | 0 | 0 |
T81 | 73297 | 1 | 0 | 0 |
T82 | 759423 | 2 | 0 | 0 |
T83 | 261768 | 3 | 0 | 0 |
T156 | 137867 | 0 | 0 | 0 |
T170 | 86625 | 8 | 0 | 0 |
T172 | 0 | 5 | 0 | 0 |
T173 | 0 | 5 | 0 | 0 |
T209 | 255084 | 0 | 0 | 0 |
T212 | 246084 | 0 | 0 | 0 |
T232 | 255830 | 0 | 0 | 0 |
T270 | 234813 | 0 | 0 | 0 |
T281 | 0 | 5 | 0 | 0 |
T282 | 0 | 8 | 0 | 0 |
T283 | 0 | 8 | 0 | 0 |
T284 | 154451 | 0 | 0 | 0 |
T285 | 77691 | 0 | 0 | 0 |
T286 | 90055 | 0 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 1 | 1 | 100.00 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 153 | 0 | 0 | |
CONT_ASSIGN | 156 | 0 | 0 | |
ALWAYS | 159 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
93 | 1 | 1 | |
153 | unreachable | ||
156 | unreachable | ||
159 | unreachable | ||
160 | unreachable | ||
162 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA | 460254785 | 39 | 0 | 0 |
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB | 460254785 | 39 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 460254785 | 39 | 0 | 0 |
T27 | 204182 | 0 | 0 | 0 |
T156 | 137867 | 0 | 0 | 0 |
T170 | 86625 | 8 | 0 | 0 |
T172 | 0 | 5 | 0 | 0 |
T173 | 0 | 5 | 0 | 0 |
T209 | 255084 | 0 | 0 | 0 |
T212 | 246084 | 0 | 0 | 0 |
T232 | 255830 | 0 | 0 | 0 |
T270 | 234813 | 0 | 0 | 0 |
T281 | 0 | 5 | 0 | 0 |
T282 | 0 | 8 | 0 | 0 |
T283 | 0 | 8 | 0 | 0 |
T284 | 154451 | 0 | 0 | 0 |
T285 | 77691 | 0 | 0 | 0 |
T286 | 90055 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 460254785 | 39 | 0 | 0 |
T27 | 204182 | 0 | 0 | 0 |
T156 | 137867 | 0 | 0 | 0 |
T170 | 86625 | 8 | 0 | 0 |
T172 | 0 | 5 | 0 | 0 |
T173 | 0 | 5 | 0 | 0 |
T209 | 255084 | 0 | 0 | 0 |
T212 | 246084 | 0 | 0 | 0 |
T232 | 255830 | 0 | 0 | 0 |
T270 | 234813 | 0 | 0 | 0 |
T281 | 0 | 5 | 0 | 0 |
T282 | 0 | 8 | 0 | 0 |
T283 | 0 | 8 | 0 | 0 |
T284 | 154451 | 0 | 0 | 0 |
T285 | 77691 | 0 | 0 | 0 |
T286 | 90055 | 0 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 1 | 1 | 100.00 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 153 | 0 | 0 | |
CONT_ASSIGN | 156 | 0 | 0 | |
ALWAYS | 159 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
93 | 1 | 1 | |
153 | unreachable | ||
156 | unreachable | ||
159 | unreachable | ||
160 | unreachable | ||
162 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA | 460254785 | 3896 | 0 | 0 |
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB | 460254785 | 3896 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 460254785 | 3896 | 0 | 0 |
T4 | 106658 | 1 | 0 | 0 |
T5 | 208140 | 0 | 0 | 0 |
T6 | 154966 | 2 | 0 | 0 |
T18 | 438609 | 4 | 0 | 0 |
T19 | 246835 | 4 | 0 | 0 |
T20 | 397861 | 2 | 0 | 0 |
T75 | 0 | 2 | 0 | 0 |
T80 | 181788 | 1 | 0 | 0 |
T81 | 73297 | 1 | 0 | 0 |
T82 | 759423 | 2 | 0 | 0 |
T83 | 261768 | 3 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 460254785 | 3896 | 0 | 0 |
T4 | 106658 | 1 | 0 | 0 |
T5 | 208140 | 0 | 0 | 0 |
T6 | 154966 | 2 | 0 | 0 |
T18 | 438609 | 4 | 0 | 0 |
T19 | 246835 | 4 | 0 | 0 |
T20 | 397861 | 2 | 0 | 0 |
T75 | 0 | 2 | 0 | 0 |
T80 | 181788 | 1 | 0 | 0 |
T81 | 73297 | 1 | 0 | 0 |
T82 | 759423 | 2 | 0 | 0 |
T83 | 261768 | 3 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |