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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.10 95.39 93.96 95.30 94.85 97.53 99.55


Total test records in report: 2866
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T296 /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.4130907823 Jun 24 08:40:23 PM PDT 24 Jun 24 08:46:53 PM PDT 24 3282892444 ps
T151 /workspace/coverage/default/0.chip_plic_all_irqs_10.1938990754 Jun 24 08:07:19 PM PDT 24 Jun 24 08:14:41 PM PDT 24 3960692246 ps
T78 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.1636823682 Jun 24 08:08:30 PM PDT 24 Jun 24 08:31:35 PM PDT 24 11693343528 ps
T863 /workspace/coverage/default/1.chip_sw_hmac_enc_idle.504969040 Jun 24 08:14:20 PM PDT 24 Jun 24 08:18:05 PM PDT 24 3118307778 ps
T864 /workspace/coverage/default/2.chip_sw_aes_idle.3277657373 Jun 24 08:24:14 PM PDT 24 Jun 24 08:29:44 PM PDT 24 3225058808 ps
T865 /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.1999054673 Jun 24 08:32:35 PM PDT 24 Jun 24 08:41:26 PM PDT 24 5196439846 ps
T32 /workspace/coverage/default/0.chip_sw_usbdev_pullup.3567739513 Jun 24 08:03:40 PM PDT 24 Jun 24 08:07:55 PM PDT 24 2570983840 ps
T250 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.3470256332 Jun 24 08:09:55 PM PDT 24 Jun 24 08:12:02 PM PDT 24 2572606436 ps
T243 /workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.2160810930 Jun 24 08:31:41 PM PDT 24 Jun 24 10:06:51 PM PDT 24 26703549660 ps
T331 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.3398750780 Jun 24 08:22:20 PM PDT 24 Jun 24 08:34:16 PM PDT 24 3888644854 ps
T639 /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.2074917331 Jun 24 08:13:05 PM PDT 24 Jun 24 08:21:40 PM PDT 24 4266276266 ps
T26 /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.3184537077 Jun 24 08:21:28 PM PDT 24 Jun 24 08:26:14 PM PDT 24 3041941648 ps
T866 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3017330962 Jun 24 08:26:38 PM PDT 24 Jun 24 08:38:15 PM PDT 24 3990123550 ps
T867 /workspace/coverage/default/40.chip_sw_all_escalation_resets.123457228 Jun 24 08:38:42 PM PDT 24 Jun 24 08:48:17 PM PDT 24 4758598340 ps
T868 /workspace/coverage/default/1.chip_tap_straps_dev.2448798537 Jun 24 08:17:22 PM PDT 24 Jun 24 08:39:42 PM PDT 24 10776250402 ps
T106 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.1210290226 Jun 24 08:14:47 PM PDT 24 Jun 24 08:31:14 PM PDT 24 5252390119 ps
T736 /workspace/coverage/default/22.chip_sw_all_escalation_resets.1373582345 Jun 24 08:37:39 PM PDT 24 Jun 24 08:49:20 PM PDT 24 4987956902 ps
T869 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2387054068 Jun 24 08:18:33 PM PDT 24 Jun 24 08:38:44 PM PDT 24 7235180150 ps
T340 /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.1094092269 Jun 24 08:37:10 PM PDT 24 Jun 24 09:01:02 PM PDT 24 9218598100 ps
T870 /workspace/coverage/default/2.chip_sw_ast_clk_outputs.1435156072 Jun 24 08:27:14 PM PDT 24 Jun 24 08:45:28 PM PDT 24 8588616296 ps
T234 /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.1340875341 Jun 24 08:04:35 PM PDT 24 Jun 24 08:12:35 PM PDT 24 5218900060 ps
T289 /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3619349740 Jun 24 08:28:04 PM PDT 24 Jun 24 08:38:21 PM PDT 24 5124867264 ps
T666 /workspace/coverage/default/60.chip_sw_all_escalation_resets.3066161999 Jun 24 08:39:29 PM PDT 24 Jun 24 08:46:46 PM PDT 24 5444694018 ps
T220 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.1573183552 Jun 24 08:14:44 PM PDT 24 Jun 24 08:51:17 PM PDT 24 10400546300 ps
T871 /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.1292230195 Jun 24 08:26:37 PM PDT 24 Jun 24 08:34:42 PM PDT 24 4592255724 ps
T699 /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.2015725624 Jun 24 08:38:21 PM PDT 24 Jun 24 08:44:05 PM PDT 24 3446980736 ps
T872 /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.4293470466 Jun 24 08:13:49 PM PDT 24 Jun 24 08:31:10 PM PDT 24 5621492756 ps
T201 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.2471896650 Jun 24 08:03:45 PM PDT 24 Jun 24 08:17:24 PM PDT 24 5065046090 ps
T200 /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2240239869 Jun 24 08:06:21 PM PDT 24 Jun 24 11:50:04 PM PDT 24 254390033900 ps
T873 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.916561340 Jun 24 08:26:47 PM PDT 24 Jun 24 08:35:19 PM PDT 24 3903191272 ps
T675 /workspace/coverage/default/73.chip_sw_all_escalation_resets.2059568244 Jun 24 08:40:09 PM PDT 24 Jun 24 08:49:10 PM PDT 24 5418316560 ps
T874 /workspace/coverage/default/49.chip_sw_all_escalation_resets.2081687155 Jun 24 08:39:29 PM PDT 24 Jun 24 08:50:56 PM PDT 24 6180393768 ps
T875 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.3907546565 Jun 24 08:13:20 PM PDT 24 Jun 24 08:21:59 PM PDT 24 4492499736 ps
T749 /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.555639715 Jun 24 08:36:27 PM PDT 24 Jun 24 08:41:18 PM PDT 24 3698625832 ps
T2 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.47306121 Jun 24 08:08:43 PM PDT 24 Jun 24 08:44:45 PM PDT 24 23846921636 ps
T91 /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.2578465169 Jun 24 08:14:42 PM PDT 24 Jun 24 08:23:44 PM PDT 24 9371865941 ps
T92 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.3118316274 Jun 24 08:11:15 PM PDT 24 Jun 24 08:20:23 PM PDT 24 6803217934 ps
T93 /workspace/coverage/default/4.chip_tap_straps_dev.860909564 Jun 24 08:32:23 PM PDT 24 Jun 24 08:58:28 PM PDT 24 12646179639 ps
T94 /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.2265700570 Jun 24 08:12:03 PM PDT 24 Jun 24 09:04:44 PM PDT 24 11337276864 ps
T45 /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.1247474297 Jun 24 08:05:58 PM PDT 24 Jun 24 08:12:06 PM PDT 24 2554371980 ps
T95 /workspace/coverage/default/1.chip_sw_aes_idle.3315654110 Jun 24 08:19:10 PM PDT 24 Jun 24 08:23:23 PM PDT 24 2802349028 ps
T96 /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.205600609 Jun 24 08:22:29 PM PDT 24 Jun 24 08:30:32 PM PDT 24 3847042244 ps
T97 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.922347048 Jun 24 08:03:28 PM PDT 24 Jun 24 08:17:09 PM PDT 24 5586789096 ps
T98 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.3920977379 Jun 24 08:16:03 PM PDT 24 Jun 24 08:24:59 PM PDT 24 3968842264 ps
T876 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1910091375 Jun 24 08:27:24 PM PDT 24 Jun 24 08:39:39 PM PDT 24 5085957134 ps
T48 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.4016454529 Jun 24 08:04:53 PM PDT 24 Jun 24 08:15:08 PM PDT 24 5941811520 ps
T877 /workspace/coverage/default/1.chip_sw_aes_entropy.3952773391 Jun 24 08:13:05 PM PDT 24 Jun 24 08:18:30 PM PDT 24 3163093428 ps
T217 /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.2398614690 Jun 24 08:06:38 PM PDT 24 Jun 24 08:36:11 PM PDT 24 8797570712 ps
T671 /workspace/coverage/default/63.chip_sw_all_escalation_resets.2243160512 Jun 24 08:38:55 PM PDT 24 Jun 24 08:50:31 PM PDT 24 4926953988 ps
T673 /workspace/coverage/default/65.chip_sw_all_escalation_resets.3039069138 Jun 24 08:40:58 PM PDT 24 Jun 24 08:52:56 PM PDT 24 4885782308 ps
T225 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.635248769 Jun 24 08:12:02 PM PDT 24 Jun 24 09:39:41 PM PDT 24 49950576200 ps
T29 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.3015491494 Jun 24 08:33:29 PM PDT 24 Jun 24 08:45:53 PM PDT 24 4111853316 ps
T49 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.376073273 Jun 24 08:12:49 PM PDT 24 Jun 24 08:22:36 PM PDT 24 6822892500 ps
T342 /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.2520443912 Jun 24 08:38:05 PM PDT 24 Jun 24 08:50:32 PM PDT 24 3912505472 ps
T878 /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.2471434041 Jun 24 08:31:08 PM PDT 24 Jun 24 08:35:20 PM PDT 24 3190990120 ps
T879 /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.149968192 Jun 24 08:24:05 PM PDT 24 Jun 24 08:32:41 PM PDT 24 3697433660 ps
T223 /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.1649356552 Jun 24 08:11:53 PM PDT 24 Jun 24 09:44:28 PM PDT 24 46539775600 ps
T880 /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.2226850443 Jun 24 08:31:35 PM PDT 24 Jun 24 08:35:37 PM PDT 24 2890790330 ps
T382 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1975303582 Jun 24 08:12:38 PM PDT 24 Jun 24 09:57:39 PM PDT 24 25173494540 ps
T751 /workspace/coverage/default/24.chip_sw_all_escalation_resets.1473236840 Jun 24 08:37:30 PM PDT 24 Jun 24 08:48:02 PM PDT 24 5353049708 ps
T881 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.1489392442 Jun 24 08:26:31 PM PDT 24 Jun 24 08:36:58 PM PDT 24 6191832232 ps
T882 /workspace/coverage/default/1.chip_sw_flash_crash_alert.2996285482 Jun 24 08:19:29 PM PDT 24 Jun 24 08:32:08 PM PDT 24 5686465578 ps
T883 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.440905719 Jun 24 08:28:18 PM PDT 24 Jun 24 08:35:12 PM PDT 24 3441062310 ps
T251 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1794214246 Jun 24 08:27:31 PM PDT 24 Jun 24 08:29:56 PM PDT 24 2979522343 ps
T884 /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.1439736409 Jun 24 08:30:39 PM PDT 24 Jun 24 08:35:45 PM PDT 24 2984633432 ps
T125 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2521613480 Jun 24 08:08:05 PM PDT 24 Jun 24 08:16:20 PM PDT 24 5572615648 ps
T885 /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.2197068525 Jun 24 08:25:10 PM PDT 24 Jun 24 08:28:25 PM PDT 24 3092062620 ps
T424 /workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.4255726212 Jun 24 08:33:53 PM PDT 24 Jun 24 10:20:59 PM PDT 24 29290234550 ps
T252 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3669022667 Jun 24 08:10:58 PM PDT 24 Jun 24 08:12:57 PM PDT 24 2517104044 ps
T886 /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.1749844833 Jun 24 08:25:01 PM PDT 24 Jun 24 08:29:49 PM PDT 24 3001078122 ps
T348 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3524592470 Jun 24 08:04:37 PM PDT 24 Jun 24 08:27:24 PM PDT 24 9164210542 ps
T887 /workspace/coverage/default/0.chip_sw_aon_timer_irq.1646023036 Jun 24 08:04:42 PM PDT 24 Jun 24 08:10:19 PM PDT 24 3419781088 ps
T888 /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.474845728 Jun 24 08:32:27 PM PDT 24 Jun 24 08:36:28 PM PDT 24 2250096640 ps
T889 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.3149848955 Jun 24 08:26:55 PM PDT 24 Jun 24 09:37:53 PM PDT 24 17557278450 ps
T188 /workspace/coverage/default/0.chip_jtag_mem_access.833836246 Jun 24 07:57:29 PM PDT 24 Jun 24 08:25:02 PM PDT 24 13485703080 ps
T356 /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3005432882 Jun 24 08:18:44 PM PDT 24 Jun 24 08:27:11 PM PDT 24 5950632572 ps
T189 /workspace/coverage/default/1.chip_jtag_csr_rw.3043744972 Jun 24 08:10:03 PM PDT 24 Jun 24 08:14:46 PM PDT 24 3678951144 ps
T890 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.190340032 Jun 24 08:22:26 PM PDT 24 Jun 24 08:41:04 PM PDT 24 5387677138 ps
T423 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.4160792897 Jun 24 08:15:32 PM PDT 24 Jun 24 08:30:39 PM PDT 24 6208348160 ps
T185 /workspace/coverage/default/0.chip_sw_spi_device_pass_through.3263872713 Jun 24 08:04:28 PM PDT 24 Jun 24 08:15:48 PM PDT 24 5759350569 ps
T34 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.3475700241 Jun 24 08:03:11 PM PDT 24 Jun 24 08:38:29 PM PDT 24 22116358760 ps
T891 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.3143723191 Jun 24 08:05:52 PM PDT 24 Jun 24 08:12:39 PM PDT 24 6494725235 ps
T672 /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.2430076138 Jun 24 08:40:45 PM PDT 24 Jun 24 08:46:53 PM PDT 24 3841932280 ps
T658 /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.2709972782 Jun 24 08:41:19 PM PDT 24 Jun 24 08:48:39 PM PDT 24 3618933706 ps
T892 /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.4266479376 Jun 24 08:10:18 PM PDT 24 Jun 24 08:16:08 PM PDT 24 2780839440 ps
T893 /workspace/coverage/default/0.chip_sw_uart_tx_rx.1032536810 Jun 24 08:02:24 PM PDT 24 Jun 24 08:12:59 PM PDT 24 4533502182 ps
T894 /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.2723083789 Jun 24 08:14:10 PM PDT 24 Jun 24 08:22:12 PM PDT 24 5297541800 ps
T3 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3915905976 Jun 24 08:28:30 PM PDT 24 Jun 24 08:57:41 PM PDT 24 25027579980 ps
T895 /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.646638770 Jun 24 08:10:04 PM PDT 24 Jun 24 08:13:06 PM PDT 24 2412478208 ps
T728 /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.1090313982 Jun 24 08:40:06 PM PDT 24 Jun 24 08:47:24 PM PDT 24 4199220250 ps
T896 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.1908349896 Jun 24 08:26:26 PM PDT 24 Jun 24 08:48:19 PM PDT 24 6874173272 ps
T701 /workspace/coverage/default/85.chip_sw_all_escalation_resets.3507576276 Jun 24 08:42:21 PM PDT 24 Jun 24 08:52:19 PM PDT 24 5831950334 ps
T508 /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.3152532865 Jun 24 08:18:03 PM PDT 24 Jun 24 08:32:59 PM PDT 24 5060957496 ps
T897 /workspace/coverage/default/2.chip_sw_example_manufacturer.647577100 Jun 24 08:21:19 PM PDT 24 Jun 24 08:25:00 PM PDT 24 2716969072 ps
T730 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.1200538462 Jun 24 08:04:58 PM PDT 24 Jun 24 08:11:39 PM PDT 24 3732982740 ps
T898 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.4101363226 Jun 24 08:28:38 PM PDT 24 Jun 24 09:27:42 PM PDT 24 15774319130 ps
T159 /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.1352236301 Jun 24 08:22:02 PM PDT 24 Jun 24 08:26:39 PM PDT 24 3053450387 ps
T899 /workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.1592061070 Jun 24 08:05:31 PM PDT 24 Jun 24 08:09:56 PM PDT 24 3185806044 ps
T900 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.1139489033 Jun 24 08:06:51 PM PDT 24 Jun 24 08:28:17 PM PDT 24 8350829197 ps
T901 /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.3282105227 Jun 24 08:07:28 PM PDT 24 Jun 24 08:27:30 PM PDT 24 5738453800 ps
T264 /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.2303736655 Jun 24 08:24:51 PM PDT 24 Jun 24 08:34:10 PM PDT 24 3999926924 ps
T902 /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.393245325 Jun 24 08:05:05 PM PDT 24 Jun 24 08:24:08 PM PDT 24 5606379754 ps
T903 /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.2749204782 Jun 24 08:12:46 PM PDT 24 Jun 24 08:15:55 PM PDT 24 2130976884 ps
T904 /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.4075714884 Jun 24 08:04:04 PM PDT 24 Jun 24 08:09:00 PM PDT 24 2488347800 ps
T905 /workspace/coverage/default/2.chip_tap_straps_prod.3373509010 Jun 24 08:26:42 PM PDT 24 Jun 24 08:53:30 PM PDT 24 15998302340 ps
T227 /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.1884958670 Jun 24 08:20:27 PM PDT 24 Jun 24 08:53:30 PM PDT 24 25975014923 ps
T341 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.1364111225 Jun 24 08:30:22 PM PDT 24 Jun 24 08:41:48 PM PDT 24 4384437708 ps
T710 /workspace/coverage/default/46.chip_sw_all_escalation_resets.1399849662 Jun 24 08:39:48 PM PDT 24 Jun 24 08:51:47 PM PDT 24 6320229320 ps
T906 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3439263766 Jun 24 08:28:14 PM PDT 24 Jun 24 08:39:41 PM PDT 24 4642732424 ps
T650 /workspace/coverage/default/32.chip_sw_all_escalation_resets.744189668 Jun 24 08:37:13 PM PDT 24 Jun 24 08:46:07 PM PDT 24 4809304926 ps
T162 /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.2846843028 Jun 24 08:04:25 PM PDT 24 Jun 24 08:13:30 PM PDT 24 4413143424 ps
T716 /workspace/coverage/default/78.chip_sw_all_escalation_resets.1013905658 Jun 24 08:40:46 PM PDT 24 Jun 24 08:48:10 PM PDT 24 4201252576 ps
T339 /workspace/coverage/default/1.chip_sw_hmac_enc.3390665717 Jun 24 08:16:00 PM PDT 24 Jun 24 08:19:48 PM PDT 24 3482291624 ps
T907 /workspace/coverage/default/1.chip_sw_flash_ctrl_access.3697267624 Jun 24 08:20:48 PM PDT 24 Jun 24 08:36:31 PM PDT 24 5233979088 ps
T908 /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.61823981 Jun 24 08:36:49 PM PDT 24 Jun 24 09:48:59 PM PDT 24 18734088176 ps
T909 /workspace/coverage/default/57.chip_sw_all_escalation_resets.2241330479 Jun 24 08:40:39 PM PDT 24 Jun 24 08:48:53 PM PDT 24 5492506008 ps
T120 /workspace/coverage/default/1.chip_sw_entropy_src_csrng.3776553460 Jun 24 08:16:21 PM PDT 24 Jun 24 08:42:16 PM PDT 24 6735694620 ps
T9 /workspace/coverage/default/1.chip_sw_sleep_pin_wake.3875718222 Jun 24 08:07:24 PM PDT 24 Jun 24 08:11:16 PM PDT 24 3397944704 ps
T688 /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.2069720396 Jun 24 08:38:09 PM PDT 24 Jun 24 08:44:03 PM PDT 24 3712595068 ps
T910 /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.2899080261 Jun 24 08:08:51 PM PDT 24 Jun 24 08:37:09 PM PDT 24 9125334916 ps
T35 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.1836707465 Jun 24 08:24:20 PM PDT 24 Jun 24 08:31:27 PM PDT 24 3986488584 ps
T911 /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.2773805101 Jun 24 08:30:43 PM PDT 24 Jun 24 08:38:31 PM PDT 24 6353430672 ps
T912 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.4167361173 Jun 24 08:08:18 PM PDT 24 Jun 24 08:12:38 PM PDT 24 2919629567 ps
T238 /workspace/coverage/default/1.chip_sw_plic_sw_irq.1986264970 Jun 24 08:15:58 PM PDT 24 Jun 24 08:20:48 PM PDT 24 2881698744 ps
T913 /workspace/coverage/default/0.chip_sw_kmac_idle.1233632815 Jun 24 08:05:29 PM PDT 24 Jun 24 08:10:21 PM PDT 24 3388381864 ps
T914 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3157271043 Jun 24 08:12:00 PM PDT 24 Jun 24 08:57:58 PM PDT 24 22891324539 ps
T915 /workspace/coverage/default/1.chip_sw_otbn_randomness.4065787070 Jun 24 08:12:26 PM PDT 24 Jun 24 08:27:02 PM PDT 24 5473918308 ps
T916 /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.2409847584 Jun 24 08:26:30 PM PDT 24 Jun 24 08:30:47 PM PDT 24 2945763224 ps
T917 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.2921426470 Jun 24 08:32:50 PM PDT 24 Jun 24 08:43:10 PM PDT 24 4341806190 ps
T380 /workspace/coverage/default/1.chip_sw_edn_boot_mode.1482608293 Jun 24 08:15:26 PM PDT 24 Jun 24 08:25:00 PM PDT 24 2556884746 ps
T918 /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.29304461 Jun 24 08:11:20 PM PDT 24 Jun 24 08:22:18 PM PDT 24 5582141382 ps
T202 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.3017040922 Jun 24 08:09:36 PM PDT 24 Jun 24 08:21:48 PM PDT 24 5365930780 ps
T919 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.2302929783 Jun 24 08:23:28 PM PDT 24 Jun 24 08:36:34 PM PDT 24 9085641294 ps
T920 /workspace/coverage/default/0.chip_sw_hmac_multistream.873528331 Jun 24 08:06:24 PM PDT 24 Jun 24 08:35:38 PM PDT 24 7217883720 ps
T326 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.472013083 Jun 24 08:10:41 PM PDT 24 Jun 24 08:22:36 PM PDT 24 4683185248 ps
T725 /workspace/coverage/default/52.chip_sw_all_escalation_resets.1672846583 Jun 24 08:38:56 PM PDT 24 Jun 24 08:52:18 PM PDT 24 4996929000 ps
T921 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2837890901 Jun 24 08:28:35 PM PDT 24 Jun 24 08:33:03 PM PDT 24 2643190111 ps
T753 /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.1307741977 Jun 24 08:37:28 PM PDT 24 Jun 24 08:44:42 PM PDT 24 3979752758 ps
T383 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.1680850386 Jun 24 08:12:47 PM PDT 24 Jun 24 09:37:29 PM PDT 24 18723243580 ps
T922 /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.204435020 Jun 24 08:23:16 PM PDT 24 Jun 24 08:43:44 PM PDT 24 9857421953 ps
T923 /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.2215470220 Jun 24 08:29:03 PM PDT 24 Jun 24 08:39:21 PM PDT 24 4466713864 ps
T924 /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.909443775 Jun 24 08:31:05 PM PDT 24 Jun 24 08:35:58 PM PDT 24 2701542500 ps
T224 /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.3243308628 Jun 24 08:24:19 PM PDT 24 Jun 24 09:48:58 PM PDT 24 46103506488 ps
T167 /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.1258764485 Jun 24 08:06:29 PM PDT 24 Jun 24 08:12:21 PM PDT 24 3732319601 ps
T925 /workspace/coverage/default/0.rom_e2e_smoke.3547985530 Jun 24 08:11:39 PM PDT 24 Jun 24 09:13:59 PM PDT 24 15496965536 ps
T926 /workspace/coverage/default/2.rom_e2e_asm_init_prod.3967549232 Jun 24 08:34:34 PM PDT 24 Jun 24 09:29:09 PM PDT 24 15689306940 ps
T927 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.896481972 Jun 24 08:15:55 PM PDT 24 Jun 24 08:22:19 PM PDT 24 3328748593 ps
T928 /workspace/coverage/default/1.chip_sw_example_rom.3571777016 Jun 24 08:06:18 PM PDT 24 Jun 24 08:08:38 PM PDT 24 2919870464 ps
T929 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.854205706 Jun 24 08:05:47 PM PDT 24 Jun 24 08:37:39 PM PDT 24 8739900483 ps
T930 /workspace/coverage/default/2.chip_sw_csrng_smoketest.1771774389 Jun 24 08:31:46 PM PDT 24 Jun 24 08:35:20 PM PDT 24 3147304600 ps
T695 /workspace/coverage/default/18.chip_sw_all_escalation_resets.3172284836 Jun 24 08:36:56 PM PDT 24 Jun 24 08:46:46 PM PDT 24 5040242344 ps
T38 /workspace/coverage/default/0.chip_sw_gpio.1408388109 Jun 24 08:01:59 PM PDT 24 Jun 24 08:09:01 PM PDT 24 4516502736 ps
T10 /workspace/coverage/default/2.chip_sw_sleep_pin_wake.656124736 Jun 24 08:22:27 PM PDT 24 Jun 24 08:28:30 PM PDT 24 3534322008 ps
T376 /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.1165961083 Jun 24 08:04:11 PM PDT 24 Jun 24 08:09:05 PM PDT 24 2573430800 ps
T747 /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.4206251894 Jun 24 08:38:45 PM PDT 24 Jun 24 08:44:55 PM PDT 24 3039094940 ps
T665 /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.1632322936 Jun 24 08:38:32 PM PDT 24 Jun 24 08:46:29 PM PDT 24 3334764000 ps
T297 /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.86856312 Jun 24 08:39:12 PM PDT 24 Jun 24 08:46:38 PM PDT 24 4384603960 ps
T931 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.737368294 Jun 24 08:18:54 PM PDT 24 Jun 24 09:32:04 PM PDT 24 15536701550 ps
T932 /workspace/coverage/default/1.chip_sw_aes_masking_off.565320815 Jun 24 08:15:24 PM PDT 24 Jun 24 08:20:26 PM PDT 24 3288316571 ps
T361 /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.2981715122 Jun 24 08:41:14 PM PDT 24 Jun 24 08:46:48 PM PDT 24 4067910122 ps
T933 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3855455259 Jun 24 08:26:25 PM PDT 24 Jun 24 08:36:20 PM PDT 24 4211086132 ps
T317 /workspace/coverage/default/0.chip_sw_entropy_src_csrng.2818883755 Jun 24 08:03:23 PM PDT 24 Jun 24 08:29:25 PM PDT 24 7839985360 ps
T680 /workspace/coverage/default/21.chip_sw_all_escalation_resets.3898653303 Jun 24 08:35:35 PM PDT 24 Jun 24 08:52:35 PM PDT 24 5184749604 ps
T349 /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.3615137321 Jun 24 08:05:41 PM PDT 24 Jun 24 08:11:44 PM PDT 24 3273895576 ps
T334 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.1945273796 Jun 24 08:24:09 PM PDT 24 Jun 24 08:37:02 PM PDT 24 3640168200 ps
T126 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1090924407 Jun 24 08:26:26 PM PDT 24 Jun 24 08:34:30 PM PDT 24 5485924586 ps
T934 /workspace/coverage/default/2.chip_sw_aes_masking_off.3736932587 Jun 24 08:26:17 PM PDT 24 Jun 24 08:29:37 PM PDT 24 2840073974 ps
T935 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.3988289123 Jun 24 08:06:34 PM PDT 24 Jun 24 08:23:31 PM PDT 24 6373145818 ps
T936 /workspace/coverage/default/0.chip_sw_uart_smoketest.769568491 Jun 24 08:08:20 PM PDT 24 Jun 24 08:11:41 PM PDT 24 2902318200 ps
T937 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.3761155366 Jun 24 08:12:39 PM PDT 24 Jun 24 08:21:42 PM PDT 24 6032050096 ps
T938 /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.3824866237 Jun 24 08:10:47 PM PDT 24 Jun 24 08:16:31 PM PDT 24 4301420810 ps
T939 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3623367174 Jun 24 08:07:17 PM PDT 24 Jun 24 08:17:22 PM PDT 24 3694057872 ps
T940 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.3455726081 Jun 24 08:16:30 PM PDT 24 Jun 24 08:56:50 PM PDT 24 9233670610 ps
T59 /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.2932824166 Jun 24 08:04:44 PM PDT 24 Jun 24 08:13:36 PM PDT 24 4112421152 ps
T195 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.4285221435 Jun 24 08:12:01 PM PDT 24 Jun 24 08:40:38 PM PDT 24 21568972158 ps
T323 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.385181074 Jun 24 08:23:39 PM PDT 24 Jun 24 08:38:22 PM PDT 24 4323861892 ps
T196 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.1527040426 Jun 24 08:23:34 PM PDT 24 Jun 24 08:28:01 PM PDT 24 2673452510 ps
T941 /workspace/coverage/default/1.rom_e2e_asm_init_rma.2213688376 Jun 24 08:25:04 PM PDT 24 Jun 24 09:40:44 PM PDT 24 15243493770 ps
T942 /workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.1617410574 Jun 24 08:37:12 PM PDT 24 Jun 24 09:50:46 PM PDT 24 22360466000 ps
T754 /workspace/coverage/default/2.chip_sw_all_escalation_resets.887848132 Jun 24 08:25:45 PM PDT 24 Jun 24 08:40:41 PM PDT 24 5944704648 ps
T943 /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.2676556236 Jun 24 08:08:12 PM PDT 24 Jun 24 08:12:16 PM PDT 24 2752080300 ps
T944 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.3239200033 Jun 24 08:17:51 PM PDT 24 Jun 24 08:30:44 PM PDT 24 8286963468 ps
T298 /workspace/coverage/default/61.chip_sw_all_escalation_resets.1026977839 Jun 24 08:39:08 PM PDT 24 Jun 24 08:52:39 PM PDT 24 6063707710 ps
T192 /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.370025481 Jun 24 08:22:34 PM PDT 24 Jun 25 12:09:22 AM PDT 24 78935228416 ps
T945 /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.1424564990 Jun 24 08:11:12 PM PDT 24 Jun 24 08:14:29 PM PDT 24 2447938136 ps
T299 /workspace/coverage/default/7.chip_sw_all_escalation_resets.565035852 Jun 24 08:35:42 PM PDT 24 Jun 24 08:46:20 PM PDT 24 5251805878 ps
T946 /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.2082613503 Jun 24 08:18:45 PM PDT 24 Jun 24 08:40:47 PM PDT 24 5697752758 ps
T947 /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.288185434 Jun 24 08:35:35 PM PDT 24 Jun 24 08:43:36 PM PDT 24 6788670673 ps
T746 /workspace/coverage/default/12.chip_sw_all_escalation_resets.2402319286 Jun 24 08:35:52 PM PDT 24 Jun 24 08:43:57 PM PDT 24 4211338232 ps
T638 /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.3000034248 Jun 24 08:41:13 PM PDT 24 Jun 24 08:49:55 PM PDT 24 3430758080 ps
T948 /workspace/coverage/default/0.rom_e2e_asm_init_prod.435044039 Jun 24 08:12:45 PM PDT 24 Jun 24 09:21:38 PM PDT 24 15925719236 ps
T949 /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.2455223805 Jun 24 08:37:04 PM PDT 24 Jun 24 08:46:38 PM PDT 24 4539083512 ps
T335 /workspace/coverage/default/2.chip_sw_pattgen_ios.3697265455 Jun 24 08:21:48 PM PDT 24 Jun 24 08:26:13 PM PDT 24 3194260376 ps
T950 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.1574534979 Jun 24 08:06:31 PM PDT 24 Jun 24 08:15:10 PM PDT 24 2909887630 ps
T951 /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.1624123190 Jun 24 08:24:59 PM PDT 24 Jun 24 08:28:40 PM PDT 24 2147470370 ps
T952 /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.1654563741 Jun 24 08:05:08 PM PDT 24 Jun 24 08:11:25 PM PDT 24 4308786212 ps
T953 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.165419494 Jun 24 08:06:06 PM PDT 24 Jun 24 08:32:05 PM PDT 24 7241756368 ps
T702 /workspace/coverage/default/58.chip_sw_all_escalation_resets.1515576836 Jun 24 08:40:55 PM PDT 24 Jun 24 08:50:15 PM PDT 24 5175299224 ps
T954 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.680958765 Jun 24 08:24:47 PM PDT 24 Jun 24 08:59:18 PM PDT 24 8997770500 ps
T955 /workspace/coverage/default/2.chip_sw_flash_ctrl_access.1544042762 Jun 24 08:24:59 PM PDT 24 Jun 24 08:40:42 PM PDT 24 5041649750 ps
T327 /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.2019799011 Jun 24 08:02:59 PM PDT 24 Jun 24 08:12:16 PM PDT 24 4287009984 ps
T228 /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.1278310429 Jun 24 08:11:17 PM PDT 24 Jun 24 09:41:37 PM PDT 24 47579408228 ps
T659 /workspace/coverage/default/75.chip_sw_all_escalation_resets.1966806371 Jun 24 08:42:02 PM PDT 24 Jun 24 08:53:34 PM PDT 24 6095700952 ps
T186 /workspace/coverage/default/2.chip_sw_spi_device_pass_through.770175589 Jun 24 08:23:03 PM PDT 24 Jun 24 08:34:37 PM PDT 24 6108968983 ps
T956 /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.3246756701 Jun 24 08:05:07 PM PDT 24 Jun 24 08:11:35 PM PDT 24 4239649548 ps
T957 /workspace/coverage/default/1.chip_sival_flash_info_access.1871641162 Jun 24 08:09:21 PM PDT 24 Jun 24 08:14:23 PM PDT 24 3119876216 ps
T958 /workspace/coverage/default/0.chip_sw_power_idle_load.2545977342 Jun 24 08:07:41 PM PDT 24 Jun 24 08:18:05 PM PDT 24 4081208852 ps
T959 /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.3952927364 Jun 24 08:26:44 PM PDT 24 Jun 24 08:36:22 PM PDT 24 4161037500 ps
T683 /workspace/coverage/default/19.chip_sw_all_escalation_resets.3773826245 Jun 24 08:37:37 PM PDT 24 Jun 24 08:50:11 PM PDT 24 5202360100 ps
T960 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.1209362416 Jun 24 08:25:43 PM PDT 24 Jun 24 08:36:03 PM PDT 24 7391205304 ps
T961 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.4078648361 Jun 24 08:13:36 PM PDT 24 Jun 24 08:21:27 PM PDT 24 6691658418 ps
T962 /workspace/coverage/default/1.chip_sw_example_flash.2242230254 Jun 24 08:09:55 PM PDT 24 Jun 24 08:14:22 PM PDT 24 3117646136 ps
T174 /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.3089232657 Jun 24 08:08:36 PM PDT 24 Jun 24 09:40:46 PM PDT 24 44378654000 ps
T963 /workspace/coverage/default/41.chip_sw_all_escalation_resets.2743194489 Jun 24 08:38:49 PM PDT 24 Jun 24 08:48:01 PM PDT 24 4831286536 ps
T750 /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.2304903400 Jun 24 08:42:27 PM PDT 24 Jun 24 08:49:44 PM PDT 24 3472479012 ps
T964 /workspace/coverage/default/0.chip_sw_example_manufacturer.4120915787 Jun 24 08:04:16 PM PDT 24 Jun 24 08:07:19 PM PDT 24 2757305800 ps
T685 /workspace/coverage/default/8.chip_sw_all_escalation_resets.955250759 Jun 24 08:37:34 PM PDT 24 Jun 24 08:47:36 PM PDT 24 5568073352 ps
T965 /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1421751098 Jun 24 08:13:00 PM PDT 24 Jun 24 08:23:28 PM PDT 24 18918753860 ps
T966 /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.2273982594 Jun 24 08:36:06 PM PDT 24 Jun 24 08:58:43 PM PDT 24 7418564172 ps
T744 /workspace/coverage/default/37.chip_sw_all_escalation_resets.4118434322 Jun 24 08:38:10 PM PDT 24 Jun 24 08:53:46 PM PDT 24 5840128902 ps
T967 /workspace/coverage/default/2.chip_sw_hmac_oneshot.1805367834 Jun 24 08:28:16 PM PDT 24 Jun 24 08:33:15 PM PDT 24 2775565862 ps
T968 /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.211355534 Jun 24 08:23:20 PM PDT 24 Jun 24 08:58:39 PM PDT 24 30563760980 ps
T969 /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.2111846043 Jun 24 08:37:14 PM PDT 24 Jun 24 09:13:59 PM PDT 24 12895709086 ps
T726 /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.1536098220 Jun 24 08:37:09 PM PDT 24 Jun 24 08:43:34 PM PDT 24 3694257864 ps
T970 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.2393361020 Jun 24 08:08:28 PM PDT 24 Jun 24 09:11:39 PM PDT 24 17305854214 ps
T300 /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.3298223415 Jun 24 08:39:31 PM PDT 24 Jun 24 08:45:47 PM PDT 24 3659068832 ps
T971 /workspace/coverage/default/2.chip_sw_kmac_idle.3878541253 Jun 24 08:28:18 PM PDT 24 Jun 24 08:31:31 PM PDT 24 2492325560 ps
T972 /workspace/coverage/default/1.chip_sw_power_idle_load.3150493332 Jun 24 08:18:31 PM PDT 24 Jun 24 08:34:50 PM PDT 24 4518651956 ps
T690 /workspace/coverage/default/10.chip_sw_all_escalation_resets.1694387494 Jun 24 08:37:47 PM PDT 24 Jun 24 08:50:12 PM PDT 24 5178563380 ps
T973 /workspace/coverage/default/3.chip_sw_uart_tx_rx.2671976761 Jun 24 08:31:03 PM PDT 24 Jun 24 08:41:56 PM PDT 24 4634826840 ps
T717 /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.3713974948 Jun 24 08:38:05 PM PDT 24 Jun 24 08:44:40 PM PDT 24 3078799082 ps
T974 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.4196728513 Jun 24 08:09:37 PM PDT 24 Jun 24 08:21:29 PM PDT 24 3637868104 ps
T653 /workspace/coverage/default/77.chip_sw_all_escalation_resets.722456520 Jun 24 08:42:03 PM PDT 24 Jun 24 08:52:25 PM PDT 24 5200205904 ps
T657 /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.4070360677 Jun 24 08:38:33 PM PDT 24 Jun 24 08:45:38 PM PDT 24 3605224428 ps
T975 /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.4138957042 Jun 24 08:36:45 PM PDT 24 Jun 24 08:42:37 PM PDT 24 3960796580 ps
T614 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.3917521378 Jun 24 08:05:02 PM PDT 24 Jun 24 08:06:45 PM PDT 24 2486002774 ps
T976 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2297724152 Jun 24 08:05:41 PM PDT 24 Jun 24 08:15:08 PM PDT 24 7117491366 ps
T229 /workspace/coverage/default/2.chip_sw_flash_init.1427454780 Jun 24 08:26:24 PM PDT 24 Jun 24 09:01:52 PM PDT 24 26463722200 ps
T357 /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3029200810 Jun 24 08:28:00 PM PDT 24 Jun 24 08:36:53 PM PDT 24 6994040320 ps
T153 /workspace/coverage/default/2.chip_sw_alert_handler_entropy.2845199500 Jun 24 08:24:05 PM PDT 24 Jun 24 08:29:39 PM PDT 24 2938070505 ps
T676 /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1361670776 Jun 24 08:41:37 PM PDT 24 Jun 24 08:47:41 PM PDT 24 3424584172 ps
T977 /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.585441072 Jun 24 08:06:57 PM PDT 24 Jun 24 08:16:33 PM PDT 24 8931926274 ps
T978 /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.2092627829 Jun 24 08:06:56 PM PDT 24 Jun 24 08:12:08 PM PDT 24 3303993658 ps
T979 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.3277824915 Jun 24 08:32:20 PM PDT 24 Jun 24 08:46:13 PM PDT 24 4462367200 ps
T330 /workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.3754244892 Jun 24 08:18:01 PM PDT 24 Jun 24 08:26:20 PM PDT 24 3946256180 ps
T218 /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.4097498521 Jun 24 08:25:34 PM PDT 24 Jun 24 08:46:29 PM PDT 24 7669062864 ps
T731 /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.3409482527 Jun 24 08:37:21 PM PDT 24 Jun 24 08:42:20 PM PDT 24 3657577560 ps
T15 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2229086257 Jun 24 08:19:11 PM PDT 24 Jun 24 08:25:10 PM PDT 24 7116792472 ps
T197 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.3072913290 Jun 24 08:12:17 PM PDT 24 Jun 24 08:18:06 PM PDT 24 4005981777 ps
T130 /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.2807332007 Jun 24 08:17:55 PM PDT 24 Jun 24 08:32:33 PM PDT 24 6061848880 ps
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