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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.10 95.39 93.96 95.30 94.85 97.53 99.55


Total test records in report: 2866
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T1143 /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.4286551035 Jun 24 08:08:10 PM PDT 24 Jun 24 08:12:38 PM PDT 24 3033050788 ps
T14 /workspace/coverage/default/2.chip_sw_sleep_pin_retention.1925650372 Jun 24 08:21:11 PM PDT 24 Jun 24 08:27:39 PM PDT 24 4478592736 ps
T1144 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.565777577 Jun 24 08:09:58 PM PDT 24 Jun 24 08:33:53 PM PDT 24 7558106066 ps
T1145 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.3488096050 Jun 24 08:03:56 PM PDT 24 Jun 24 08:27:20 PM PDT 24 7236556810 ps
T1146 /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.3118227645 Jun 24 08:26:47 PM PDT 24 Jun 24 08:45:50 PM PDT 24 9216279320 ps
T1147 /workspace/coverage/default/2.chip_sw_flash_crash_alert.2355365146 Jun 24 08:29:32 PM PDT 24 Jun 24 08:38:25 PM PDT 24 5556220038 ps
T1148 /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.2968642143 Jun 24 08:13:47 PM PDT 24 Jun 24 08:29:12 PM PDT 24 8225561265 ps
T1149 /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.2239650765 Jun 24 08:08:13 PM PDT 24 Jun 24 08:11:20 PM PDT 24 3003257880 ps
T1150 /workspace/coverage/default/1.chip_sw_uart_smoketest.1595453717 Jun 24 08:24:02 PM PDT 24 Jun 24 08:28:40 PM PDT 24 3043226420 ps
T608 /workspace/coverage/default/0.chip_sw_edn_boot_mode.2749484165 Jun 24 08:06:05 PM PDT 24 Jun 24 08:16:46 PM PDT 24 2646786360 ps
T637 /workspace/coverage/default/1.chip_sw_power_sleep_load.4134057929 Jun 24 08:18:25 PM PDT 24 Jun 24 08:25:08 PM PDT 24 4298890984 ps
T1151 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.1290119496 Jun 24 08:25:48 PM PDT 24 Jun 24 09:22:06 PM PDT 24 19265097443 ps
T219 /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.2838474040 Jun 24 08:14:31 PM PDT 24 Jun 24 08:57:25 PM PDT 24 13172964920 ps
T1152 /workspace/coverage/default/2.chip_sw_kmac_entropy.2665564476 Jun 24 08:21:38 PM PDT 24 Jun 24 08:25:55 PM PDT 24 2958109882 ps
T1153 /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.4249292300 Jun 24 08:35:38 PM PDT 24 Jun 24 08:45:00 PM PDT 24 6368896390 ps
T1154 /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.4060087973 Jun 24 08:38:54 PM PDT 24 Jun 24 08:45:48 PM PDT 24 3140898496 ps
T707 /workspace/coverage/default/93.chip_sw_all_escalation_resets.2297515783 Jun 24 08:41:11 PM PDT 24 Jun 24 08:50:09 PM PDT 24 4866784556 ps
T679 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.896206587 Jun 24 08:15:42 PM PDT 24 Jun 24 08:22:42 PM PDT 24 4073993462 ps
T1155 /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.2333518830 Jun 24 08:08:16 PM PDT 24 Jun 24 08:18:06 PM PDT 24 6095057690 ps
T1156 /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.3978596487 Jun 24 08:36:10 PM PDT 24 Jun 24 09:10:13 PM PDT 24 12767643630 ps
T1157 /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.1325135434 Jun 24 08:20:46 PM PDT 24 Jun 24 08:30:36 PM PDT 24 5012623642 ps
T682 /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.1119447968 Jun 24 08:37:41 PM PDT 24 Jun 24 08:45:47 PM PDT 24 3902893326 ps
T1158 /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.1554587986 Jun 24 08:03:11 PM PDT 24 Jun 24 11:59:55 PM PDT 24 78491598050 ps
T1159 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2511586190 Jun 24 08:05:53 PM PDT 24 Jun 24 08:16:03 PM PDT 24 4465730500 ps
T1160 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.3914110575 Jun 24 08:14:34 PM PDT 24 Jun 24 09:14:42 PM PDT 24 15522266296 ps
T1161 /workspace/coverage/default/1.chip_sw_inject_scramble_seed.1275020114 Jun 24 08:09:34 PM PDT 24 Jun 24 11:19:23 PM PDT 24 64268571583 ps
T104 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.3142505901 Jun 24 08:31:02 PM PDT 24 Jun 24 10:05:10 PM PDT 24 34132312165 ps
T1162 /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.4050581360 Jun 24 08:16:40 PM PDT 24 Jun 24 08:21:44 PM PDT 24 2961262618 ps
T1163 /workspace/coverage/default/0.rom_e2e_asm_init_rma.333020304 Jun 24 08:14:18 PM PDT 24 Jun 24 09:16:14 PM PDT 24 15211169622 ps
T1164 /workspace/coverage/default/0.chip_sw_otbn_randomness.3739754708 Jun 24 08:04:21 PM PDT 24 Jun 24 08:18:25 PM PDT 24 6035654784 ps
T1165 /workspace/coverage/default/1.chip_sw_clkmgr_jitter.2404181724 Jun 24 08:17:30 PM PDT 24 Jun 24 08:22:15 PM PDT 24 3188518865 ps
T1166 /workspace/coverage/default/1.chip_sw_data_integrity_escalation.3830380386 Jun 24 08:09:03 PM PDT 24 Jun 24 08:18:57 PM PDT 24 6145538078 ps
T743 /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.1307340944 Jun 24 08:37:38 PM PDT 24 Jun 24 08:44:32 PM PDT 24 3788986976 ps
T733 /workspace/coverage/default/84.chip_sw_all_escalation_resets.1089815432 Jun 24 08:42:30 PM PDT 24 Jun 24 08:49:27 PM PDT 24 5329311472 ps
T1167 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.1753661368 Jun 24 08:30:35 PM PDT 24 Jun 24 08:41:26 PM PDT 24 3893334741 ps
T1168 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1049010839 Jun 24 08:10:48 PM PDT 24 Jun 24 09:46:51 PM PDT 24 24042339464 ps
T663 /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.1538300211 Jun 24 08:35:24 PM PDT 24 Jun 24 08:41:35 PM PDT 24 3498613892 ps
T231 /workspace/coverage/default/0.chip_sw_flash_init.720028254 Jun 24 08:03:32 PM PDT 24 Jun 24 08:41:35 PM PDT 24 23373405216 ps
T1169 /workspace/coverage/default/0.chip_sw_edn_auto_mode.2216782143 Jun 24 08:06:52 PM PDT 24 Jun 24 08:27:47 PM PDT 24 4759981544 ps
T1170 /workspace/coverage/default/1.chip_tap_straps_prod.3243320852 Jun 24 08:18:03 PM PDT 24 Jun 24 08:20:49 PM PDT 24 2571202882 ps
T1171 /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.697165823 Jun 24 08:04:12 PM PDT 24 Jun 24 08:12:43 PM PDT 24 4381932418 ps
T613 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.754199472 Jun 24 08:17:02 PM PDT 24 Jun 24 08:30:02 PM PDT 24 5863917630 ps
T364 /workspace/coverage/default/70.chip_sw_all_escalation_resets.858774104 Jun 24 08:39:39 PM PDT 24 Jun 24 08:49:17 PM PDT 24 5332465950 ps
T1172 /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.2444794868 Jun 24 08:22:21 PM PDT 24 Jun 24 08:25:25 PM PDT 24 2807347322 ps
T1173 /workspace/coverage/default/2.chip_sw_hmac_multistream.3453023909 Jun 24 08:28:25 PM PDT 24 Jun 24 08:55:53 PM PDT 24 7750396660 ps
T1174 /workspace/coverage/default/1.chip_sw_edn_kat.1707987180 Jun 24 08:14:14 PM PDT 24 Jun 24 08:27:59 PM PDT 24 3353530204 ps
T1175 /workspace/coverage/default/2.rom_volatile_raw_unlock.2532731382 Jun 24 08:30:37 PM PDT 24 Jun 24 08:32:29 PM PDT 24 2068097592 ps
T687 /workspace/coverage/default/27.chip_sw_all_escalation_resets.452187704 Jun 24 08:37:08 PM PDT 24 Jun 24 08:44:53 PM PDT 24 5555414160 ps
T337 /workspace/coverage/default/1.chip_sw_pattgen_ios.1993085635 Jun 24 08:07:33 PM PDT 24 Jun 24 08:11:56 PM PDT 24 2842822210 ps
T17 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.3892633839 Jun 24 08:20:17 PM PDT 24 Jun 24 08:46:04 PM PDT 24 20801723374 ps
T1176 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.985756944 Jun 24 08:29:02 PM PDT 24 Jun 24 09:00:38 PM PDT 24 11270260224 ps
T287 /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.2780168898 Jun 24 08:05:59 PM PDT 24 Jun 24 08:23:29 PM PDT 24 9703710414 ps
T1177 /workspace/coverage/default/1.chip_sw_hmac_smoketest.1936351986 Jun 24 08:21:54 PM PDT 24 Jun 24 08:31:01 PM PDT 24 3323399096 ps
T1178 /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.2512653513 Jun 24 08:33:42 PM PDT 24 Jun 24 08:41:29 PM PDT 24 3332715464 ps
T652 /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.4176569054 Jun 24 08:36:54 PM PDT 24 Jun 24 08:43:49 PM PDT 24 4310981992 ps
T187 /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.864160599 Jun 24 08:21:05 PM PDT 24 Jun 24 08:29:11 PM PDT 24 4728859727 ps
T1179 /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.3348239568 Jun 24 08:25:24 PM PDT 24 Jun 24 08:53:59 PM PDT 24 10237512160 ps
T705 /workspace/coverage/default/69.chip_sw_all_escalation_resets.801116811 Jun 24 08:41:10 PM PDT 24 Jun 24 08:49:29 PM PDT 24 4703933896 ps
T1180 /workspace/coverage/default/2.chip_sw_otbn_randomness.2540899209 Jun 24 08:24:09 PM PDT 24 Jun 24 08:41:06 PM PDT 24 6161834312 ps
T1181 /workspace/coverage/default/31.chip_sw_all_escalation_resets.3907988252 Jun 24 08:38:00 PM PDT 24 Jun 24 08:47:40 PM PDT 24 5029021124 ps
T1182 /workspace/coverage/default/1.chip_sw_gpio_smoketest.3840859166 Jun 24 08:23:12 PM PDT 24 Jun 24 08:27:24 PM PDT 24 2956175300 ps
T1183 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.378457841 Jun 24 08:25:52 PM PDT 24 Jun 24 08:47:13 PM PDT 24 5729051432 ps
T1184 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.4071952975 Jun 24 08:22:28 PM PDT 24 Jun 24 08:27:05 PM PDT 24 3365818493 ps
T254 /workspace/coverage/default/4.chip_sw_data_integrity_escalation.2299271883 Jun 24 08:32:11 PM PDT 24 Jun 24 08:45:37 PM PDT 24 6748863152 ps
T256 /workspace/coverage/default/1.rom_e2e_smoke.2946458439 Jun 24 08:23:24 PM PDT 24 Jun 24 09:31:48 PM PDT 24 15040492200 ps
T257 /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.1755704103 Jun 24 08:22:54 PM PDT 24 Jun 24 08:54:09 PM PDT 24 8957182546 ps
T258 /workspace/coverage/default/92.chip_sw_all_escalation_resets.2433058659 Jun 24 08:42:35 PM PDT 24 Jun 24 08:52:08 PM PDT 24 5003365784 ps
T259 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.1465539235 Jun 24 08:25:48 PM PDT 24 Jun 24 09:01:51 PM PDT 24 12345966454 ps
T260 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.2523927665 Jun 24 08:26:45 PM PDT 24 Jun 24 08:36:35 PM PDT 24 5249204059 ps
T8 /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.857976768 Jun 24 08:29:48 PM PDT 24 Jun 24 08:36:54 PM PDT 24 3564631680 ps
T261 /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1717000770 Jun 24 08:40:16 PM PDT 24 Jun 24 08:47:02 PM PDT 24 3148927496 ps
T262 /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.3986028896 Jun 24 08:37:05 PM PDT 24 Jun 24 08:57:56 PM PDT 24 8295325960 ps
T263 /workspace/coverage/default/88.chip_sw_all_escalation_resets.4170617438 Jun 24 08:40:57 PM PDT 24 Jun 24 08:51:34 PM PDT 24 6369948844 ps
T1185 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.3549496749 Jun 24 08:06:32 PM PDT 24 Jun 24 08:59:40 PM PDT 24 19979744001 ps
T311 /workspace/coverage/default/0.chip_plic_all_irqs_0.2779231937 Jun 24 08:05:34 PM PDT 24 Jun 24 08:28:47 PM PDT 24 6426151928 ps
T738 /workspace/coverage/default/9.chip_sw_all_escalation_resets.220487992 Jun 24 08:36:19 PM PDT 24 Jun 24 08:45:30 PM PDT 24 4945430796 ps
T1186 /workspace/coverage/default/4.chip_sw_uart_tx_rx.3638084434 Jun 24 08:32:53 PM PDT 24 Jun 24 08:43:25 PM PDT 24 4048757910 ps
T1187 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.715310207 Jun 24 08:25:54 PM PDT 24 Jun 24 08:47:51 PM PDT 24 9052393072 ps
T1188 /workspace/coverage/default/2.chip_sw_uart_smoketest.1188191631 Jun 24 08:30:14 PM PDT 24 Jun 24 08:35:05 PM PDT 24 2770999820 ps
T350 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1818154807 Jun 24 08:29:07 PM PDT 24 Jun 24 08:40:09 PM PDT 24 4670197493 ps
T656 /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.1478835491 Jun 24 08:36:16 PM PDT 24 Jun 24 08:42:42 PM PDT 24 3163660186 ps
T248 /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.2875508666 Jun 24 08:11:38 PM PDT 24 Jun 24 08:21:32 PM PDT 24 5124084050 ps
T158 /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.3356951838 Jun 24 08:22:47 PM PDT 24 Jun 24 08:25:53 PM PDT 24 2996826655 ps
T1189 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.4269263739 Jun 24 08:24:55 PM PDT 24 Jun 24 08:56:02 PM PDT 24 10793466750 ps
T1190 /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.2950354299 Jun 24 08:32:37 PM PDT 24 Jun 24 08:40:23 PM PDT 24 3731821190 ps
T324 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.656103705 Jun 24 08:08:38 PM PDT 24 Jun 24 08:21:11 PM PDT 24 5165846136 ps
T283 /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.3265912226 Jun 24 08:17:36 PM PDT 24 Jun 24 08:20:36 PM PDT 24 2783385500 ps
T1191 /workspace/coverage/default/62.chip_sw_all_escalation_resets.1651602739 Jun 24 08:39:06 PM PDT 24 Jun 24 08:49:47 PM PDT 24 5453301084 ps
T1192 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.283056461 Jun 24 08:12:09 PM PDT 24 Jun 24 09:07:58 PM PDT 24 20430449885 ps
T1193 /workspace/coverage/default/1.chip_sw_csrng_smoketest.2935029487 Jun 24 08:23:41 PM PDT 24 Jun 24 08:27:04 PM PDT 24 2394725692 ps
T1194 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.2437145410 Jun 24 08:03:20 PM PDT 24 Jun 24 09:20:39 PM PDT 24 18824684408 ps
T1195 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.3342348043 Jun 24 08:29:10 PM PDT 24 Jun 24 08:32:18 PM PDT 24 2888282573 ps
T1196 /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.1786234560 Jun 24 08:29:27 PM PDT 24 Jun 24 08:48:51 PM PDT 24 5864606050 ps
T1197 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.3056337962 Jun 24 08:03:16 PM PDT 24 Jun 24 08:14:36 PM PDT 24 9417388604 ps
T1198 /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.2425333734 Jun 24 08:37:50 PM PDT 24 Jun 24 08:42:46 PM PDT 24 3433003678 ps
T1199 /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.3421846158 Jun 24 08:09:03 PM PDT 24 Jun 24 08:34:08 PM PDT 24 8218825840 ps
T1200 /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.1397047560 Jun 24 08:37:22 PM PDT 24 Jun 24 08:42:56 PM PDT 24 2879942056 ps
T1201 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3539071464 Jun 24 08:11:58 PM PDT 24 Jun 24 08:38:23 PM PDT 24 13877625456 ps
T724 /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.3901164948 Jun 24 08:37:36 PM PDT 24 Jun 24 08:45:10 PM PDT 24 4609077994 ps
T1202 /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.724029965 Jun 24 08:37:09 PM PDT 24 Jun 24 08:44:25 PM PDT 24 4435844612 ps
T1203 /workspace/coverage/default/42.chip_sw_all_escalation_resets.23079408 Jun 24 08:38:31 PM PDT 24 Jun 24 08:50:27 PM PDT 24 5583694960 ps
T1204 /workspace/coverage/default/0.chip_sw_edn_kat.2393031022 Jun 24 08:05:50 PM PDT 24 Jun 24 08:15:32 PM PDT 24 3491961796 ps
T1205 /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.3002254734 Jun 24 08:23:31 PM PDT 24 Jun 24 08:27:45 PM PDT 24 3046016264 ps
T1206 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.2219943820 Jun 24 08:05:20 PM PDT 24 Jun 24 08:09:18 PM PDT 24 3097043156 ps
T1207 /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.2666552538 Jun 24 08:25:08 PM PDT 24 Jun 24 08:32:00 PM PDT 24 3920925060 ps
T1208 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1857776637 Jun 24 08:25:26 PM PDT 24 Jun 24 09:20:00 PM PDT 24 42570918979 ps
T1209 /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.1327014831 Jun 24 08:28:47 PM PDT 24 Jun 24 08:35:18 PM PDT 24 3155327830 ps
T1210 /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.143678840 Jun 24 08:23:21 PM PDT 24 Jun 24 08:31:07 PM PDT 24 7004205208 ps
T1211 /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.2878516915 Jun 24 08:26:59 PM PDT 24 Jun 24 08:34:48 PM PDT 24 4580525480 ps
T1212 /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.3447500347 Jun 24 08:12:42 PM PDT 24 Jun 24 08:22:15 PM PDT 24 6441286350 ps
T1213 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.39803965 Jun 24 08:21:40 PM PDT 24 Jun 24 08:34:40 PM PDT 24 4549534086 ps
T1214 /workspace/coverage/default/1.chip_sw_kmac_app_rom.1435576208 Jun 24 08:17:03 PM PDT 24 Jun 24 08:20:47 PM PDT 24 3122314940 ps
T1215 /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.2515373050 Jun 24 08:41:00 PM PDT 24 Jun 24 08:46:51 PM PDT 24 3821825202 ps
T312 /workspace/coverage/default/2.chip_plic_all_irqs_0.2680569278 Jun 24 08:25:54 PM PDT 24 Jun 24 08:46:42 PM PDT 24 5924129730 ps
T1216 /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.117179422 Jun 24 08:11:50 PM PDT 24 Jun 24 08:19:38 PM PDT 24 5552486913 ps
T1217 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.4012706841 Jun 24 08:08:33 PM PDT 24 Jun 24 08:29:28 PM PDT 24 7688614949 ps
T1218 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.1759514816 Jun 24 08:06:19 PM PDT 24 Jun 24 08:10:55 PM PDT 24 2710954947 ps
T1219 /workspace/coverage/default/2.chip_sw_example_concurrency.342396789 Jun 24 08:22:54 PM PDT 24 Jun 24 08:27:01 PM PDT 24 3280976610 ps
T1220 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.2692405340 Jun 24 08:17:54 PM PDT 24 Jun 24 08:32:03 PM PDT 24 13731641056 ps
T50 /workspace/coverage/default/0.chip_sw_spi_device_tpm.3961204184 Jun 24 08:03:46 PM PDT 24 Jun 24 08:08:35 PM PDT 24 3592697650 ps
T1221 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.3861923525 Jun 24 08:25:54 PM PDT 24 Jun 24 08:37:09 PM PDT 24 4780141148 ps
T1222 /workspace/coverage/default/1.chip_sw_example_concurrency.1047979574 Jun 24 08:06:46 PM PDT 24 Jun 24 08:09:39 PM PDT 24 2473196546 ps
T402 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3963942300 Jun 24 08:06:13 PM PDT 24 Jun 24 08:34:31 PM PDT 24 23325124748 ps
T1223 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.1970827117 Jun 24 08:09:55 PM PDT 24 Jun 24 08:54:21 PM PDT 24 13310029655 ps
T1224 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.2154404112 Jun 24 08:04:24 PM PDT 24 Jun 24 08:08:34 PM PDT 24 2351602706 ps
T1225 /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.410321911 Jun 24 08:27:17 PM PDT 24 Jun 24 08:35:40 PM PDT 24 4930219800 ps
T1226 /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.1300138852 Jun 24 08:36:31 PM PDT 24 Jun 24 08:48:47 PM PDT 24 11225369195 ps
T1227 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.680256589 Jun 24 08:31:29 PM PDT 24 Jun 24 08:40:30 PM PDT 24 4170015276 ps
T1228 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3497871285 Jun 24 08:03:30 PM PDT 24 Jun 24 08:58:14 PM PDT 24 29205092411 ps
T1229 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.1867631935 Jun 24 08:06:44 PM PDT 24 Jun 24 08:15:26 PM PDT 24 4418590708 ps
T1230 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.807030044 Jun 24 08:31:25 PM PDT 24 Jun 24 08:41:13 PM PDT 24 4661736934 ps
T1231 /workspace/coverage/default/0.chip_sw_kmac_smoketest.239643557 Jun 24 08:08:56 PM PDT 24 Jun 24 08:13:04 PM PDT 24 2595035736 ps
T407 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.367834094 Jun 24 08:18:06 PM PDT 24 Jun 24 08:51:09 PM PDT 24 23632083340 ps
T1232 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.1990888586 Jun 24 08:04:26 PM PDT 24 Jun 24 08:15:02 PM PDT 24 4698530159 ps
T1233 /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1790527751 Jun 24 08:40:26 PM PDT 24 Jun 24 08:46:00 PM PDT 24 3312627496 ps
T399 /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.783825026 Jun 24 08:10:12 PM PDT 24 Jun 24 08:14:16 PM PDT 24 2814628605 ps
T1234 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.512990990 Jun 24 08:12:27 PM PDT 24 Jun 24 09:25:26 PM PDT 24 25781656407 ps
T51 /workspace/coverage/default/2.chip_sw_spi_device_tpm.952855165 Jun 24 08:23:24 PM PDT 24 Jun 24 08:31:22 PM PDT 24 3521776390 ps
T1235 /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.876355977 Jun 24 08:10:51 PM PDT 24 Jun 24 08:16:01 PM PDT 24 5113048568 ps
T1236 /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.3972177780 Jun 24 08:22:40 PM PDT 24 Jun 24 08:42:05 PM PDT 24 8182184679 ps
T625 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.661592048 Jun 24 08:02:42 PM PDT 24 Jun 24 08:08:02 PM PDT 24 3577735300 ps
T1237 /workspace/coverage/default/90.chip_sw_all_escalation_resets.539616287 Jun 24 08:42:28 PM PDT 24 Jun 24 08:54:10 PM PDT 24 5038889752 ps
T388 /workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.306969630 Jun 24 08:08:36 PM PDT 24 Jun 24 08:12:24 PM PDT 24 2717704392 ps
T413 /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.1733768935 Jun 24 08:18:00 PM PDT 24 Jun 24 08:24:15 PM PDT 24 4237870070 ps
T1238 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1127438662 Jun 24 08:13:16 PM PDT 24 Jun 24 08:29:47 PM PDT 24 7875545381 ps
T694 /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.1549012976 Jun 24 08:37:10 PM PDT 24 Jun 24 08:43:26 PM PDT 24 3824689318 ps
T1239 /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.1735959235 Jun 24 08:36:45 PM PDT 24 Jun 24 08:45:05 PM PDT 24 4005703768 ps
T1240 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3715242360 Jun 24 08:16:36 PM PDT 24 Jun 24 08:26:09 PM PDT 24 4183631880 ps
T1241 /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.3063221564 Jun 24 08:36:33 PM PDT 24 Jun 24 08:49:16 PM PDT 24 4949440840 ps
T175 /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.699406972 Jun 24 08:03:03 PM PDT 24 Jun 24 09:25:15 PM PDT 24 43375334974 ps
T1242 /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.2932074302 Jun 24 08:23:16 PM PDT 24 Jun 24 08:41:57 PM PDT 24 5479915946 ps
T734 /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.3689588290 Jun 24 08:36:41 PM PDT 24 Jun 24 08:42:43 PM PDT 24 4240734552 ps
T1243 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.2194684578 Jun 24 08:11:39 PM PDT 24 Jun 24 08:21:40 PM PDT 24 4075184750 ps
T1244 /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.556382699 Jun 24 08:04:08 PM PDT 24 Jun 24 08:56:54 PM PDT 24 13178662296 ps
T696 /workspace/coverage/default/6.chip_sw_all_escalation_resets.632796526 Jun 24 08:38:10 PM PDT 24 Jun 24 08:47:15 PM PDT 24 4729429622 ps
T1245 /workspace/coverage/default/2.chip_sw_gpio_smoketest.2792601363 Jun 24 08:29:43 PM PDT 24 Jun 24 08:34:32 PM PDT 24 2929475805 ps
T1246 /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.2314338121 Jun 24 08:39:01 PM PDT 24 Jun 24 08:44:37 PM PDT 24 3337835272 ps
T1247 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.2740986794 Jun 24 08:11:48 PM PDT 24 Jun 24 10:07:15 PM PDT 24 23651716622 ps
T1248 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.4256034790 Jun 24 08:18:41 PM PDT 24 Jun 24 09:26:33 PM PDT 24 14772167860 ps
T1249 /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.756764405 Jun 24 08:36:13 PM PDT 24 Jun 24 08:50:09 PM PDT 24 9522124899 ps
T739 /workspace/coverage/default/3.chip_sw_all_escalation_resets.3198156419 Jun 24 08:31:26 PM PDT 24 Jun 24 08:42:10 PM PDT 24 4596714116 ps
T318 /workspace/coverage/default/2.chip_sw_entropy_src_csrng.2429895407 Jun 24 08:25:03 PM PDT 24 Jun 24 08:52:02 PM PDT 24 7724152100 ps
T1250 /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1346186805 Jun 24 08:33:04 PM PDT 24 Jun 24 08:42:52 PM PDT 24 7179783174 ps
T1251 /workspace/coverage/default/0.chip_sw_hmac_enc.377432379 Jun 24 08:05:04 PM PDT 24 Jun 24 08:10:41 PM PDT 24 2680372048 ps
T697 /workspace/coverage/default/16.chip_sw_all_escalation_resets.3958394710 Jun 24 08:36:30 PM PDT 24 Jun 24 08:47:09 PM PDT 24 5771817960 ps
T1252 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.1403133606 Jun 24 08:34:35 PM PDT 24 Jun 24 09:34:41 PM PDT 24 15227783750 ps
T52 /workspace/coverage/default/1.chip_sw_spi_device_tpm.1462990968 Jun 24 08:09:43 PM PDT 24 Jun 24 08:14:47 PM PDT 24 3365916795 ps
T626 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.3375168243 Jun 24 08:10:08 PM PDT 24 Jun 24 08:14:09 PM PDT 24 3356604534 ps
T1253 /workspace/coverage/default/2.chip_sw_clkmgr_jitter.3082823593 Jun 24 08:28:02 PM PDT 24 Jun 24 08:32:22 PM PDT 24 2726838558 ps
T1254 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.804965431 Jun 24 08:16:52 PM PDT 24 Jun 24 08:56:27 PM PDT 24 11570736504 ps
T1255 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.4172306317 Jun 24 08:08:08 PM PDT 24 Jun 24 08:12:14 PM PDT 24 3158298099 ps
T1256 /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.2824265995 Jun 24 08:11:40 PM PDT 24 Jun 24 08:20:48 PM PDT 24 3761477852 ps
T1257 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.2940675898 Jun 24 08:29:02 PM PDT 24 Jun 24 08:33:29 PM PDT 24 3123054578 ps
T1258 /workspace/coverage/default/0.chip_sival_flash_info_access.4284049120 Jun 24 08:04:24 PM PDT 24 Jun 24 08:10:19 PM PDT 24 2836159372 ps
T65 /workspace/coverage/default/4.chip_tap_straps_rma.1315406356 Jun 24 08:34:40 PM PDT 24 Jun 24 08:41:46 PM PDT 24 4395272021 ps
T1259 /workspace/coverage/default/1.chip_sw_edn_auto_mode.875173771 Jun 24 08:14:18 PM PDT 24 Jun 24 08:30:59 PM PDT 24 4231516882 ps
T288 /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.3353109219 Jun 24 08:25:34 PM PDT 24 Jun 24 08:44:07 PM PDT 24 9719073934 ps
T1260 /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.811821123 Jun 24 08:20:37 PM PDT 24 Jun 24 08:24:53 PM PDT 24 2945521730 ps
T1261 /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.1996370307 Jun 24 08:36:57 PM PDT 24 Jun 24 08:44:35 PM PDT 24 4002538744 ps
T1262 /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.3370787123 Jun 24 08:21:55 PM PDT 24 Jun 24 08:26:06 PM PDT 24 3390208760 ps
T1263 /workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.1272030430 Jun 24 08:27:29 PM PDT 24 Jun 24 08:32:16 PM PDT 24 2914208465 ps
T1264 /workspace/coverage/default/1.chip_sw_kmac_idle.1478695579 Jun 24 08:15:12 PM PDT 24 Jun 24 08:18:22 PM PDT 24 2348738256 ps
T1265 /workspace/coverage/default/2.chip_sival_flash_info_access.1312684991 Jun 24 08:21:39 PM PDT 24 Jun 24 08:26:48 PM PDT 24 2608513946 ps
T1266 /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.1948072405 Jun 24 08:16:11 PM PDT 24 Jun 24 08:23:33 PM PDT 24 4463634952 ps
T698 /workspace/coverage/default/59.chip_sw_all_escalation_resets.381349198 Jun 24 08:39:36 PM PDT 24 Jun 24 08:48:17 PM PDT 24 5440570718 ps
T160 /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.846398081 Jun 24 08:04:42 PM PDT 24 Jun 24 08:06:35 PM PDT 24 2379562601 ps
T1267 /workspace/coverage/default/1.rom_volatile_raw_unlock.2174157010 Jun 24 08:22:42 PM PDT 24 Jun 24 08:24:27 PM PDT 24 2431300309 ps
T1268 /workspace/coverage/default/0.chip_sw_usbdev_stream.1257271243 Jun 24 08:04:03 PM PDT 24 Jun 24 09:20:42 PM PDT 24 18730116340 ps
T1269 /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.1876539922 Jun 24 08:05:26 PM PDT 24 Jun 24 08:28:28 PM PDT 24 9406165306 ps
T681 /workspace/coverage/default/53.chip_sw_all_escalation_resets.3601140621 Jun 24 08:38:49 PM PDT 24 Jun 24 08:50:10 PM PDT 24 6169135044 ps
T1270 /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.686851054 Jun 24 08:22:52 PM PDT 24 Jun 24 08:27:13 PM PDT 24 2565733288 ps
T727 /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.2869021832 Jun 24 08:36:17 PM PDT 24 Jun 24 08:44:28 PM PDT 24 3507166080 ps
T1271 /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.2893913702 Jun 24 08:08:29 PM PDT 24 Jun 24 08:20:01 PM PDT 24 4777210568 ps
T1272 /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.4044714877 Jun 24 08:36:06 PM PDT 24 Jun 24 08:53:30 PM PDT 24 11039687311 ps
T222 /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.3352588407 Jun 24 08:29:57 PM PDT 24 Jun 24 09:18:04 PM PDT 24 12566488312 ps
T1273 /workspace/coverage/default/0.chip_sw_hmac_smoketest.1354806820 Jun 24 08:08:15 PM PDT 24 Jun 24 08:14:11 PM PDT 24 3753764864 ps
T1274 /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.190876560 Jun 24 08:10:14 PM PDT 24 Jun 24 08:17:21 PM PDT 24 5080175628 ps
T316 /workspace/coverage/default/1.chip_plic_all_irqs_0.3120381617 Jun 24 08:16:01 PM PDT 24 Jun 24 08:33:59 PM PDT 24 5502586540 ps
T1275 /workspace/coverage/default/2.chip_sw_hmac_enc_idle.3656614447 Jun 24 08:26:28 PM PDT 24 Jun 24 08:32:36 PM PDT 24 3010279778 ps
T1276 /workspace/coverage/default/0.chip_sw_alert_handler_entropy.1198162363 Jun 24 08:06:10 PM PDT 24 Jun 24 08:10:30 PM PDT 24 2985278504 ps
T377 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.2110048271 Jun 24 08:22:51 PM PDT 24 Jun 24 08:33:15 PM PDT 24 4727712400 ps
T1277 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.2786465955 Jun 24 08:17:15 PM PDT 24 Jun 24 08:29:41 PM PDT 24 6676310000 ps
T1278 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.3081658472 Jun 24 08:25:18 PM PDT 24 Jun 24 08:30:29 PM PDT 24 2628788066 ps
T1279 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.1746365750 Jun 24 08:07:20 PM PDT 24 Jun 24 08:12:08 PM PDT 24 3085718020 ps
T1280 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.3790053790 Jun 24 08:24:58 PM PDT 24 Jun 24 08:53:09 PM PDT 24 24803645270 ps
T255 /workspace/coverage/default/2.chip_sw_data_integrity_escalation.2819392829 Jun 24 08:21:38 PM PDT 24 Jun 24 08:34:19 PM PDT 24 5715070930 ps
T328 /workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.3002769423 Jun 24 08:29:46 PM PDT 24 Jun 24 08:36:27 PM PDT 24 3663324590 ps
T1281 /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.915562164 Jun 24 08:24:54 PM PDT 24 Jun 24 09:16:38 PM PDT 24 11441945085 ps
T1282 /workspace/coverage/default/0.chip_sw_data_integrity_escalation.699882241 Jun 24 08:03:19 PM PDT 24 Jun 24 08:12:31 PM PDT 24 4937663264 ps
T1283 /workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.1442275221 Jun 24 08:11:39 PM PDT 24 Jun 24 08:16:18 PM PDT 24 3628074679 ps
T1284 /workspace/coverage/default/1.chip_sw_hmac_oneshot.297791077 Jun 24 08:14:46 PM PDT 24 Jun 24 08:21:01 PM PDT 24 3505376096 ps
T1285 /workspace/coverage/default/2.rom_e2e_static_critical.250461585 Jun 24 08:34:48 PM PDT 24 Jun 24 09:30:30 PM PDT 24 17347649528 ps
T748 /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3327737741 Jun 24 08:41:00 PM PDT 24 Jun 24 08:46:24 PM PDT 24 3501228930 ps
T1286 /workspace/coverage/default/35.chip_sw_all_escalation_resets.3819593714 Jun 24 08:37:14 PM PDT 24 Jun 24 08:47:31 PM PDT 24 6243110600 ps
T654 /workspace/coverage/default/94.chip_sw_all_escalation_resets.3685297829 Jun 24 08:43:00 PM PDT 24 Jun 24 08:53:55 PM PDT 24 5303483240 ps
T1287 /workspace/coverage/default/2.chip_sw_edn_auto_mode.69854872 Jun 24 08:26:15 PM PDT 24 Jun 24 08:44:50 PM PDT 24 4769430648 ps
T134 /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.2095694825 Jun 24 08:33:13 PM PDT 24 Jun 24 08:47:21 PM PDT 24 7622464856 ps
T68 /workspace/coverage/cover_reg_top/37.xbar_smoke_zero_delays.1507757947 Jun 24 07:44:28 PM PDT 24 Jun 24 07:44:42 PM PDT 24 45800651 ps
T69 /workspace/coverage/cover_reg_top/99.xbar_access_same_device.1062368055 Jun 24 07:55:21 PM PDT 24 Jun 24 07:56:45 PM PDT 24 1831883066 ps
T70 /workspace/coverage/cover_reg_top/92.xbar_smoke_slow_rsp.878340812 Jun 24 07:54:03 PM PDT 24 Jun 24 07:54:59 PM PDT 24 3290665743 ps
T73 /workspace/coverage/cover_reg_top/32.xbar_random_slow_rsp.1462244634 Jun 24 07:42:49 PM PDT 24 Jun 24 07:46:23 PM PDT 24 13089168131 ps
T122 /workspace/coverage/cover_reg_top/82.xbar_smoke_zero_delays.2458278171 Jun 24 07:52:22 PM PDT 24 Jun 24 07:52:31 PM PDT 24 50695653 ps
T74 /workspace/coverage/cover_reg_top/19.xbar_access_same_device.4199887866 Jun 24 07:40:31 PM PDT 24 Jun 24 07:42:29 PM PDT 24 3053214018 ps
T146 /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.2869561148 Jun 24 07:40:15 PM PDT 24 Jun 24 07:45:41 PM PDT 24 898271689 ps
T147 /workspace/coverage/cover_reg_top/8.chip_tl_errors.4227751390 Jun 24 07:37:37 PM PDT 24 Jun 24 07:44:30 PM PDT 24 4734908664 ps
T379 /workspace/coverage/cover_reg_top/14.xbar_random_large_delays.566578827 Jun 24 07:39:22 PM PDT 24 Jun 24 07:50:20 PM PDT 24 63429514848 ps
T823 /workspace/coverage/cover_reg_top/2.chip_prim_tl_access.1257402628 Jun 24 07:36:35 PM PDT 24 Jun 24 07:43:30 PM PDT 24 8943572714 ps
T237 /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_error.2377622168 Jun 24 07:47:41 PM PDT 24 Jun 24 07:50:16 PM PDT 24 1885844697 ps
T425 /workspace/coverage/cover_reg_top/26.xbar_error_random.1601984844 Jun 24 07:42:11 PM PDT 24 Jun 24 07:43:23 PM PDT 24 1951313038 ps
T566 /workspace/coverage/cover_reg_top/4.xbar_smoke_large_delays.407424775 Jun 24 07:37:08 PM PDT 24 Jun 24 07:38:47 PM PDT 24 9465367306 ps
T515 /workspace/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.72377272 Jun 24 07:50:06 PM PDT 24 Jun 24 08:24:58 PM PDT 24 114794827693 ps
T516 /workspace/coverage/cover_reg_top/79.xbar_smoke_large_delays.2462677644 Jun 24 07:51:37 PM PDT 24 Jun 24 07:53:13 PM PDT 24 9376935538 ps
T623 /workspace/coverage/cover_reg_top/16.xbar_access_same_device.2537932917 Jun 24 07:39:24 PM PDT 24 Jun 24 07:39:57 PM PDT 24 439436200 ps
T512 /workspace/coverage/cover_reg_top/15.xbar_same_source.1591883994 Jun 24 07:41:09 PM PDT 24 Jun 24 07:41:51 PM PDT 24 569605746 ps
T426 /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_error.3778743425 Jun 24 07:40:41 PM PDT 24 Jun 24 07:43:11 PM PDT 24 4406398194 ps
T517 /workspace/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.1364183210 Jun 24 07:49:05 PM PDT 24 Jun 24 07:50:21 PM PDT 24 4415706796 ps
T513 /workspace/coverage/cover_reg_top/97.xbar_error_and_unmapped_addr.404395111 Jun 24 07:55:22 PM PDT 24 Jun 24 07:55:57 PM PDT 24 283790438 ps
T410 /workspace/coverage/cover_reg_top/82.xbar_random_zero_delays.380274126 Jun 24 07:52:21 PM PDT 24 Jun 24 07:52:43 PM PDT 24 219459850 ps
T511 /workspace/coverage/cover_reg_top/88.xbar_random_slow_rsp.2071394686 Jun 24 07:53:26 PM PDT 24 Jun 24 08:09:50 PM PDT 24 49633365458 ps
T1288 /workspace/coverage/cover_reg_top/93.xbar_smoke_zero_delays.1274934305 Jun 24 07:54:09 PM PDT 24 Jun 24 07:54:16 PM PDT 24 49804750 ps
T514 /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.3540751652 Jun 24 07:44:22 PM PDT 24 Jun 24 07:49:54 PM PDT 24 6731778259 ps
T1289 /workspace/coverage/cover_reg_top/73.xbar_smoke_large_delays.911456123 Jun 24 07:50:44 PM PDT 24 Jun 24 07:52:04 PM PDT 24 7384415223 ps
T510 /workspace/coverage/cover_reg_top/25.chip_tl_errors.2926062663 Jun 24 07:41:35 PM PDT 24 Jun 24 07:47:30 PM PDT 24 3924961970 ps
T506 /workspace/coverage/cover_reg_top/87.xbar_random_large_delays.2752636499 Jun 24 07:53:07 PM PDT 24 Jun 24 08:07:24 PM PDT 24 77405632611 ps
T788 /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.1074049571 Jun 24 07:38:32 PM PDT 24 Jun 24 07:39:36 PM PDT 24 257682897 ps
T590 /workspace/coverage/cover_reg_top/48.xbar_smoke.3569027220 Jun 24 07:45:45 PM PDT 24 Jun 24 07:45:59 PM PDT 24 277324159 ps
T404 /workspace/coverage/cover_reg_top/88.xbar_stress_all.2237065999 Jun 24 07:53:19 PM PDT 24 Jun 24 07:55:34 PM PDT 24 1630675636 ps
T757 /workspace/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.978886136 Jun 24 07:44:24 PM PDT 24 Jun 24 07:53:14 PM PDT 24 32149984917 ps
T1290 /workspace/coverage/cover_reg_top/16.xbar_smoke_zero_delays.1512437743 Jun 24 07:39:29 PM PDT 24 Jun 24 07:39:36 PM PDT 24 46932458 ps
T455 /workspace/coverage/cover_reg_top/85.xbar_random.3962484851 Jun 24 07:53:02 PM PDT 24 Jun 24 07:53:45 PM PDT 24 469386079 ps
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