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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.10 95.39 93.96 95.30 94.85 97.53 99.55


Total test records in report: 2866
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T980 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.3616457443 Jun 24 08:14:32 PM PDT 24 Jun 24 08:51:47 PM PDT 24 9278239720 ps
T981 /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.875098090 Jun 24 08:06:59 PM PDT 24 Jun 24 08:50:19 PM PDT 24 11412504524 ps
T362 /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.1614041777 Jun 24 08:42:25 PM PDT 24 Jun 24 08:48:25 PM PDT 24 3377947956 ps
T982 /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.711889830 Jun 24 08:08:28 PM PDT 24 Jun 24 08:12:45 PM PDT 24 2883476268 ps
T983 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.793443286 Jun 24 08:17:57 PM PDT 24 Jun 24 08:29:31 PM PDT 24 4726580848 ps
T984 /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.4256616955 Jun 24 08:23:47 PM PDT 24 Jun 24 08:33:14 PM PDT 24 3802300960 ps
T711 /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3601973797 Jun 24 08:39:57 PM PDT 24 Jun 24 08:47:16 PM PDT 24 3736694112 ps
T985 /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.2622723166 Jun 24 08:36:42 PM PDT 24 Jun 24 09:33:57 PM PDT 24 17467842400 ps
T703 /workspace/coverage/default/26.chip_sw_all_escalation_resets.2449132158 Jun 24 08:36:57 PM PDT 24 Jun 24 08:48:10 PM PDT 24 6108867080 ps
T986 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3436989377 Jun 24 08:23:35 PM PDT 24 Jun 24 08:29:31 PM PDT 24 6533905648 ps
T712 /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.1128200999 Jun 24 08:37:43 PM PDT 24 Jun 24 08:44:27 PM PDT 24 3107049828 ps
T22 /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2487673127 Jun 24 08:02:27 PM PDT 24 Jun 24 08:06:56 PM PDT 24 2696559541 ps
T336 /workspace/coverage/default/0.chip_sw_pattgen_ios.2916534085 Jun 24 08:03:55 PM PDT 24 Jun 24 08:08:29 PM PDT 24 3102969256 ps
T987 /workspace/coverage/default/1.chip_sw_edn_sw_mode.1095563221 Jun 24 08:13:38 PM PDT 24 Jun 24 08:35:45 PM PDT 24 6526185478 ps
T611 /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.2264977874 Jun 24 08:03:54 PM PDT 24 Jun 24 08:12:11 PM PDT 24 6034703154 ps
T988 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3430156340 Jun 24 08:22:14 PM PDT 24 Jun 24 08:33:58 PM PDT 24 4442431000 ps
T989 /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.2455372882 Jun 24 08:11:29 PM PDT 24 Jun 24 08:52:52 PM PDT 24 32113944240 ps
T36 /workspace/coverage/default/0.chip_sw_usbdev_setuprx.4216928678 Jun 24 08:03:32 PM PDT 24 Jun 24 08:13:54 PM PDT 24 3520208000 ps
T990 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3103708084 Jun 24 08:18:33 PM PDT 24 Jun 24 08:23:12 PM PDT 24 3693571366 ps
T11 /workspace/coverage/default/0.chip_sw_sleep_pin_wake.1592962108 Jun 24 08:04:16 PM PDT 24 Jun 24 08:07:59 PM PDT 24 3621889450 ps
T265 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1582254991 Jun 24 08:29:43 PM PDT 24 Jun 24 08:38:31 PM PDT 24 4493135270 ps
T991 /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.3206044084 Jun 24 08:16:53 PM PDT 24 Jun 24 08:33:26 PM PDT 24 9814763240 ps
T992 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.3587781875 Jun 24 08:22:53 PM PDT 24 Jun 24 08:44:39 PM PDT 24 7110113772 ps
T360 /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3028967329 Jun 24 08:24:05 PM PDT 24 Jun 24 11:35:34 PM PDT 24 254351308968 ps
T246 /workspace/coverage/default/13.chip_sw_all_escalation_resets.3920801680 Jun 24 08:37:23 PM PDT 24 Jun 24 08:48:51 PM PDT 24 5144130952 ps
T732 /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.2875761657 Jun 24 08:36:46 PM PDT 24 Jun 24 08:43:26 PM PDT 24 3336801964 ps
T993 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.185289502 Jun 24 08:18:22 PM PDT 24 Jun 24 08:28:12 PM PDT 24 5726897174 ps
T606 /workspace/coverage/default/2.chip_sw_edn_boot_mode.442112382 Jun 24 08:25:13 PM PDT 24 Jun 24 08:35:23 PM PDT 24 3196760552 ps
T994 /workspace/coverage/default/0.chip_sw_aes_idle.2354019027 Jun 24 08:08:15 PM PDT 24 Jun 24 08:12:05 PM PDT 24 2344130440 ps
T995 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.933226688 Jun 24 08:10:51 PM PDT 24 Jun 24 08:37:17 PM PDT 24 12653218203 ps
T996 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.2649599652 Jun 24 08:26:00 PM PDT 24 Jun 24 09:31:15 PM PDT 24 15750767956 ps
T997 /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.3182402996 Jun 24 08:11:35 PM PDT 24 Jun 24 08:46:44 PM PDT 24 23130213018 ps
T678 /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.1177276630 Jun 24 08:39:20 PM PDT 24 Jun 24 08:46:06 PM PDT 24 3640768248 ps
T998 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.1957820906 Jun 24 08:18:17 PM PDT 24 Jun 24 09:15:32 PM PDT 24 11830654992 ps
T16 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.2954484163 Jun 24 08:27:36 PM PDT 24 Jun 24 08:47:40 PM PDT 24 21588463386 ps
T615 /workspace/coverage/default/0.rom_volatile_raw_unlock.781439554 Jun 24 08:08:41 PM PDT 24 Jun 24 08:10:29 PM PDT 24 1926095052 ps
T752 /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.1497246039 Jun 24 08:40:34 PM PDT 24 Jun 24 08:48:23 PM PDT 24 3484160040 ps
T999 /workspace/coverage/default/1.chip_sw_example_manufacturer.3183001898 Jun 24 08:10:36 PM PDT 24 Jun 24 08:14:35 PM PDT 24 3264535028 ps
T719 /workspace/coverage/default/20.chip_sw_all_escalation_resets.3966286318 Jun 24 08:35:20 PM PDT 24 Jun 24 08:47:51 PM PDT 24 5098467800 ps
T1000 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.4272727259 Jun 24 08:11:12 PM PDT 24 Jun 24 08:21:30 PM PDT 24 8429607964 ps
T713 /workspace/coverage/default/98.chip_sw_all_escalation_resets.2976914020 Jun 24 08:41:48 PM PDT 24 Jun 24 08:52:57 PM PDT 24 6180982064 ps
T1001 /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.3147379508 Jun 24 08:35:42 PM PDT 24 Jun 24 08:42:47 PM PDT 24 5557381050 ps
T315 /workspace/coverage/default/1.chip_plic_all_irqs_20.371264906 Jun 24 08:16:14 PM PDT 24 Jun 24 08:28:06 PM PDT 24 5075111312 ps
T1002 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3514781499 Jun 24 08:10:00 PM PDT 24 Jun 24 08:22:01 PM PDT 24 4775654864 ps
T239 /workspace/coverage/default/0.chip_sw_plic_sw_irq.1260668892 Jun 24 08:07:16 PM PDT 24 Jun 24 08:11:39 PM PDT 24 2387455024 ps
T1003 /workspace/coverage/default/0.chip_sw_example_flash.4064705143 Jun 24 08:02:28 PM PDT 24 Jun 24 08:06:09 PM PDT 24 3083171288 ps
T136 /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.1327295389 Jun 24 08:26:52 PM PDT 24 Jun 24 08:30:22 PM PDT 24 3476599358 ps
T1004 /workspace/coverage/default/2.chip_sw_edn_kat.1053537310 Jun 24 08:24:59 PM PDT 24 Jun 24 08:37:43 PM PDT 24 2906643548 ps
T1005 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.2282733996 Jun 24 08:23:25 PM PDT 24 Jun 24 08:36:03 PM PDT 24 6531582428 ps
T290 /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3445186230 Jun 24 08:10:03 PM PDT 24 Jun 24 08:18:03 PM PDT 24 5422558000 ps
T612 /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.1301308614 Jun 24 08:28:41 PM PDT 24 Jun 24 08:37:04 PM PDT 24 4637752210 ps
T1006 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.3022807787 Jun 24 08:10:25 PM PDT 24 Jun 24 08:23:48 PM PDT 24 4780716720 ps
T1007 /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.3060177793 Jun 24 08:21:49 PM PDT 24 Jun 24 08:28:25 PM PDT 24 3504871302 ps
T1008 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.4099407614 Jun 24 08:18:10 PM PDT 24 Jun 24 09:11:45 PM PDT 24 24903356176 ps
T729 /workspace/coverage/default/44.chip_sw_all_escalation_resets.3831778811 Jun 24 08:37:53 PM PDT 24 Jun 24 08:49:03 PM PDT 24 6223733040 ps
T137 /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.2184660537 Jun 24 08:12:46 PM PDT 24 Jun 24 08:24:03 PM PDT 24 7402485624 ps
T1009 /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.2497725971 Jun 24 08:19:00 PM PDT 24 Jun 24 08:31:25 PM PDT 24 4034902946 ps
T320 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.3097757860 Jun 24 08:10:12 PM PDT 24 Jun 24 08:23:15 PM PDT 24 5282653240 ps
T692 /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.2726822694 Jun 24 08:40:59 PM PDT 24 Jun 24 08:49:09 PM PDT 24 4370804040 ps
T1010 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.260246754 Jun 24 08:06:27 PM PDT 24 Jun 24 08:35:47 PM PDT 24 7855662762 ps
T266 /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.2154733955 Jun 24 08:14:10 PM PDT 24 Jun 24 08:24:22 PM PDT 24 3488292280 ps
T1011 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.1419336231 Jun 24 08:35:19 PM PDT 24 Jun 24 09:43:14 PM PDT 24 14910100730 ps
T1012 /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.4170105041 Jun 24 08:18:39 PM PDT 24 Jun 24 08:53:46 PM PDT 24 27397869190 ps
T693 /workspace/coverage/default/79.chip_sw_all_escalation_resets.1142309139 Jun 24 08:41:29 PM PDT 24 Jun 24 08:50:41 PM PDT 24 5385594568 ps
T1013 /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.4123655293 Jun 24 08:39:26 PM PDT 24 Jun 24 08:46:06 PM PDT 24 3937929512 ps
T1014 /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.3615193670 Jun 24 08:36:17 PM PDT 24 Jun 24 08:47:12 PM PDT 24 4347111446 ps
T1015 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.1170058739 Jun 24 08:06:06 PM PDT 24 Jun 24 08:18:09 PM PDT 24 8600142830 ps
T1016 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.207161063 Jun 24 08:18:38 PM PDT 24 Jun 24 09:38:20 PM PDT 24 16328106428 ps
T1017 /workspace/coverage/default/2.chip_sw_otbn_smoketest.4191891480 Jun 24 08:30:22 PM PDT 24 Jun 24 08:55:39 PM PDT 24 6902761976 ps
T1018 /workspace/coverage/default/2.chip_sw_example_flash.3379696303 Jun 24 08:22:25 PM PDT 24 Jun 24 08:25:42 PM PDT 24 2641171304 ps
T1019 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.3947194281 Jun 24 08:02:36 PM PDT 24 Jun 24 08:18:29 PM PDT 24 5625813992 ps
T1020 /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.2437468953 Jun 24 08:26:36 PM PDT 24 Jun 24 08:36:37 PM PDT 24 5141997112 ps
T1021 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.1570207684 Jun 24 08:13:58 PM PDT 24 Jun 24 08:48:01 PM PDT 24 9583199800 ps
T1022 /workspace/coverage/default/0.chip_sw_hmac_enc_idle.298030588 Jun 24 08:05:24 PM PDT 24 Jun 24 08:11:58 PM PDT 24 3049824696 ps
T1023 /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.2195063986 Jun 24 08:21:59 PM PDT 24 Jun 24 09:02:51 PM PDT 24 13280047288 ps
T1024 /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.3697317809 Jun 24 08:32:33 PM PDT 24 Jun 24 08:44:49 PM PDT 24 4310126898 ps
T1025 /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.1957527685 Jun 24 08:13:55 PM PDT 24 Jun 24 08:50:18 PM PDT 24 12310955568 ps
T718 /workspace/coverage/default/43.chip_sw_all_escalation_resets.3367323102 Jun 24 08:38:35 PM PDT 24 Jun 24 08:48:10 PM PDT 24 4276051744 ps
T616 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.4127426684 Jun 24 08:22:57 PM PDT 24 Jun 24 08:24:56 PM PDT 24 2386260139 ps
T1026 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.3921478513 Jun 24 08:05:04 PM PDT 24 Jun 24 09:08:20 PM PDT 24 19126309013 ps
T1027 /workspace/coverage/default/0.chip_sw_clkmgr_jitter.3403679422 Jun 24 08:06:32 PM PDT 24 Jun 24 08:09:25 PM PDT 24 2717965229 ps
T714 /workspace/coverage/default/33.chip_sw_all_escalation_resets.4018779659 Jun 24 08:36:45 PM PDT 24 Jun 24 08:46:09 PM PDT 24 5929248720 ps
T1028 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.197945148 Jun 24 08:06:03 PM PDT 24 Jun 24 08:17:48 PM PDT 24 6822511560 ps
T1029 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.4238562438 Jun 24 08:16:21 PM PDT 24 Jun 24 08:25:45 PM PDT 24 3875342000 ps
T1030 /workspace/coverage/default/0.chip_sw_hmac_oneshot.1674158095 Jun 24 08:05:47 PM PDT 24 Jun 24 08:11:04 PM PDT 24 3739960348 ps
T1031 /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.645569137 Jun 24 08:26:17 PM PDT 24 Jun 24 09:14:29 PM PDT 24 23446365418 ps
T152 /workspace/coverage/default/2.chip_plic_all_irqs_10.1484068214 Jun 24 08:26:51 PM PDT 24 Jun 24 08:36:32 PM PDT 24 3484810408 ps
T321 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.3133920319 Jun 24 08:24:34 PM PDT 24 Jun 24 08:40:17 PM PDT 24 5260934764 ps
T1032 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.1449470576 Jun 24 08:02:12 PM PDT 24 Jun 24 08:13:43 PM PDT 24 4512145400 ps
T624 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.3535483825 Jun 24 08:24:43 PM PDT 24 Jun 24 08:29:46 PM PDT 24 3476163126 ps
T149 /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.2961892685 Jun 24 08:12:02 PM PDT 24 Jun 24 11:15:19 PM PDT 24 57965266812 ps
T1033 /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.3776095757 Jun 24 08:23:57 PM PDT 24 Jun 24 08:37:49 PM PDT 24 4970335800 ps
T1034 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.3382521503 Jun 24 08:25:25 PM PDT 24 Jun 24 09:00:36 PM PDT 24 12693264940 ps
T1035 /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.3295267626 Jun 24 08:09:39 PM PDT 24 Jun 24 08:45:49 PM PDT 24 22116791491 ps
T1036 /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.3684019018 Jun 24 08:37:04 PM PDT 24 Jun 24 08:45:36 PM PDT 24 4085840500 ps
T23 /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3544179815 Jun 24 08:22:58 PM PDT 24 Jun 24 08:27:03 PM PDT 24 2902873796 ps
T1037 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1446102205 Jun 24 08:15:28 PM PDT 24 Jun 24 09:17:43 PM PDT 24 15663894304 ps
T198 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.1045321103 Jun 24 08:12:51 PM PDT 24 Jun 24 08:18:09 PM PDT 24 2501028812 ps
T1038 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.3435727992 Jun 24 08:25:05 PM PDT 24 Jun 24 08:35:37 PM PDT 24 5638306620 ps
T1039 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.3006004208 Jun 24 08:10:20 PM PDT 24 Jun 24 09:18:44 PM PDT 24 15403590750 ps
T1040 /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.1973903178 Jun 24 08:36:06 PM PDT 24 Jun 24 08:58:53 PM PDT 24 10480921777 ps
T722 /workspace/coverage/default/4.chip_sw_all_escalation_resets.1327569180 Jun 24 08:32:25 PM PDT 24 Jun 24 08:42:56 PM PDT 24 4796567354 ps
T332 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2858042449 Jun 24 08:19:01 PM PDT 24 Jun 24 08:31:43 PM PDT 24 4703713139 ps
T39 /workspace/coverage/default/0.chip_sw_gpio_smoketest.2166164542 Jun 24 08:07:11 PM PDT 24 Jun 24 08:12:30 PM PDT 24 2582949983 ps
T267 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.254094468 Jun 24 08:07:08 PM PDT 24 Jun 24 08:14:13 PM PDT 24 4368817350 ps
T1041 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2392747174 Jun 24 08:31:30 PM PDT 24 Jun 24 08:43:22 PM PDT 24 4579143880 ps
T1042 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.1590726414 Jun 24 08:12:06 PM PDT 24 Jun 24 09:11:35 PM PDT 24 18209271900 ps
T173 /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.2836104570 Jun 24 08:28:19 PM PDT 24 Jun 24 08:32:54 PM PDT 24 2245355998 ps
T1043 /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.2108848876 Jun 24 08:11:23 PM PDT 24 Jun 24 08:30:05 PM PDT 24 6519403779 ps
T745 /workspace/coverage/default/17.chip_sw_all_escalation_resets.548253639 Jun 24 08:38:01 PM PDT 24 Jun 24 08:47:15 PM PDT 24 5377756960 ps
T1044 /workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.3340417833 Jun 24 08:24:55 PM PDT 24 Jun 24 08:45:55 PM PDT 24 8269247912 ps
T686 /workspace/coverage/default/97.chip_sw_all_escalation_resets.3685953848 Jun 24 08:40:50 PM PDT 24 Jun 24 08:51:24 PM PDT 24 5414780488 ps
T1045 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.754088011 Jun 24 08:04:37 PM PDT 24 Jun 24 08:11:06 PM PDT 24 3929498840 ps
T1046 /workspace/coverage/default/1.chip_sw_ast_clk_outputs.260084896 Jun 24 08:18:44 PM PDT 24 Jun 24 08:40:29 PM PDT 24 7089961100 ps
T103 /workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.3043170478 Jun 24 08:22:03 PM PDT 24 Jun 24 09:09:39 PM PDT 24 19661511135 ps
T1047 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.2661236061 Jun 24 08:28:36 PM PDT 24 Jun 24 08:35:43 PM PDT 24 3561882190 ps
T1048 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.311365797 Jun 24 08:19:23 PM PDT 24 Jun 24 08:43:14 PM PDT 24 7488492906 ps
T1049 /workspace/coverage/default/2.chip_sw_aes_enc.3585460097 Jun 24 08:24:38 PM PDT 24 Jun 24 08:29:26 PM PDT 24 2890721560 ps
T1050 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.2750722984 Jun 24 08:03:37 PM PDT 24 Jun 24 08:15:18 PM PDT 24 4744531408 ps
T1051 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.1075617728 Jun 24 08:22:03 PM PDT 24 Jun 24 08:34:08 PM PDT 24 4876375152 ps
T1052 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3404179949 Jun 24 08:04:18 PM PDT 24 Jun 24 08:18:31 PM PDT 24 3680944694 ps
T131 /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.3767651873 Jun 24 08:05:20 PM PDT 24 Jun 24 08:14:00 PM PDT 24 5532253918 ps
T1053 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1545592991 Jun 24 08:19:56 PM PDT 24 Jun 24 08:51:49 PM PDT 24 11655716990 ps
T1054 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.3888555857 Jun 24 08:23:47 PM PDT 24 Jun 24 08:33:30 PM PDT 24 3739641774 ps
T268 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.2464695923 Jun 24 08:15:49 PM PDT 24 Jun 24 08:27:55 PM PDT 24 5661594284 ps
T1055 /workspace/coverage/default/0.chip_sw_power_sleep_load.4070768646 Jun 24 08:07:17 PM PDT 24 Jun 24 08:20:42 PM PDT 24 10286076386 ps
T715 /workspace/coverage/default/87.chip_sw_all_escalation_resets.1526159987 Jun 24 08:40:56 PM PDT 24 Jun 24 08:53:04 PM PDT 24 5981395080 ps
T269 /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.394900297 Jun 24 08:04:48 PM PDT 24 Jun 24 08:15:46 PM PDT 24 3574160532 ps
T1056 /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.1372245494 Jun 24 08:06:10 PM PDT 24 Jun 24 08:12:30 PM PDT 24 3500209380 ps
T1057 /workspace/coverage/default/2.chip_sw_alert_handler_escalation.3642549486 Jun 24 08:24:24 PM PDT 24 Jun 24 08:33:47 PM PDT 24 4544571400 ps
T700 /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.2670519417 Jun 24 08:39:49 PM PDT 24 Jun 24 08:46:38 PM PDT 24 3871368860 ps
T1058 /workspace/coverage/default/0.chip_sw_example_rom.2590234516 Jun 24 08:01:24 PM PDT 24 Jun 24 08:03:19 PM PDT 24 3076175936 ps
T64 /workspace/coverage/default/1.chip_tap_straps_rma.2292517492 Jun 24 08:19:07 PM PDT 24 Jun 24 08:32:33 PM PDT 24 8197111716 ps
T1059 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.921331938 Jun 24 08:12:47 PM PDT 24 Jun 24 08:18:02 PM PDT 24 2879639899 ps
T1060 /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.3008805433 Jun 24 08:35:16 PM PDT 24 Jun 24 09:12:47 PM PDT 24 11285202839 ps
T1061 /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.3340948216 Jun 24 08:16:39 PM PDT 24 Jun 24 08:23:26 PM PDT 24 3133988064 ps
T1062 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.2933594834 Jun 24 08:04:47 PM PDT 24 Jun 24 08:18:45 PM PDT 24 7849401620 ps
T741 /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.2666116796 Jun 24 08:37:11 PM PDT 24 Jun 24 08:43:09 PM PDT 24 3721497730 ps
T1063 /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.3298443751 Jun 24 08:04:02 PM PDT 24 Jun 24 08:06:37 PM PDT 24 2532724670 ps
T1064 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.4074896962 Jun 24 08:23:26 PM PDT 24 Jun 24 08:41:44 PM PDT 24 6894000580 ps
T720 /workspace/coverage/default/96.chip_sw_all_escalation_resets.1344085714 Jun 24 08:41:21 PM PDT 24 Jun 24 08:50:38 PM PDT 24 4659848576 ps
T1065 /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1687775703 Jun 24 08:41:08 PM PDT 24 Jun 24 08:47:10 PM PDT 24 4044986008 ps
T1066 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.367295033 Jun 24 08:22:47 PM PDT 24 Jun 24 08:27:11 PM PDT 24 3299750870 ps
T1067 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.1044563230 Jun 24 08:15:50 PM PDT 24 Jun 24 08:26:07 PM PDT 24 6651772614 ps
T1068 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.676967624 Jun 24 08:04:40 PM PDT 24 Jun 24 08:35:58 PM PDT 24 15000894661 ps
T1069 /workspace/coverage/default/2.chip_sw_rv_timer_irq.822003466 Jun 24 08:24:17 PM PDT 24 Jun 24 08:28:17 PM PDT 24 3327652920 ps
T1070 /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.1927437765 Jun 24 08:30:51 PM PDT 24 Jun 24 08:38:28 PM PDT 24 2690866062 ps
T1071 /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.2480355529 Jun 24 08:22:40 PM PDT 24 Jun 24 08:27:45 PM PDT 24 3558238960 ps
T1072 /workspace/coverage/default/0.chip_tap_straps_prod.3375402417 Jun 24 08:05:36 PM PDT 24 Jun 24 08:08:52 PM PDT 24 3040468217 ps
T338 /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.1965776930 Jun 24 08:16:12 PM PDT 24 Jun 24 08:21:09 PM PDT 24 3243736540 ps
T37 /workspace/coverage/default/0.chip_sw_usbdev_config_host.3967664212 Jun 24 08:03:51 PM PDT 24 Jun 24 08:39:24 PM PDT 24 8247971316 ps
T385 /workspace/coverage/default/5.chip_sw_data_integrity_escalation.4280749446 Jun 24 08:35:40 PM PDT 24 Jun 24 08:45:35 PM PDT 24 6173916264 ps
T708 /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.4154229213 Jun 24 08:36:33 PM PDT 24 Jun 24 08:42:47 PM PDT 24 4122799264 ps
T660 /workspace/coverage/default/34.chip_sw_all_escalation_resets.708859660 Jun 24 08:38:20 PM PDT 24 Jun 24 08:53:29 PM PDT 24 5320171464 ps
T363 /workspace/coverage/default/76.chip_sw_all_escalation_resets.180485059 Jun 24 08:40:56 PM PDT 24 Jun 24 08:51:42 PM PDT 24 5128178110 ps
T1073 /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.416913974 Jun 24 08:03:52 PM PDT 24 Jun 24 08:23:34 PM PDT 24 6491576071 ps
T1074 /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.2920804705 Jun 24 08:05:17 PM PDT 24 Jun 24 08:08:40 PM PDT 24 2512505648 ps
T1075 /workspace/coverage/default/2.chip_sw_kmac_app_rom.3992252118 Jun 24 08:27:01 PM PDT 24 Jun 24 08:30:16 PM PDT 24 2788824960 ps
T1076 /workspace/coverage/default/0.chip_sw_flash_crash_alert.1507799494 Jun 24 08:08:52 PM PDT 24 Jun 24 08:20:44 PM PDT 24 4385286644 ps
T509 /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.295235642 Jun 24 08:04:13 PM PDT 24 Jun 24 08:16:25 PM PDT 24 4910565200 ps
T1077 /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.1425437224 Jun 24 08:26:31 PM PDT 24 Jun 24 08:35:08 PM PDT 24 3047869474 ps
T1078 /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.3188933710 Jun 24 08:04:35 PM PDT 24 Jun 24 08:08:05 PM PDT 24 2445497722 ps
T1079 /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.3631782827 Jun 24 08:05:57 PM PDT 24 Jun 24 08:24:44 PM PDT 24 5414200949 ps
T1080 /workspace/coverage/default/25.chip_sw_all_escalation_resets.1812523554 Jun 24 08:37:43 PM PDT 24 Jun 24 08:50:08 PM PDT 24 5578389100 ps
T1081 /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.1981261330 Jun 24 08:30:31 PM PDT 24 Jun 24 08:33:50 PM PDT 24 2949615976 ps
T1082 /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.2056589194 Jun 24 08:25:30 PM PDT 24 Jun 24 09:23:23 PM PDT 24 15722896750 ps
T1083 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.942618731 Jun 24 08:12:49 PM PDT 24 Jun 24 09:14:14 PM PDT 24 17342639300 ps
T230 /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.437239359 Jun 24 08:21:19 PM PDT 24 Jun 24 08:29:40 PM PDT 24 4563011780 ps
T301 /workspace/coverage/default/71.chip_sw_all_escalation_resets.2966946843 Jun 24 08:40:39 PM PDT 24 Jun 24 08:49:07 PM PDT 24 5206632952 ps
T1084 /workspace/coverage/default/1.rom_e2e_asm_init_prod.1340169264 Jun 24 08:26:00 PM PDT 24 Jun 24 09:25:37 PM PDT 24 15906778531 ps
T40 /workspace/coverage/default/1.chip_sw_gpio.3167801745 Jun 24 08:08:40 PM PDT 24 Jun 24 08:16:09 PM PDT 24 4065252300 ps
T1085 /workspace/coverage/default/0.chip_sw_usbdev_dpi.2383710778 Jun 24 08:03:43 PM PDT 24 Jun 24 08:52:12 PM PDT 24 12806220580 ps
T1086 /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.2976549008 Jun 24 08:09:38 PM PDT 24 Jun 24 08:13:36 PM PDT 24 2990979374 ps
T1087 /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.2798962655 Jun 24 08:04:04 PM PDT 24 Jun 24 08:06:23 PM PDT 24 3203686362 ps
T662 /workspace/coverage/default/55.chip_sw_all_escalation_resets.2264863216 Jun 24 08:40:22 PM PDT 24 Jun 24 08:50:31 PM PDT 24 6278902856 ps
T1088 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1981028005 Jun 24 08:10:09 PM PDT 24 Jun 24 08:20:59 PM PDT 24 4024426720 ps
T1089 /workspace/coverage/default/86.chip_sw_all_escalation_resets.409186650 Jun 24 08:41:37 PM PDT 24 Jun 24 08:49:16 PM PDT 24 4658295780 ps
T1090 /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3115782005 Jun 24 08:18:14 PM PDT 24 Jun 24 08:27:03 PM PDT 24 4580427380 ps
T1091 /workspace/coverage/default/83.chip_sw_all_escalation_resets.1377652532 Jun 24 08:43:26 PM PDT 24 Jun 24 08:52:42 PM PDT 24 5171105708 ps
T1092 /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.523982437 Jun 24 08:09:51 PM PDT 24 Jun 24 08:17:56 PM PDT 24 3985430926 ps
T281 /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.4235582863 Jun 24 08:09:21 PM PDT 24 Jun 24 08:12:27 PM PDT 24 3067156075 ps
T1093 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.688351249 Jun 24 08:24:48 PM PDT 24 Jun 24 09:44:29 PM PDT 24 49110100704 ps
T1094 /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.1105516684 Jun 24 08:07:54 PM PDT 24 Jun 24 08:12:21 PM PDT 24 2473608440 ps
T1095 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.992338486 Jun 24 08:13:12 PM PDT 24 Jun 24 09:28:52 PM PDT 24 15865347250 ps
T1096 /workspace/coverage/default/1.chip_sw_rv_timer_irq.1610125823 Jun 24 08:14:37 PM PDT 24 Jun 24 08:17:55 PM PDT 24 2752465480 ps
T1097 /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.3035949682 Jun 24 08:36:31 PM PDT 24 Jun 24 08:45:50 PM PDT 24 4519077432 ps
T1098 /workspace/coverage/default/1.chip_sw_kmac_smoketest.365594381 Jun 24 08:24:06 PM PDT 24 Jun 24 08:28:56 PM PDT 24 3032043000 ps
T46 /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.854804198 Jun 24 08:22:20 PM PDT 24 Jun 24 08:26:28 PM PDT 24 2808767720 ps
T1099 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2123503522 Jun 24 08:10:34 PM PDT 24 Jun 24 08:17:21 PM PDT 24 7703268156 ps
T651 /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3444475039 Jun 24 08:41:26 PM PDT 24 Jun 24 08:48:30 PM PDT 24 3666453432 ps
T1100 /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.553079475 Jun 24 08:06:20 PM PDT 24 Jun 24 08:11:44 PM PDT 24 3968912277 ps
T1101 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3536877705 Jun 24 08:08:23 PM PDT 24 Jun 24 08:20:16 PM PDT 24 5335906351 ps
T1102 /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.62894601 Jun 24 08:23:20 PM PDT 24 Jun 24 08:30:23 PM PDT 24 7464965416 ps
T1103 /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.2294863704 Jun 24 08:16:22 PM PDT 24 Jun 24 08:25:14 PM PDT 24 5242662400 ps
T1104 /workspace/coverage/default/0.chip_sw_aes_smoketest.986302363 Jun 24 08:08:54 PM PDT 24 Jun 24 08:13:55 PM PDT 24 3169043272 ps
T1105 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.386527334 Jun 24 08:16:22 PM PDT 24 Jun 24 08:28:21 PM PDT 24 5457362824 ps
T1106 /workspace/coverage/default/2.chip_sw_hmac_smoketest.2350173543 Jun 24 08:30:53 PM PDT 24 Jun 24 08:38:04 PM PDT 24 2724932352 ps
T689 /workspace/coverage/default/74.chip_sw_all_escalation_resets.2682219687 Jun 24 08:42:33 PM PDT 24 Jun 24 08:52:58 PM PDT 24 4928170456 ps
T1107 /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.2281497238 Jun 24 08:05:07 PM PDT 24 Jun 24 08:23:17 PM PDT 24 9015250158 ps
T1108 /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.653058895 Jun 24 08:24:03 PM PDT 24 Jun 24 08:30:12 PM PDT 24 3137108392 ps
T740 /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.1161687426 Jun 24 08:43:56 PM PDT 24 Jun 24 08:50:39 PM PDT 24 4039637580 ps
T1109 /workspace/coverage/default/1.rom_e2e_static_critical.4180472658 Jun 24 08:25:35 PM PDT 24 Jun 24 09:38:43 PM PDT 24 17211022780 ps
T1110 /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.3208394884 Jun 24 08:24:44 PM PDT 24 Jun 24 08:34:35 PM PDT 24 5220326937 ps
T1111 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1769990218 Jun 24 08:12:49 PM PDT 24 Jun 24 08:18:21 PM PDT 24 3727069977 ps
T1112 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.367553694 Jun 24 08:06:33 PM PDT 24 Jun 24 08:58:22 PM PDT 24 39374705383 ps
T1113 /workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.1193589841 Jun 24 08:37:02 PM PDT 24 Jun 24 09:43:57 PM PDT 24 17168774392 ps
T1114 /workspace/coverage/default/1.chip_sw_csrng_kat_test.3213672069 Jun 24 08:16:07 PM PDT 24 Jun 24 08:19:22 PM PDT 24 1980495594 ps
T1115 /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.3387761309 Jun 24 08:22:57 PM PDT 24 Jun 24 08:30:10 PM PDT 24 6849122322 ps
T282 /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1977338702 Jun 24 08:04:44 PM PDT 24 Jun 24 08:11:11 PM PDT 24 3203197888 ps
T1116 /workspace/coverage/default/2.chip_sw_example_rom.1868178563 Jun 24 08:21:01 PM PDT 24 Jun 24 08:23:18 PM PDT 24 2316400408 ps
T1117 /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.445291006 Jun 24 08:34:38 PM PDT 24 Jun 24 08:42:03 PM PDT 24 6711498850 ps
T1118 /workspace/coverage/default/0.chip_sw_otbn_smoketest.464421417 Jun 24 08:09:43 PM PDT 24 Jun 24 08:31:42 PM PDT 24 5777996664 ps
T1119 /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.1266268124 Jun 24 08:04:11 PM PDT 24 Jun 24 09:33:29 PM PDT 24 44688016100 ps
T1120 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.949484113 Jun 24 08:09:45 PM PDT 24 Jun 24 08:22:36 PM PDT 24 3806130568 ps
T1121 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.2045726458 Jun 24 08:16:34 PM PDT 24 Jun 24 08:22:30 PM PDT 24 3067877776 ps
T1122 /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.4147359900 Jun 24 08:39:46 PM PDT 24 Jun 24 08:45:56 PM PDT 24 4408105250 ps
T1123 /workspace/coverage/default/1.rom_e2e_asm_init_dev.2069602362 Jun 24 08:28:08 PM PDT 24 Jun 24 09:23:52 PM PDT 24 16080295713 ps
T670 /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.367929123 Jun 24 08:39:54 PM PDT 24 Jun 24 08:47:10 PM PDT 24 4096244000 ps
T12 /workspace/coverage/default/1.chip_sw_sleep_pin_retention.1621651824 Jun 24 08:11:24 PM PDT 24 Jun 24 08:16:45 PM PDT 24 3439083990 ps
T13 /workspace/coverage/default/0.chip_sw_sleep_pin_retention.2932080745 Jun 24 08:05:32 PM PDT 24 Jun 24 08:13:31 PM PDT 24 4455505190 ps
T1124 /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.2656743790 Jun 24 08:28:21 PM PDT 24 Jun 24 08:52:36 PM PDT 24 17004971267 ps
T190 /workspace/coverage/default/2.chip_jtag_mem_access.3095175208 Jun 24 08:20:31 PM PDT 24 Jun 24 08:46:11 PM PDT 24 14121841150 ps
T1125 /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.3743510385 Jun 24 08:09:27 PM PDT 24 Jun 24 11:59:09 PM PDT 24 79221546600 ps
T691 /workspace/coverage/default/23.chip_sw_all_escalation_resets.1197975688 Jun 24 08:37:26 PM PDT 24 Jun 24 08:50:36 PM PDT 24 6009191518 ps
T1126 /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.3345621338 Jun 24 08:22:32 PM PDT 24 Jun 24 08:26:50 PM PDT 24 2120220040 ps
T1127 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.1478538212 Jun 24 08:21:58 PM PDT 24 Jun 24 08:33:14 PM PDT 24 4486351914 ps
T1128 /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.2214821096 Jun 24 08:06:03 PM PDT 24 Jun 24 08:13:50 PM PDT 24 3863975613 ps
T1129 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.2887896932 Jun 24 08:05:33 PM PDT 24 Jun 24 08:12:31 PM PDT 24 3931043656 ps
T1130 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.2840328127 Jun 24 08:04:10 PM PDT 24 Jun 24 08:13:41 PM PDT 24 4022885028 ps
T1131 /workspace/coverage/default/3.chip_tap_straps_dev.3105206219 Jun 24 08:30:48 PM PDT 24 Jun 24 08:34:32 PM PDT 24 2939862004 ps
T384 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.3793811722 Jun 24 08:12:50 PM PDT 24 Jun 24 09:42:33 PM PDT 24 24970132756 ps
T1132 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.927789172 Jun 24 08:04:16 PM PDT 24 Jun 24 08:26:55 PM PDT 24 6795448152 ps
T1133 /workspace/coverage/default/1.chip_sw_aon_timer_irq.1080592226 Jun 24 08:12:41 PM PDT 24 Jun 24 08:18:26 PM PDT 24 3904330800 ps
T1134 /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.3513462238 Jun 24 08:27:24 PM PDT 24 Jun 24 08:48:52 PM PDT 24 5084193504 ps
T58 /workspace/coverage/default/1.chip_sw_alert_test.3101596289 Jun 24 08:18:54 PM PDT 24 Jun 24 08:25:13 PM PDT 24 3247160970 ps
T1135 /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.1099618827 Jun 24 08:22:49 PM PDT 24 Jun 24 08:27:30 PM PDT 24 2954941514 ps
T1136 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.3068929438 Jun 24 08:23:58 PM PDT 24 Jun 24 08:34:52 PM PDT 24 9101246370 ps
T247 /workspace/coverage/default/64.chip_sw_all_escalation_resets.2453257765 Jun 24 08:40:52 PM PDT 24 Jun 24 08:50:26 PM PDT 24 4436299632 ps
T1137 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.2634791116 Jun 24 08:14:42 PM PDT 24 Jun 24 08:21:09 PM PDT 24 3684998601 ps
T627 /workspace/coverage/default/2.chip_sw_plic_sw_irq.3740489245 Jun 24 08:26:44 PM PDT 24 Jun 24 08:32:00 PM PDT 24 2666535424 ps
T157 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.4289060998 Jun 24 08:18:45 PM PDT 24 Jun 24 08:38:16 PM PDT 24 10107583880 ps
T1138 /workspace/coverage/default/2.rom_e2e_smoke.1399293997 Jun 24 08:35:12 PM PDT 24 Jun 24 09:45:37 PM PDT 24 15244033768 ps
T1139 /workspace/coverage/default/0.rom_e2e_asm_init_dev.3785369702 Jun 24 08:10:39 PM PDT 24 Jun 24 09:13:43 PM PDT 24 15718168634 ps
T1140 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.1785648127 Jun 24 08:34:37 PM PDT 24 Jun 24 09:39:32 PM PDT 24 15206586256 ps
T723 /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1239900862 Jun 24 08:39:41 PM PDT 24 Jun 24 08:44:54 PM PDT 24 3785534200 ps
T742 /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.2348353425 Jun 24 08:40:09 PM PDT 24 Jun 24 08:47:17 PM PDT 24 4130123032 ps
T1141 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2490705677 Jun 24 08:24:26 PM PDT 24 Jun 24 08:51:07 PM PDT 24 17492174246 ps
T1142 /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.619598339 Jun 24 08:26:55 PM PDT 24 Jun 24 08:37:59 PM PDT 24 5367475476 ps
T358 /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.627821882 Jun 24 08:08:30 PM PDT 24 Jun 24 08:15:00 PM PDT 24 5698837528 ps
T737 /workspace/coverage/default/38.chip_sw_all_escalation_resets.4199967955 Jun 24 08:37:29 PM PDT 24 Jun 24 08:45:09 PM PDT 24 5426278328 ps
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