CHIP Simulation Results

Monday June 24 2024 23:02:35 UTC

GitHub Revision: `6e698b4dfe`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 102849012855470111388983783327793201144267754054590670930996118558901483180117

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	4.440m	3.118ms	3	3	100.00
		chip_sw_example_rom	2.311m	2.920ms	3	3	100.00
		chip_sw_example_manufacturer	3.974m	3.265ms	3	3	100.00
		chip_sw_example_concurrency	4.038m	3.281ms	3	3	100.00
V1	csr_hw_reset	chip_csr_hw_reset	6.818m	7.510ms	5	5	100.00
V1	csr_rw	chip_csr_rw	11.959m	5.647ms	19	20	95.00
V1	csr_bit_bash	chip_csr_bit_bash	2.316h	68.147ms	5	5	100.00
V1	csr_aliasing	chip_csr_aliasing	2.941h	72.910ms	4	5	80.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	1.926m	2.741ms	0	20	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	2.941h	72.910ms	4	5	80.00
		chip_csr_rw	11.959m	5.647ms	19	20	95.00
V1	xbar_smoke	xbar_smoke	10.870s	271.064us	100	100	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	8.369m	4.202ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	8.369m	4.202ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	8.369m	4.202ms	3	3	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	11.149m	4.290ms	5	5	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	11.149m	4.290ms	5	5	100.00
		chip_sw_uart_tx_rx_idx1	13.358m	4.781ms	5	5	100.00
		chip_sw_uart_tx_rx_idx2	13.838m	4.462ms	5	5	100.00
		chip_sw_uart_tx_rx_idx3	12.812m	3.806ms	5	5	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	52.700m	13.179ms	20	20	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	44.410m	13.310ms	5	5	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	30.199m	13.629ms	5	5	100.00
V1		TOTAL			198	220	90.00
V2	chip_pin_mux	chip_padctrl_attributes	5.821m	4.841ms	10	10	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	5.821m	4.841ms	10	10	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	5.905m	2.680ms	3	3	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	6.040m	3.534ms	3	3	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	7.965m	4.456ms	3	3	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	26.006m	12.646ms	5	5	100.00
		chip_tap_straps_testunlock0	26.548m	14.504ms	1	5	20.00
		chip_tap_straps_rma	27.548m	14.245ms	3	5	60.00
		chip_tap_straps_prod	26.766m	15.998ms	5	5	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	4.532m	3.103ms	3	3	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	26.383m	9.323ms	3	3	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	13.418m	6.749ms	6	6	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	13.418m	6.749ms	6	6	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	21.727m	7.090ms	3	3	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	47.564m	19.662ms	2	3	66.67
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	12.080m	3.571ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	18.627m	5.388ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.054h	19.126ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.227m	2.880ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	21.863m	6.874ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	6.399m	3.685ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	39.561m	11.571ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	6.394m	3.329ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.074m	5.662ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.727m	3.189ms	3	3	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	4.043m	2.815ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	20.928m	8.492ms	5	5	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	8.790m	5.449ms	3	3	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	4.939m	3.244ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	8.790m	5.449ms	3	3	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	5.515m	2.880ms	3	3	100.00
		chip_sw_aes_smoketest	5.412m	3.098ms	3	3	100.00
		chip_sw_aon_timer_smoketest	5.506m	2.717ms	3	3	100.00
		chip_sw_clkmgr_smoketest	5.074m	2.985ms	3	3	100.00
		chip_sw_csrng_smoketest	4.080m	2.862ms	3	3	100.00
		chip_sw_entropy_src_smoketest	9.436m	3.802ms	3	3	100.00
		chip_sw_gpio_smoketest	5.282m	2.583ms	3	3	100.00
		chip_sw_hmac_smoketest	9.084m	3.323ms	3	3	100.00
		chip_sw_kmac_smoketest	4.997m	3.031ms	3	3	100.00
		chip_sw_otbn_smoketest	33.614m	9.645ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	7.774m	6.353ms	3	3	100.00
		chip_sw_pwrmgr_usbdev_smoketest	7.169m	6.849ms	3	3	100.00
		chip_sw_rv_plic_smoketest	5.061m	2.973ms	3	3	100.00
		chip_sw_rv_timer_smoketest	6.130m	3.137ms	3	3	100.00
		chip_sw_rstmgr_smoketest	4.808m	2.702ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	5.053m	3.558ms	3	3	100.00
		chip_sw_uart_smoketest	4.821m	2.771ms	3	3	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	4.598m	2.955ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	11.636m	4.627ms	3	3	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	3.945h	78.492ms	3	3	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	1.173h	15.244ms	3	3	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	5.120h	204.233ms	0	3	0.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	16.280m	4.519ms	3	3	100.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	13.386m	10.286ms	3	3	100.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	3.078h	59.189ms	2	3	66.67
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	3.257h	64.967ms	3	3	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	7.132m	4.474ms	30	30	100.00
V2	tl_d_illegal_access	chip_tl_errors	7.132m	4.474ms	30	30	100.00
V2	tl_d_outstanding_access	chip_csr_aliasing	2.941h	72.910ms	4	5	80.00
		chip_same_csr_outstanding	1.250h	27.717ms	20	20	100.00
		chip_csr_hw_reset	6.818m	7.510ms	5	5	100.00
		chip_csr_rw	11.959m	5.647ms	19	20	95.00
V2	tl_d_partial_access	chip_csr_aliasing	2.941h	72.910ms	4	5	80.00
		chip_same_csr_outstanding	1.250h	27.717ms	20	20	100.00
		chip_csr_hw_reset	6.818m	7.510ms	5	5	100.00
		chip_csr_rw	11.959m	5.647ms	19	20	95.00
V2	xbar_base_random_sequence	xbar_random	1.642m	2.658ms	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	7.550s	58.283us	100	100	100.00
		xbar_smoke_large_delays	2.124m	12.247ms	100	100	100.00
		xbar_smoke_slow_rsp	1.983m	7.116ms	100	100	100.00
		xbar_random_zero_delays	58.090s	611.584us	100	100	100.00
		xbar_random_large_delays	19.962m	106.774ms	100	100	100.00
		xbar_random_slow_rsp	20.356m	68.623ms	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.045m	1.392ms	100	100	100.00
		xbar_error_and_unmapped_addr	59.490s	1.406ms	100	100	100.00
V2	xbar_error_cases	xbar_error_random	1.526m	2.554ms	100	100	100.00
		xbar_error_and_unmapped_addr	59.490s	1.406ms	100	100	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.156m	2.835ms	100	100	100.00
		xbar_access_same_device_slow_rsp	56.261m	175.286ms	100	100	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.387m	2.685ms	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	18.154m	25.139ms	100	100	100.00
		xbar_stress_all_with_error	9.820m	16.990ms	100	100	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	17.160m	18.626ms	100	100	100.00
		xbar_stress_all_with_reset_error	13.907m	19.087ms	100	100	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	1.173h	15.244ms	3	3	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	10.977m	7.434ms	0	3	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	14.615m	4.931ms	0	3	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	1.056h	12.154ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	1.216h	15.193ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	1.328h	16.328ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	1.002h	15.522ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	1.131h	14.772ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	57.201m	11.831ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	1.037h	15.664ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	1.139h	15.404ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	1.184h	15.787ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	1.304h	15.776ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	1.411h	18.723ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	1.750h	25.173ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	1.600h	24.042ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	1.495h	24.970ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	1.924h	23.652ms	1	1	100.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	7.144m	3.783ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	14.770m	4.963ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	13.675m	5.161ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	12.772m	4.768ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	11.841m	4.477ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	6.419m	3.964ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	14.708m	4.704ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	15.268m	4.609ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	12.944m	5.228ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	11.902m	4.389ms	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	7.200m	4.551ms	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	14.252m	4.964ms	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	14.987m	5.451ms	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	15.989m	6.031ms	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	12.201m	5.556ms	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	52.630m	11.337ms	3	3	100.00
		rom_e2e_asm_init_dev	1.051h	15.718ms	3	3	100.00
		rom_e2e_asm_init_prod	1.148h	15.926ms	3	3	100.00
		rom_e2e_asm_init_prod_end	1.096h	15.536ms	3	3	100.00
		rom_e2e_asm_init_rma	1.260h	15.243ms	3	3	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	1.087h	15.751ms	3	3	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	1.219h	15.537ms	3	3	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	1.260h	15.865ms	3	3	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	1.218h	17.211ms	3	3	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.791m	2.891ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.227m	2.880ms	3	3	100.00
V2	chip_sw_aes_multi_block	chip_sw_aes_multi_block			0	0	--
V2	chip_sw_aes_interrupt_encryption	chip_sw_aes_interrupt_encryption			0	0	--
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	5.396m	3.163ms	3	3	100.00
V2	chip_sw_aes_prng_reseed	chip_sw_aes_prng_reseed			0	0	--
V2	chip_sw_aes_force_prng_reseed	chip_sw_aes_force_prng_reseed			0	0	--
V2	chip_sw_aes_idle	chip_sw_aes_idle	5.497m	3.225ms	3	3	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	42.881m	13.173ms	3	3	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	10.444m	18.919ms	3	3	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	10.444m	18.919ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	7.025m	3.966ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	7.774m	6.353ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	7.025m	3.966ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	13.943m	7.849ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	13.943m	7.849ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	10.380m	7.748ms	5	5	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	10.881m	5.667ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	16.919m	6.162ms	3	3	100.00
		chip_sw_aes_idle	5.497m	3.225ms	3	3	100.00
		chip_sw_hmac_enc_idle	6.533m	3.050ms	3	3	100.00
		chip_sw_kmac_idle	4.850m	3.388ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	8.826m	5.243ms	3	3	100.00
		chip_sw_clkmgr_off_hmac_trans	8.367m	4.930ms	3	3	100.00
		chip_sw_clkmgr_off_kmac_trans	12.355m	4.035ms	3	3	100.00
		chip_sw_clkmgr_off_otbn_trans	11.034m	5.367ms	3	3	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	28.269m	9.125ms	3	3	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.998m	4.776ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.458m	4.953ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.072m	3.694ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.545m	4.727ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.896m	4.821ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.223m	5.086ms	3	3	100.00
		chip_sw_ast_clk_outputs	21.727m	7.090ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	17.823m	10.388ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.072m	3.694ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.545m	4.727ms	3	3	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	12.080m	3.571ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	18.627m	5.388ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.054h	19.126ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.227m	2.880ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	21.863m	6.874ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	6.399m	3.685ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	39.561m	11.571ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	6.394m	3.329ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.074m	5.662ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.727m	3.189ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	4.590m	3.366ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	12.641m	4.704ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	21.382m	7.392ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	1.216h	25.782ms	3	3	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	4.437m	3.123ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	4.779m	3.086ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	31.827m	11.656ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	5.510m	3.727ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	10.673m	5.772ms	3	3	100.00
		chip_sw_flash_init_reduced_freq	35.116m	23.130ms	3	3	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	1.568h	34.132ms	1	3	33.33
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	21.727m	7.090ms	3	3	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	11.508m	4.777ms	3	3	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	8.604m	3.048ms	3	3	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	16.989m	5.185ms	100	100	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	37.234m	9.278ms	3	3	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	26.943m	7.724ms	3	3	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	7.980m	5.298ms	3	3	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	15.390m	8.226ms	3	3	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.814m	2.706ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	19.681m	6.492ms	3	3	100.00
		chip_sw_sysrst_ctrl_reset	35.293m	22.116ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	5.483m	3.340ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	7.082m	3.986ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	13.335m	4.554ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	35.293m	22.116ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	35.293m	22.116ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	55.788m	20.430ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	55.788m	20.430ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	10.781m	5.162ms	3	3	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	10.444m	18.919ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	1.785h	29.290ms	10	10	100.00
		chip_sw_entropy_src_ast_rng_req	4.256m	2.883ms	3	3	100.00
		chip_sw_edn_entropy_reqs	21.337m	5.729ms	3	3	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	4.256m	2.883ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	26.943m	7.724ms	3	3	100.00
V2	chip_sw_entropy_src_fuse_en_fw_read	chip_sw_entropy_src_fuse_en_fw_read_test			0	0	--
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	4.932m	3.554ms	3	3	100.00
V2	chip_sw_entropy_src_fw_observe_many_contiguous	chip_sw_entropy_src_fw_observe_many_contiguous			0	0	--
V2	chip_sw_entropy_src_fw_extract_and_insert	chip_sw_entropy_src_fw_extract_and_insert			0	0	--
V2	chip_sw_flash_init	chip_sw_flash_init	38.022m	23.373ms	3	3	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	18.391m	5.802ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	18.627m	5.388ms	3	3	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	12.842m	3.640ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en	12.080m	3.571ms	3	3	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	1.535h	44.379ms	3	3	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	38.022m	23.373ms	3	3	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	6.584m	3.505ms	3	3	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	36.512m	10.401ms	3	3	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	8.473m	5.626ms	3	3	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	1.535h	44.379ms	3	3	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	8.473m	5.626ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	8.473m	5.626ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	8.473m	5.626ms	3	3	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	8.473m	5.626ms	3	3	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	16.989m	5.185ms	100	100	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	6.897m	8.944ms	3	3	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	21.437m	5.084ms	3	3	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	12.632m	5.686ms	3	3	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	12.632m	5.686ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	5.606m	2.680ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	6.399m	3.685ms	3	3	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	6.533m	3.050ms	3	3	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	6.232m	3.505ms	3	3	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	29.223m	7.218ms	3	3	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	13.616m	5.065ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx1	15.696m	5.261ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx2	14.695m	4.324ms	3	3	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	9.564m	3.482ms	3	3	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	36.512m	10.401ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	39.561m	11.571ms	3	3	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	43.246m	11.413ms	3	3	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	42.881m	13.173ms	3	3	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	1.387h	15.888ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	5.038m	2.961ms	3	3	100.00
		chip_sw_kmac_mode_kmac	6.881m	3.441ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	6.394m	3.329ms	3	3	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	36.512m	10.401ms	3	3	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	22.551m	10.481ms	15	15	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	5.290m	2.758ms	3	3	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	5.676m	3.165ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	4.850m	3.388ms	3	3	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	10.203m	5.799ms	3	3	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	26.006m	12.646ms	5	5	100.00
		chip_tap_straps_rma	27.548m	14.245ms	3	5	60.00
		chip_tap_straps_prod	26.766m	15.998ms	5	5	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	4.943m	2.503ms	3	3	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	22.551m	10.481ms	15	15	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	22.551m	10.481ms	15	15	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	22.551m	10.481ms	15	15	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	34.024m	9.583ms	3	3	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	8.473m	5.626ms	3	3	100.00
		chip_sw_flash_rma_unlocked	1.535h	44.379ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	14.173m	3.681ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	22.534m	9.718ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	26.677m	9.031ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	23.892m	7.558ms	3	3	100.00
		chip_sw_lc_ctrl_transition	22.551m	10.481ms	15	15	100.00
		chip_sw_keymgr_key_derivation	36.512m	10.401ms	3	3	100.00
		chip_sw_rom_ctrl_integrity_check	9.511m	8.932ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	18.523m	9.719ms	3	3	100.00
		chip_prim_tl_access	6.897m	8.944ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	17.823m	10.388ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.998m	4.776ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.458m	4.953ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.072m	3.694ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.545m	4.727ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.896m	4.821ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.223m	5.086ms	3	3	100.00
		chip_tap_straps_dev	26.006m	12.646ms	5	5	100.00
		chip_tap_straps_rma	27.548m	14.245ms	3	5	60.00
		chip_tap_straps_prod	26.766m	15.998ms	5	5	100.00
		chip_rv_dm_lc_disabled	12.327m	21.013ms	3	3	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	3.494m	2.445ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	2.372m	3.435ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	2.275m	3.204ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	5.849m	3.732ms	3	3	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	46.400m	34.433ms	3	3	100.00
		chip_rv_dm_lc_disabled	12.327m	21.013ms	3	3	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.542h	46.540ms	3	3	100.00
		chip_sw_lc_walkthrough_prod	1.459h	49.951ms	3	3	100.00
		chip_sw_lc_walkthrough_prodend	18.070m	8.099ms	3	3	100.00
		chip_sw_lc_walkthrough_rma	1.600h	48.743ms	3	3	100.00
		chip_sw_lc_walkthrough_testunlocks	46.400m	34.433ms	3	3	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	2.101m	2.573ms	3	3	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	2.405m	2.980ms	3	3	100.00
		rom_volatile_raw_unlock	1.845m	2.068ms	3	3	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	22.551m	10.481ms	15	15	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	38.022m	23.373ms	3	3	100.00
		chip_sw_otbn_mem_scramble	10.951m	3.574ms	3	3	100.00
		chip_sw_keymgr_key_derivation	36.512m	10.401ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	11.232m	4.780ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.754m	3.050ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	38.022m	23.373ms	3	3	100.00
		chip_sw_otbn_mem_scramble	10.951m	3.574ms	3	3	100.00
		chip_sw_keymgr_key_derivation	36.512m	10.401ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	11.232m	4.780ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.754m	3.050ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	22.551m	10.481ms	15	15	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	22.743m	14.850ms	0	3	0.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	4.943m	2.503ms	3	3	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	14.173m	3.681ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	22.534m	9.718ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	26.677m	9.031ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	23.892m	7.558ms	3	3	100.00
		chip_sw_lc_ctrl_transition	22.551m	10.481ms	15	15	100.00
		chip_prim_tl_access	6.897m	8.944ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	6.897m	8.944ms	3	3	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	1.574h	29.171ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	11.264m	7.402ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	28.257m	23.325ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	5.969m	7.117ms	1	3	33.33
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	11.316m	9.417ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	12.631m	6.532ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	35.998m	23.847ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	31.276m	15.001ms	3	3	100.00
		chip_sw_aon_timer_wdog_bite_reset	13.943m	7.849ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	26.420m	12.653ms	3	3	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	8.931m	4.215ms	3	3	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	11.264m	7.402ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	9.841m	5.220ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	54.547m	42.571ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	9.417m	7.117ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	9.034m	6.032ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	54.709m	29.205ms	3	3	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	19.681m	6.492ms	3	3	100.00
		chip_sw_pwrmgr_all_reset_reqs	28.367m	9.539ms	3	3	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	48.187m	23.446ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	5.310m	3.578ms	3	3	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	16.989m	5.185ms	100	100	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	9.511m	8.932ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	9.511m	8.932ms	3	3	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	28.367m	9.539ms	3	3	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	54.709m	29.205ms	3	3	100.00
		chip_sw_pwrmgr_wdog_reset	8.931m	4.215ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	7.774m	6.353ms	3	3	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	7.068m	3.565ms	3	3	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	9.918m	5.656ms	3	3	100.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	8.051m	4.592ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	32.294m	11.513ms	3	3	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.850m	2.573ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	16.989m	5.185ms	100	100	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	29.313m	7.856ms	3	3	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	23.185m	6.426ms	3	3	100.00
		chip_plic_all_irqs_10	10.363m	4.483ms	3	3	100.00
		chip_plic_all_irqs_20	14.160m	4.403ms	3	3	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	5.246m	2.667ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	5.054m	2.378ms	3	3	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	1.173h	15.244ms	3	3	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	11.554m	6.109ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	40.123m	13.288ms	2	3	66.67
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	7.954m	3.522ms	3	3	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	6.121m	2.554ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	11.232m	4.780ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.074m	5.662ms	3	3	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	12.408m	6.676ms	3	3	100.00
		chip_sw_sleep_sram_ret_contents_scramble	10.312m	7.391ms	3	3	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	18.523m	9.719ms	3	3	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	16.989m	5.185ms	100	100	100.00
		chip_sw_data_integrity_escalation	13.418m	6.749ms	6	6	100.00
V2	chip_sw_usbdev_mem	chip_sw_usbdev_mem			0	0	--
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	3.974m	2.801ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	4.229m	2.571ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	8.860m	4.112ms	1	1	100.00
V2	chip_sw_usbdev_sof	chip_sw_usbdev_sof			0	0	--
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	10.337m	3.520ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	35.527m	8.248ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.879h	31.692ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	48.445m	12.806ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	6.561m	3.518ms	3	3	100.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	10.203m	5.799ms	3	3	100.00
V2	chip_sw_alert_handler_escalation_nmi_reset	chip_sw_alert_handler_escalation_nmi_reset			0	0	--
V2	chip_sw_alert_handler_escalation_methods	chip_sw_alert_handler_escalation_methods			0	0	--
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	16.989m	5.185ms	100	100	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs			0	0	--
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	5.555m	2.938ms	3	3	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	32.294m	11.513ms	3	3	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	11.774m	5.533ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	8.551m	3.653ms	87	90	96.67
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	23.069m	11.693ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	37.234m	9.278ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	29.313m	7.856ms	3	3	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	23.252m	7.897ms	3	3	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	3.728h	254.390ms	2	3	66.67
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	36.252m	19.469ms	3	3	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	27.518m	13.486ms	3	3	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	7.068m	3.565ms	3	3	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	10.270m	5.125ms	3	3	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	10.087m	3.615ms	0	3	0.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	27.548m	14.245ms	3	5	60.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	12.327m	21.013ms	3	3	100.00
V2	chip_rv_dm_jtag	chip_rv_dm_jtag			0	0	--
V2	chip_rv_dm_dtm	chip_rv_dm_dtm			0	0	--
V2	chip_rv_dm_control_status	chip_rv_dm_control_status			0	0	--
V2		TOTAL			2597	2644	98.22
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	6.742m	2.968ms	3	3	100.00
V2S		TOTAL			3	3	100.00
V3	chip_sw_usb_suspend	chip_sw_usb_suspend			0	0	--
V3	chip_usb_wake_debug	chip_usb_wake_debug			0	0	--
V3	chip_sw_coremark	chip_sw_coremark			0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus			0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	24.414m	8.503ms	0	1	0.00
		rom_e2e_jtag_debug_dev	13.750m	7.214ms	0	1	0.00
		rom_e2e_jtag_debug_rma	19.707m	6.622ms	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	36.181m	24.955ms	1	1	100.00
		rom_e2e_jtag_inject_dev	47.810m	24.206ms	1	1	100.00
		rom_e2e_jtag_inject_rma	31.345m	27.436ms	1	1	100.00
V3	rom_bootstrap_rma	rom_bootstrap_rma			0	0	--
V3	rom_e2e_weak_straps	rom_e2e_weak_straps			0	0	--
V3	rom_e2e_self_hash	rom_e2e_self_hash			0	0	--
V3	manuf_cp_unlock_raw	manuf_cp_unlock_raw			0	0	--
V3	manuf_scrap	manuf_scrap			0	0	--
V3	manuf_cp_yield_test	manuf_cp_yield_test			0	0	--
V3	manuf_cp_ast_test_execution	manuf_cp_ast_test_execution			0	0	--
V3	manuf_cp_device_info_flash_wr	manuf_cp_device_info_flash_wr			0	0	--
V3	manuf_cp_test_lock	manuf_cp_test_lock			0	0	--
V3	manuf_ft_exit_token	manuf_ft_exit_token			0	0	--
V3	manuf_ft_sku_individualization_preop	manuf_ft_sku_individualization_preop			0	0	--
V3	manuf_ft_sku_individualization	manuf_ft_sku_individualization			0	0	--
V3	manuf_ft_provision_rma_token_and_personalization	manuf_ft_provision_rma_token_and_personalization			0	0	--
V3	manuf_ft_load_transport_image	manuf_ft_load_transport_image			0	0	--
V3	manuf_ft_load_certificates	manuf_ft_load_certificates			0	0	--
V3	manuf_ft_eom	manuf_ft_eom			0	0	--
V3	manuf_rma_entry	manuf_rma_entry			0	0	--
V3	manuf_sram_program_crc_functest	manuf_sram_program_crc_functest			0	0	--
V3	chip_sw_adc_ctrl_normal	chip_sw_adc_ctrl_normal			0	0	--
V3	chip_sw_adc_ctrl_oneshot	chip_sw_adc_ctrl_oneshot			0	0	--
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.630m	2.910ms	3	3	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	10.674m	2.647ms	3	3	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	20.820m	4.760ms	3	3	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	43.012m	9.836ms	3	3	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	13.737m	3.354ms	3	3	100.00
V3	chip_sw_entropy_src_bypass_mode_health_tests	chip_sw_entropy_src_bypass_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_fips_mode_health_tests	chip_sw_entropy_src_fips_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_validation	chip_sw_entropy_src_validation			0	0	--
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	21.993m	5.698ms	3	3	100.00
V3	chip_sw_hmac_sha2_stress	chip_sw_hmac_sha2_stress			0	0	--
V3	chip_sw_hmac_stress	chip_sw_hmac_stress			0	0	--
V3	chip_sw_hmac_endianness	chip_sw_hmac_endianness			0	0	--
V3	chip_sw_hmac_secure_wipe	chip_sw_hmac_secure_wipe			0	0	--
V3	chip_sw_hmac_error_conditions	chip_sw_hmac_error_conditions			0	0	--
V3	chip_sw_i2c_speed	chip_sw_i2c_speed			0	0	--
V3	chip_sw_i2c_override	//sw/device/tests:i2c_host_override_test			0	0	--
V3	chip_sw_i2c_clockstretching	chip_sw_i2c_clockstretching			0	0	--
V3	chip_sw_i2c_nack	chip_sw_i2c_nack			0	0	--
V3	chip_sw_i2c_repeatedstart	chip_sw_i2c_repeatedstart			0	0	--
V3	chip_sw_keymgr_sideload_kmac_error	chip_sw_keymgr_sideload_kmac_error			0	0	--
V3	chip_sw_keymgr_derive_attestation	chip_sw_keymgr_derive_attestation			0	0	--
V3	chip_sw_keymgr_derive_sealing	chip_sw_keymgr_derive_sealing			0	0	--
V3	chip_sw_kmac_sha3_stress	chip_sw_kmac_sha3_stress			0	0	--
V3	chip_sw_kmac_shake_stress	chip_sw_kmac_shake_stress			0	0	--
V3	chip_sw_kmac_cshake_stress	chip_sw_kmac_cshake_stress			0	0	--
V3	chip_sw_kmac_kmac_stress	chip_sw_kmac_kmac_stress			0	0	--
V3	chip_sw_kmac_kmac_key_sideload	chip_sw_kmac_kmac_key_sideload			0	0	--
V3	chip_sw_kmac_endianess	chip_sw_kmac_endianess			0	0	--
V3	chip_sw_kmac_entropy_stress	chip_sw_kmac_entropy_stress			0	0	--
V3	chip_sw_kmac_error_conditions	chip_sw_kmac_error_conditions			0	0	--
V3	chip_sw_lc_ctrl_kmac_error	chip_sw_lc_ctrl_kmac_error			0	0	--
V3	chip_sw_lc_ctrl_debug_access	chip_sw_lc_ctrl_debug_access			0	0	--
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	4.608m	3.053ms	3	3	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	9.040m	4.413ms	1	1	100.00
V3	otp_ctrl_calibration	otp_ctrl_calibration			0	0	--
V3	otp_ctrl_partition_access_locked	otp_ctrl_partition_access_locked			0	0	--
V3	otp_ctrl_check_timeout	otp_ctrl_check_timeout			0	0	--
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	8.850m	6.994ms	3	3	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	10.932m	5.582ms	3	3	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	28.367m	9.539ms	3	3	100.00
V3	chip_sw_rom_ctrl_kmac_error	chip_sw_rom_ctrl_kmac_error			0	0	--
V3	chip_sw_rom_ctrl_digests	chip_sw_rom_ctrl_digests			0	0	--
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	16.989m	5.185ms	100	100	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test			0	3	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test			0	3	0.00
V3	chip_sw_spi_device_pass_through_flash_model	//sw/device/tests:spi_passthru_test			0	0	--
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_output_when_disabled_or_sleeping			0	0	--
V3	chip_sw_spi_host_pass_through	//sw/device/tests:spi_passthru_test			0	0	--
V3	chip_sw_spi_host_configuration	chip_sw_spi_host_configuration			0	0	--
V3	chip_sw_spi_host_events	chip_sw_spi_host_events			0	0	--
V3	chip_sw_sram_memset	chip_sw_sram_memset			0	0	--
V3	chip_sw_sram_subword_access	chip_sw_sram_subword_access			0	0	--
V3	chip_sw_uart_parity	chip_sw_uart_parity			0	0	--
V3	chip_sw_uart_line_loopback	chip_sw_uart_line_loopback			0	0	--
V3	chip_sw_uart_system_loopback	chip_sw_uart_system_loopback			0	0	--
V3	chip_sw_uart_line_break	chip_sw_uart_line_break			0	0	--
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	11.149m	4.290ms	5	5	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	1.277h	18.730ms	1	1	100.00
V3	chip_sw_usbdev_iso	chip_sw_usbdev_iso			0	0	--
V3	chip_sw_usbdev_mixed	chip_sw_usbdev_mixed			0	0	--
V3	chip_sw_usbdev_suspend_resume	chip_sw_usbdev_suspend_resume			0	0	--
V3	chip_sw_usbdev_aon_wake_reset	chip_sw_usbdev_aon_wake_reset			0	0	--
V3	chip_sw_usbdev_aon_wake_disconnect	chip_sw_usbdev_aon_wake_disconnect			0	0	--
V3	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore			0	0	--
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	24.414m	8.503ms	0	1	0.00
		rom_e2e_jtag_debug_dev	13.750m	7.214ms	0	1	0.00
		rom_e2e_jtag_debug_rma	19.707m	6.622ms	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	12.968m	5.864ms	3	3	100.00
V3		TOTAL			35	45	77.78
	Unmapped tests	chip_sival_flash_info_access	5.883m	2.836ms	3	3	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	13.860m	4.970ms	3	3	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	4.755m	2.914ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq	1.053h	17.306ms	3	3	100.00
		chip_sw_rv_core_ibex_rnd	19.044m	5.606ms	3	3	100.00
		chip_sw_rv_core_ibex_nmi_irq	15.729m	4.590ms	3	3	100.00
		chip_sw_pwrmgr_lowpower_cancel	8.290m	3.946ms	3	3	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	10.884m	5.711ms	3	3	100.00
		chip_sw_rv_core_ibex_address_translation	6.423m	3.203ms	3	3	100.00
		chip_sw_rv_core_ibex_lockstep_glitch	5.366m	3.538ms	3	3	100.00
		chip_sw_flash_ctrl_write_clear	6.492m	3.155ms	3	3	100.00
		TOTAL			2866	2945	97.32

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	11	11	11	100.00
V1	18	18	15	83.33
V2	285	270	241	84.56
V2S	1	1	1	100.00
V3	90	21	15	16.67

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.10	95.39	93.96	95.30	--	94.85	97.53	99.55

Failure Buckets

UVM_ERROR @ * us: (cip_base_vseq.sv:828) [chip_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
- Test chip_csr_mem_rw_with_rand_reset has 20 failures.
  - 0.chip_csr_mem_rw_with_rand_reset.24381745654144600542661004210064067543659097473830906994538185423160728921552
    Line 363, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2071.653265 us: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2071.653265 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_csr_mem_rw_with_rand_reset.79643576640213788875342988842889324280344016391139700330623847772413147686489
    Line 381, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2635.581862 us: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2635.581862 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 18 more failures.
UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:35) [chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "OpenTitan:*-*-* has 15 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.81537803519301753438262480035277541271091168866254494303345886831954048519104
    Line 1015, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_ERROR @ 3783.417315 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "OpenTitan:4001-0002-01
  GIT:" == "BFV:07535603
  LCV:02108421
  "
  UVM_INFO @ 3783.417315 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.14707671310442873749595038012059329300961699429863215569097802378655258071903
    Line 1359, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_ERROR @ 4962.504837 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "OpenTitan:4001-0002-01
  GIT:" == "BFV:07535603
  LCV:21084210
  "
  UVM_INFO @ 4962.504837 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
- Test rom_e2e_sigverify_always_a_bad_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_prod.83904903196583108867448931893753059724111136160210457697209478300030949652894
    Line 1038, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest/run.log
```
  UVM_ERROR @ 5161.170313 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "OpenTitan:4001-0002-01
  GIT:" == "BFV:07535603
  LCV:2318c631
  "
  UVM_INFO @ 5161.170313 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
- Test rom_e2e_sigverify_always_a_bad_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.30994885313683655893013950721457246175592321889126333484964452041584589005012
    Line 1057, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest/run.log
```
  UVM_ERROR @ 4767.792417 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "OpenTitan:4001-0002-01
  GIT:" == "BFV:07535603
  LCV:25294a52
  "
  UVM_INFO @ 4767.792417 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
- Test rom_e2e_sigverify_always_a_bad_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_rma.85313832485547032707736683273283924691008463784138940631816375520644924396590
    Line 1061, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest/run.log
```
  UVM_ERROR @ 4476.572625 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "OpenTitan:4001-0002-01
  GIT:" == "BFV:07535603
  LCV:2739ce73
  "
  UVM_INFO @ 4476.572625 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
- ... and 10 more tests.
Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 12 failures:
- Test chip_sw_exit_test_unlocked_bootstrap has 1 failures.
  - 0.chip_sw_exit_test_unlocked_bootstrap.12718460771832626309754505196653136610636496821342476982216371180614463390594
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_exit_test_unlocked_bootstrap/latest/run.log
```
  Job ID: smart:058a19ee-0ff5-405e-871b-e697384309d4
```
- Test chip_sw_rv_timer_systick_test has 3 failures.
  - 0.chip_sw_rv_timer_systick_test.22781923271875083993391507797744489136419009330726994638899338306623745232345
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:9beefcee-8b5d-4bb0-99ab-59d2722b9f65
```
  - 1.chip_sw_rv_timer_systick_test.14886439120617462843789493883521351611173149168005143381060541679215466536129
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:fc6cd6e0-d039-4464-95ba-eb7d5f63d632
```
  - ... and 1 more failures.
- Test chip_sw_coremark has 1 failures.
  - 0.chip_sw_coremark.14200175765958380155651068800877884637242639131804494231798868076260052584317
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_coremark/latest/run.log
```
  Job ID: smart:fcd0108e-f453-48dd-a973-1b670a0392e0
```
- Test chip_sw_csrng_edn_concurrency_reduced_freq has 2 failures.
  - 0.chip_sw_csrng_edn_concurrency_reduced_freq.73419861307435201453532503674585951202629039250094139387461139117679809629346
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_edn_concurrency_reduced_freq/latest/run.log
```
  Job ID: smart:535fa113-aadd-427b-80f1-b7a933ad23bd
```
  - 1.chip_sw_csrng_edn_concurrency_reduced_freq.48517571129994900999605597162466071028565514729201234763143471275385677743373
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_edn_concurrency_reduced_freq/latest/run.log
```
  Job ID: smart:33546dc9-a492-4a00-8e8d-dfb6923de23f
```
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.99324455548048028665906969134295872279710396565429004024235117933464983398144
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  Job ID: smart:30e65e8e-3fbd-443b-8c1d-8239b2df6100
```
- ... and 2 more tests.
UVM_FATAL @ * us: (jtag_driver.sv:124) [driver] wait timeout occurred! has 6 failures:
- Test chip_tap_straps_testunlock0 has 4 failures.
  - 0.chip_tap_straps_testunlock0.58784225718166999055923760837953134585960579080510749869341259424880138483706
    Line 5962, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_tap_straps_testunlock0/latest/run.log
```
  UVM_FATAL @ 14158.374152 us: (jtag_driver.sv:124) [uvm_test_top.env.m_jtag_riscv_agent.m_jtag_agent.driver] wait timeout occurred!
  UVM_INFO @ 14158.374152 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_tap_straps_testunlock0.88143887673499375111135005707887099732184511653537665527920433548610107575883
    Line 5936, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_tap_straps_testunlock0/latest/run.log
```
  UVM_FATAL @ 12849.488562 us: (jtag_driver.sv:124) [uvm_test_top.env.m_jtag_riscv_agent.m_jtag_agent.driver] wait timeout occurred!
  UVM_INFO @ 12849.488562 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
- Test chip_tap_straps_rma has 2 failures.
  - 0.chip_tap_straps_rma.54305663693330684555626541860680778275890643420838779809234460272685361212923
    Line 6080, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_tap_straps_rma/latest/run.log
```
  UVM_FATAL @ 14244.865963 us: (jtag_driver.sv:124) [uvm_test_top.env.m_jtag_riscv_agent.m_jtag_agent.driver] wait timeout occurred!
  UVM_INFO @ 14244.865963 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.chip_tap_straps_rma.112083482497810538253116603303056308536114611370229290169402229232628184789583
    Line 6041, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/3.chip_tap_straps_rma/latest/run.log
```
  UVM_FATAL @ 16829.705947 us: (jtag_driver.sv:124) [uvm_test_top.env.m_jtag_riscv_agent.m_jtag_agent.driver] wait timeout occurred!
  UVM_INFO @ 16829.705947 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:
- Test chip_sw_lc_ctrl_program_error has 3 failures.
  - 0.chip_sw_lc_ctrl_program_error.11119714547781551402392807615663634226540774465067302976476085997249947987785
    Line 820, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_program_error/latest/run.log
```
  UVM_ERROR @ 14849.639880 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 14849.639880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 1.chip_sw_lc_ctrl_program_error.42383326203223337899604028651099183245743636437596883203581169654106005362901
    Line 800, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_program_error/latest/run.log
```
  UVM_ERROR @ 15212.977888 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 15212.977888 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep. has 3 failures:
- Test chip_sw_rv_dm_access_after_wakeup has 3 failures.
  - 0.chip_sw_rv_dm_access_after_wakeup.41068032507342832692310913222132000709540597521472599639972126319981078831647
    Line 854, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 3615.292105 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
  UVM_INFO @ 3615.292105 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_rv_dm_access_after_wakeup.82756332239043503989309395946533088453120255244684289958462745153138456612397
    Line 757, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 4062.779713 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
  UVM_INFO @ 4062.779713 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:35) [chip_sw_rom_e2e_shutdown_exception_c_vseq] Check failed "OpenTitan:*-*-* has 3 failures:
- Test rom_e2e_shutdown_exception_c has 3 failures.
  - 0.rom_e2e_shutdown_exception_c.4128905285442299467895016091819789679210377196738904126009317527358419626140
    Line 1036, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_exception_c/latest/run.log
```
  UVM_ERROR @ 4888.618611 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_shutdown_exception_c_vseq] Check failed "OpenTitan:4001-0002-01
  GIT:" == "BFV:01495202
  LCV:2739ce73
  "
  UVM_INFO @ 4888.618611 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
  - 1.rom_e2e_shutdown_exception_c.22506522684806988963046195849785053063416950954362533543588202762645577082119
    Line 974, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_shutdown_exception_c/latest/run.log
```
  UVM_ERROR @ 4732.090385 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_shutdown_exception_c_vseq] Check failed "OpenTitan:4001-0002-01
  GIT:" == "BFV:01495202
  LCV:2739ce73
  "
  UVM_INFO @ 4732.090385 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:35) [chip_sw_rom_e2e_shutdown_output_vseq] Check failed "OpenTitan:*-*-* has 3 failures:
- Test rom_e2e_shutdown_output has 3 failures.
  - 0.rom_e2e_shutdown_output.5691565906738538799758034501469251134621910957726233223010609222455701725517
    Line 1151, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_output/latest/run.log
```
  UVM_ERROR @ 7433.925006 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_shutdown_output_vseq] Check failed "OpenTitan:4001-0002-01
  GIT:" == "BFV:0142500d
  LCV:02108421
  "
  UVM_INFO @ 7433.925006 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
  - 1.rom_e2e_shutdown_output.97953543212992189519695201967110540369932434809548816409723981021125066618744
    Line 954, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_shutdown_output/latest/run.log
```
  UVM_ERROR @ 6675.059121 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_shutdown_output_vseq] Check failed "OpenTitan:4001-0002-01
  GIT:" == "BFV:0142500d
  LCV:02108421
  "
  UVM_INFO @ 6675.059121 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "uart_putchar.dat" has 3 failures:
- Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_debug_test_unlocked0.38096678392095910976948539881446275088964798969604647116652584135805004804606
    Line 937, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 8503.139500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "uart_putchar.dat"
  UVM_INFO @ 8503.139500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_dev has 1 failures.
  - 0.rom_e2e_jtag_debug_dev.11479762779769925507754008572211050984682220983627493991458375729312045780907
    Line 804, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
```
  UVM_FATAL @ 7214.417500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "uart_putchar.dat"
  UVM_INFO @ 7214.417500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_rma has 1 failures.
  - 0.rom_e2e_jtag_debug_rma.32294022508780019935135638198209501049769563606697277460491879166104844995837
    Line 798, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log
```
  UVM_FATAL @ 6622.080500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "uart_putchar.dat"
  UVM_INFO @ 6622.080500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = * ns has 3 failures:

Test rom_raw_unlock has 3 failures.

0.rom_raw_unlock.93866267659758257224514100720908642777116230674884263396398921595951879161582
Line 789, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_raw_unlock/latest/run.log

  UVM_ERROR @ 205957.627939 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 200000000 ns
  
  UVM_INFO @ 205957.627939 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.rom_raw_unlock.6979342975803597496109928220390773436871788576559457277603859421132359898096
Line 804, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_raw_unlock/latest/run.log

  UVM_ERROR @ 204232.725189 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 200000000 ns
  
  UVM_INFO @ 204232.725189 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 3 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 3 failures.
  - 41.chip_sw_alert_handler_lpg_sleep_mode_alerts.68986987001407324618165711537121991292087550878342310252400733195596340422979
    Line 823, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/41.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3856.928800 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003720 MTVAL=40600800
  UVM_INFO @ 3856.928800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 42.chip_sw_alert_handler_lpg_sleep_mode_alerts.28086840680055559146282010628290950609982756266471143395219956903428431073016
    Line 787, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/42.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3689.329448 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003720 MTVAL=40600800
  UVM_INFO @ 3689.329448 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:250)] CHECK-fail: Expected bits * and * set in filter status, got status * has 2 failures:
- Test chip_sw_pwrmgr_normal_sleep_all_wake_ups has 2 failures.
  - 0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.10319898347528495441210751102963834655944165550987543415376713580466845745022
    Line 757, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest/run.log
```
  UVM_ERROR @ 6758.298368 us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:250)] CHECK-fail: Expected bits 5 and 8 set in filter status, got status 0x100
  UVM_INFO @ 6758.298368 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.93057946218582553509497423372404429889398839902275560448186245128442137871048
    Line 819, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest/run.log
```
  UVM_ERROR @ 6140.825470 us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:250)] CHECK-fail: Expected bits 5 and 8 set in filter status, got status 0x100
  UVM_INFO @ 6140.825470 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:457) [chip_sw_spi_passthrough_collision_vseq] timeout occurred! has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 1.chip_sw_spi_device_pass_through_collision.60503195767191553436875796450095841070688793900012592415158202113031782285743
    Line 1076, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_FATAL @ 13287.969033 us: (chip_sw_base_vseq.sv:457) [uvm_test_top.env.virtual_sequencer.chip_sw_spi_passthrough_collision_vseq] timeout occurred!
  UVM_INFO @ 13287.969033 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job chip_earlgrey_asic-sim-vcs_run_cover_reg_top killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test chip_csr_aliasing has 1 failures.
  - 4.chip_csr_aliasing.55803231372449525771664492344843700490139078098283211578579728046031678357382
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/4.chip_csr_aliasing/latest/run.log
```
  Job ID: smart:6271849e-422b-46e7-a432-c2e3cc8e5bfd
```
UVM_ERROR @ * us: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: chip_reg_block.i2c*.controller_events.arbitration_lost reset value: * has 1 failures:
- Test chip_csr_rw has 1 failures.
  - 16.chip_csr_rw.100530326799028129672550609457650352785459166206318748295391865125861146310993
    Line 962, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/16.chip_csr_rw/latest/run.log
```
  UVM_ERROR @ 4567.120680 us: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: chip_reg_block.i2c0.controller_events.arbitration_lost reset value: 0x0
  UVM_INFO @ 4567.120680 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```