Unified Coverage Report :: Module :: prim_sync_reqack_data

Module : prim_sync_reqack_data

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data	100.00	100.00					100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	100.00	66.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.83	96.47	89.29	99.75		100.00	63.64	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_sync_reqack	91.67	100.00	66.67			100.00	100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	100.00	66.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	84.62			100.00	100.00	u_edn_if

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_sync_reqack	91.67	100.00	66.67			100.00	100.00

Line Coverage for Module : prim_sync_reqack_data

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	153	0	0
CONT_ASSIGN	156	0	0
ALWAYS	159	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
153		unreachable
156		unreachable
159		unreachable
160		unreachable
162		unreachable

---

Assert Coverage for Module : prim_sync_reqack_data

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	940689114	3947	0	0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	940689114	3947	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA

Name	Attempts	Real Successes	Failures	Incomplete
Total	940689114	3947	0	0
T1	110167	2	0	0
T2	201249	0	0	0
T4	214119	1	0	0
T5	69071	1	0	0
T15	136331	24	0	0
T38	233928	4	0	0
T59	177554	4	0	0
T86	74681	2	0	0
T87	126119	24	0	0
T88	145625	2	0	0
T89	216296	2	0	0
T95	108587	8	0	0
T96	282934	0	0	0
T97	142378	0	0	0
T98	128542	0	0	0
T170	0	11	0	0
T171	0	6	0	0
T270	0	8	0	0
T271	0	8	0	0
T272	0	4	0	0
T273	74351	0	0	0
T274	92617	0	0	0
T275	159257	0	0	0
T276	327931	0	0	0
T277	238050	0	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB

Name	Attempts	Real Successes	Failures	Incomplete
Total	940689114	3947	0	0
T1	110167	2	0	0
T2	201249	0	0	0
T4	214119	1	0	0
T5	69071	1	0	0
T15	136331	24	0	0
T38	233928	4	0	0
T59	177554	4	0	0
T86	74681	2	0	0
T87	126119	24	0	0
T88	145625	2	0	0
T89	216296	2	0	0
T95	108587	8	0	0
T96	282934	0	0	0
T97	142378	0	0	0
T98	128542	0	0	0
T170	0	11	0	0
T171	0	6	0	0
T270	0	8	0	0
T271	0	8	0	0
T272	0	4	0	0
T273	74351	0	0	0
T274	92617	0	0	0
T275	159257	0	0	0
T276	327931	0	0	0
T277	238050	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	153	0	0
CONT_ASSIGN	156	0	0
ALWAYS	159	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
153		unreachable
156		unreachable
159		unreachable
160		unreachable
162		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	470344557	45	0	0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	470344557	45	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA

Name	Attempts	Real Successes	Failures	Incomplete
Total	470344557	45	0	0
T2	201249	0	0	0
T95	108587	8	0	0
T96	282934	0	0	0
T97	142378	0	0	0
T98	128542	0	0	0
T170	0	11	0	0
T171	0	6	0	0
T270	0	8	0	0
T271	0	8	0	0
T272	0	4	0	0
T273	74351	0	0	0
T274	92617	0	0	0
T275	159257	0	0	0
T276	327931	0	0	0
T277	238050	0	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB

Name	Attempts	Real Successes	Failures	Incomplete
Total	470344557	45	0	0
T2	201249	0	0	0
T95	108587	8	0	0
T96	282934	0	0	0
T97	142378	0	0	0
T98	128542	0	0	0
T170	0	11	0	0
T171	0	6	0	0
T270	0	8	0	0
T271	0	8	0	0
T272	0	4	0	0
T273	74351	0	0	0
T274	92617	0	0	0
T275	159257	0	0	0
T276	327931	0	0	0
T277	238050	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	153	0	0
CONT_ASSIGN	156	0	0
ALWAYS	159	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
153		unreachable
156		unreachable
159		unreachable
160		unreachable
162		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	470344557	3902	0	0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	470344557	3902	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA

Name	Attempts	Real Successes	Failures	Incomplete
Total	470344557	3902	0	0
T1	110167	2	0	0
T4	214119	1	0	0
T5	69071	1	0	0
T15	136331	24	0	0
T38	233928	4	0	0
T59	177554	4	0	0
T86	74681	2	0	0
T87	126119	24	0	0
T88	145625	2	0	0
T89	216296	2	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB

Name	Attempts	Real Successes	Failures	Incomplete
Total	470344557	3902	0	0
T1	110167	2	0	0
T4	214119	1	0	0
T5	69071	1	0	0
T15	136331	24	0	0
T38	233928	4	0	0
T59	177554	4	0	0
T86	74681	2	0	0
T87	126119	24	0	0
T88	145625	2	0	0
T89	216296	2	0	0