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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.01 95.46 93.71 95.36 94.43 97.53 99.57


Total test records in report: 2870
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T1032 /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.2307106480 Jun 26 07:55:18 PM PDT 24 Jun 26 08:08:47 PM PDT 24 7005114300 ps
T1033 /workspace/coverage/default/0.chip_sw_rv_timer_irq.529844564 Jun 26 07:55:43 PM PDT 24 Jun 26 08:01:07 PM PDT 24 3462466800 ps
T196 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.2389193464 Jun 26 07:55:18 PM PDT 24 Jun 26 08:06:08 PM PDT 24 4385610156 ps
T1034 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.2714139004 Jun 26 08:22:24 PM PDT 24 Jun 26 08:33:00 PM PDT 24 4227714850 ps
T1035 /workspace/coverage/default/2.chip_tap_straps_prod.2443829271 Jun 26 08:17:57 PM PDT 24 Jun 26 08:20:52 PM PDT 24 2973226348 ps
T1036 /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.2850767763 Jun 26 08:08:22 PM PDT 24 Jun 26 08:20:38 PM PDT 24 5685926596 ps
T1037 /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.3220181449 Jun 26 07:55:53 PM PDT 24 Jun 26 07:59:11 PM PDT 24 2927156158 ps
T61 /workspace/coverage/default/1.chip_sw_alert_test.437069734 Jun 26 08:04:08 PM PDT 24 Jun 26 08:08:44 PM PDT 24 3010623840 ps
T326 /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.44345823 Jun 26 07:56:39 PM PDT 24 Jun 26 08:09:00 PM PDT 24 3740173186 ps
T157 /workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.3468595975 Jun 26 08:07:04 PM PDT 24 Jun 26 08:16:18 PM PDT 24 4748145296 ps
T1038 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.3404825612 Jun 26 08:15:33 PM PDT 24 Jun 26 08:21:37 PM PDT 24 3633340908 ps
T1039 /workspace/coverage/default/2.chip_sw_aes_idle.1786277198 Jun 26 08:13:20 PM PDT 24 Jun 26 08:18:30 PM PDT 24 2956307260 ps
T338 /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.3038093050 Jun 26 07:56:14 PM PDT 24 Jun 26 08:01:01 PM PDT 24 3259024107 ps
T1040 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.1818503874 Jun 26 08:03:24 PM PDT 24 Jun 26 09:24:44 PM PDT 24 18122505472 ps
T773 /workspace/coverage/default/22.chip_sw_all_escalation_resets.1306431081 Jun 26 08:24:38 PM PDT 24 Jun 26 08:35:54 PM PDT 24 5763786724 ps
T197 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.255162637 Jun 26 07:56:50 PM PDT 24 Jun 26 08:31:48 PM PDT 24 23156961896 ps
T38 /workspace/coverage/default/0.chip_sw_gpio.2221006342 Jun 26 07:54:22 PM PDT 24 Jun 26 08:02:07 PM PDT 24 3752726608 ps
T1041 /workspace/coverage/default/0.rom_volatile_raw_unlock.3089914038 Jun 26 07:59:03 PM PDT 24 Jun 26 08:00:48 PM PDT 24 2964066268 ps
T1042 /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.399886910 Jun 26 07:54:43 PM PDT 24 Jun 26 08:29:35 PM PDT 24 27018024520 ps
T77 /workspace/coverage/default/0.chip_jtag_mem_access.2194657747 Jun 26 07:48:36 PM PDT 24 Jun 26 08:16:09 PM PDT 24 13382227983 ps
T735 /workspace/coverage/default/62.chip_sw_all_escalation_resets.4047989399 Jun 26 08:27:47 PM PDT 24 Jun 26 08:37:15 PM PDT 24 6058835400 ps
T791 /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1333505415 Jun 26 08:29:15 PM PDT 24 Jun 26 08:36:00 PM PDT 24 3818963876 ps
T325 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.2363449550 Jun 26 07:55:44 PM PDT 24 Jun 26 08:07:28 PM PDT 24 4881327340 ps
T754 /workspace/coverage/default/30.chip_sw_all_escalation_resets.3930920561 Jun 26 08:26:13 PM PDT 24 Jun 26 08:37:03 PM PDT 24 5102295438 ps
T1043 /workspace/coverage/default/84.chip_sw_all_escalation_resets.1829534309 Jun 26 08:29:12 PM PDT 24 Jun 26 08:40:13 PM PDT 24 4649987914 ps
T1044 /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.2282202329 Jun 26 08:07:05 PM PDT 24 Jun 26 08:17:05 PM PDT 24 3320680276 ps
T1045 /workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.43552132 Jun 26 08:21:12 PM PDT 24 Jun 26 09:18:26 PM PDT 24 16370125204 ps
T1046 /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.3505315310 Jun 26 08:19:44 PM PDT 24 Jun 26 08:36:55 PM PDT 24 12291248503 ps
T23 /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3578356287 Jun 26 08:10:14 PM PDT 24 Jun 26 08:16:20 PM PDT 24 3605946705 ps
T1047 /workspace/coverage/default/3.chip_tap_straps_prod.1260088415 Jun 26 08:20:02 PM PDT 24 Jun 26 08:47:00 PM PDT 24 18210302535 ps
T1048 /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.2748761877 Jun 26 08:24:17 PM PDT 24 Jun 26 09:09:36 PM PDT 24 11148556463 ps
T1049 /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.3793390356 Jun 26 07:54:31 PM PDT 24 Jun 26 07:58:44 PM PDT 24 2996054780 ps
T750 /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.2477170511 Jun 26 08:24:26 PM PDT 24 Jun 26 08:32:27 PM PDT 24 4213259840 ps
T687 /workspace/coverage/default/1.chip_sw_pattgen_ios.245380722 Jun 26 08:01:29 PM PDT 24 Jun 26 08:06:50 PM PDT 24 2662565730 ps
T1050 /workspace/coverage/default/0.chip_sw_aes_idle.499388952 Jun 26 07:54:46 PM PDT 24 Jun 26 07:58:41 PM PDT 24 2695517950 ps
T795 /workspace/coverage/default/27.chip_sw_all_escalation_resets.4242369327 Jun 26 08:26:01 PM PDT 24 Jun 26 08:38:20 PM PDT 24 6283543552 ps
T1051 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.1500587298 Jun 26 07:57:18 PM PDT 24 Jun 26 08:04:08 PM PDT 24 5464963688 ps
T1052 /workspace/coverage/default/1.chip_sw_alert_handler_escalation.3128110681 Jun 26 08:03:03 PM PDT 24 Jun 26 08:13:41 PM PDT 24 5335250318 ps
T1053 /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.2086867744 Jun 26 08:06:31 PM PDT 24 Jun 26 08:16:39 PM PDT 24 4590965284 ps
T1054 /workspace/coverage/default/2.chip_sw_csrng_kat_test.1852162457 Jun 26 08:16:59 PM PDT 24 Jun 26 08:20:51 PM PDT 24 2499002496 ps
T52 /workspace/coverage/default/2.chip_sw_spi_device_tpm.1257003234 Jun 26 08:13:04 PM PDT 24 Jun 26 08:21:04 PM PDT 24 3253873317 ps
T1055 /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.695016752 Jun 26 07:55:04 PM PDT 24 Jun 26 07:58:24 PM PDT 24 2293286152 ps
T246 /workspace/coverage/default/1.chip_sw_power_sleep_load.2596389888 Jun 26 08:12:06 PM PDT 24 Jun 26 08:19:58 PM PDT 24 4757401256 ps
T1056 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.1784971015 Jun 26 08:09:50 PM PDT 24 Jun 26 09:49:36 PM PDT 24 37885325270 ps
T1057 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.453957046 Jun 26 08:04:41 PM PDT 24 Jun 26 08:27:38 PM PDT 24 5380863860 ps
T783 /workspace/coverage/default/21.chip_sw_all_escalation_resets.461955222 Jun 26 08:25:57 PM PDT 24 Jun 26 08:38:13 PM PDT 24 5208005424 ps
T310 /workspace/coverage/default/1.chip_plic_all_irqs_0.1210817203 Jun 26 08:07:29 PM PDT 24 Jun 26 08:29:30 PM PDT 24 6232422424 ps
T268 /workspace/coverage/default/4.chip_sw_data_integrity_escalation.40705798 Jun 26 08:20:37 PM PDT 24 Jun 26 08:35:59 PM PDT 24 5464431932 ps
T185 /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.2073263175 Jun 26 07:55:36 PM PDT 24 Jun 26 08:07:50 PM PDT 24 5020215853 ps
T299 /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.1847553613 Jun 26 08:26:18 PM PDT 24 Jun 26 08:34:22 PM PDT 24 4620774060 ps
T1058 /workspace/coverage/default/0.chip_sw_example_concurrency.994005229 Jun 26 07:53:55 PM PDT 24 Jun 26 07:58:24 PM PDT 24 2594018780 ps
T1059 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.3698544169 Jun 26 07:54:36 PM PDT 24 Jun 26 08:04:52 PM PDT 24 7074542740 ps
T1060 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2549930807 Jun 26 08:20:38 PM PDT 24 Jun 26 08:30:17 PM PDT 24 4714270058 ps
T1061 /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.2267221047 Jun 26 08:23:11 PM PDT 24 Jun 26 09:04:41 PM PDT 24 13546626500 ps
T1062 /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.864391648 Jun 26 08:16:35 PM PDT 24 Jun 26 08:51:21 PM PDT 24 24760529600 ps
T670 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.4172561378 Jun 26 08:04:21 PM PDT 24 Jun 26 08:08:43 PM PDT 24 3071107304 ps
T1063 /workspace/coverage/default/1.chip_sw_clkmgr_jitter.2315783411 Jun 26 08:06:21 PM PDT 24 Jun 26 08:10:19 PM PDT 24 3531341690 ps
T36 /workspace/coverage/default/0.chip_sw_usbdev_pincfg.571875489 Jun 26 07:55:21 PM PDT 24 Jun 26 10:07:42 PM PDT 24 31152853416 ps
T1064 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.2075240104 Jun 26 07:54:41 PM PDT 24 Jun 26 08:04:19 PM PDT 24 5535896148 ps
T1065 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1692038066 Jun 26 08:08:15 PM PDT 24 Jun 26 08:20:52 PM PDT 24 4685813643 ps
T198 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.3513212998 Jun 26 08:12:20 PM PDT 24 Jun 26 08:19:05 PM PDT 24 3337300620 ps
T247 /workspace/coverage/default/0.chip_sw_plic_sw_irq.1297440272 Jun 26 07:57:22 PM PDT 24 Jun 26 08:02:22 PM PDT 24 2463259920 ps
T647 /workspace/coverage/default/2.chip_sw_edn_boot_mode.866286886 Jun 26 08:15:04 PM PDT 24 Jun 26 08:24:53 PM PDT 24 2877853808 ps
T1066 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.684945455 Jun 26 08:12:38 PM PDT 24 Jun 26 08:39:55 PM PDT 24 18016684963 ps
T1067 /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.3911777446 Jun 26 08:27:47 PM PDT 24 Jun 26 08:35:33 PM PDT 24 3109832546 ps
T1068 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.2087829571 Jun 26 08:06:36 PM PDT 24 Jun 26 09:04:04 PM PDT 24 15653659418 ps
T1069 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.90476770 Jun 26 08:24:57 PM PDT 24 Jun 26 08:36:40 PM PDT 24 7666550408 ps
T1070 /workspace/coverage/default/0.chip_sw_edn_auto_mode.507578598 Jun 26 07:56:47 PM PDT 24 Jun 26 08:36:35 PM PDT 24 8579283568 ps
T1071 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.428660033 Jun 26 07:56:39 PM PDT 24 Jun 26 08:10:56 PM PDT 24 11693055590 ps
T188 /workspace/coverage/default/0.chip_jtag_csr_rw.758824424 Jun 26 07:48:37 PM PDT 24 Jun 26 08:06:54 PM PDT 24 11871488740 ps
T1072 /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.3307404066 Jun 26 08:19:06 PM PDT 24 Jun 26 08:25:16 PM PDT 24 6686684148 ps
T1073 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.1020576640 Jun 26 08:03:21 PM PDT 24 Jun 26 09:12:10 PM PDT 24 14944192460 ps
T1074 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1333903479 Jun 26 08:20:27 PM PDT 24 Jun 26 08:36:49 PM PDT 24 8447302659 ps
T1075 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3220708659 Jun 26 08:16:50 PM PDT 24 Jun 26 08:29:28 PM PDT 24 4108493436 ps
T744 /workspace/coverage/default/94.chip_sw_all_escalation_resets.2671209350 Jun 26 08:29:06 PM PDT 24 Jun 26 08:37:06 PM PDT 24 5001031778 ps
T300 /workspace/coverage/default/43.chip_sw_all_escalation_resets.1347938028 Jun 26 08:25:47 PM PDT 24 Jun 26 08:34:43 PM PDT 24 4729129640 ps
T1076 /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3583020515 Jun 26 08:02:43 PM PDT 24 Jun 26 08:12:32 PM PDT 24 19095672584 ps
T727 /workspace/coverage/default/39.chip_sw_all_escalation_resets.2017841534 Jun 26 08:25:34 PM PDT 24 Jun 26 08:37:20 PM PDT 24 5138165600 ps
T1077 /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.2880802956 Jun 26 07:59:59 PM PDT 24 Jun 26 08:27:05 PM PDT 24 9411641464 ps
T1078 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.3531956399 Jun 26 07:57:07 PM PDT 24 Jun 26 09:01:43 PM PDT 24 13521966416 ps
T229 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.3232662909 Jun 26 08:14:20 PM PDT 24 Jun 26 09:53:05 PM PDT 24 50225904515 ps
T1079 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.3961252815 Jun 26 08:16:46 PM PDT 24 Jun 26 08:25:17 PM PDT 24 3842323464 ps
T774 /workspace/coverage/default/6.chip_sw_all_escalation_resets.2913394584 Jun 26 08:22:40 PM PDT 24 Jun 26 08:34:17 PM PDT 24 6279180106 ps
T1080 /workspace/coverage/default/0.chip_sw_aes_enc.2116171186 Jun 26 07:55:54 PM PDT 24 Jun 26 08:00:56 PM PDT 24 3371548792 ps
T769 /workspace/coverage/default/91.chip_sw_all_escalation_resets.3763033005 Jun 26 08:29:05 PM PDT 24 Jun 26 08:38:23 PM PDT 24 5673180800 ps
T757 /workspace/coverage/default/96.chip_sw_all_escalation_resets.653590 Jun 26 08:28:43 PM PDT 24 Jun 26 08:37:54 PM PDT 24 6034987500 ps
T1081 /workspace/coverage/default/1.chip_tap_straps_testunlock0.1726120429 Jun 26 08:07:55 PM PDT 24 Jun 26 08:17:24 PM PDT 24 5388790338 ps
T1082 /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.260494888 Jun 26 08:28:15 PM PDT 24 Jun 26 08:34:21 PM PDT 24 3803686082 ps
T1083 /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.1184735548 Jun 26 07:58:26 PM PDT 24 Jun 26 08:03:04 PM PDT 24 3029144860 ps
T1084 /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.2612831929 Jun 26 08:16:51 PM PDT 24 Jun 26 08:27:09 PM PDT 24 4588801000 ps
T1085 /workspace/coverage/default/1.chip_sw_aes_masking_off.2078008854 Jun 26 08:04:03 PM PDT 24 Jun 26 08:09:02 PM PDT 24 2790990411 ps
T651 /workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.1380980097 Jun 26 08:22:35 PM PDT 24 Jun 26 10:47:10 PM PDT 24 41195165464 ps
T1086 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.3401128584 Jun 26 07:54:46 PM PDT 24 Jun 26 08:19:54 PM PDT 24 7097301828 ps
T717 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.2634806246 Jun 26 08:15:17 PM PDT 24 Jun 26 08:22:08 PM PDT 24 3543919792 ps
T741 /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.3904451226 Jun 26 08:27:19 PM PDT 24 Jun 26 08:32:16 PM PDT 24 3486356472 ps
T1087 /workspace/coverage/default/0.rom_e2e_static_critical.1504394544 Jun 26 08:04:02 PM PDT 24 Jun 26 09:20:18 PM PDT 24 17448883944 ps
T1088 /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.17672394 Jun 26 08:05:17 PM PDT 24 Jun 26 08:15:22 PM PDT 24 5478763380 ps
T1089 /workspace/coverage/default/86.chip_sw_all_escalation_resets.3483551048 Jun 26 08:30:09 PM PDT 24 Jun 26 08:40:07 PM PDT 24 4756725784 ps
T1090 /workspace/coverage/default/0.chip_sw_uart_tx_rx.2316188950 Jun 26 07:53:45 PM PDT 24 Jun 26 08:03:59 PM PDT 24 4305918884 ps
T1091 /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.827446871 Jun 26 08:28:57 PM PDT 24 Jun 26 08:34:40 PM PDT 24 3367964184 ps
T1092 /workspace/coverage/default/1.chip_sw_csrng_kat_test.4262301080 Jun 26 08:04:21 PM PDT 24 Jun 26 08:08:28 PM PDT 24 2647947270 ps
T745 /workspace/coverage/default/90.chip_sw_all_escalation_resets.2596386832 Jun 26 08:28:37 PM PDT 24 Jun 26 08:35:28 PM PDT 24 4805144640 ps
T1093 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3855486338 Jun 26 07:55:17 PM PDT 24 Jun 26 08:05:15 PM PDT 24 4081767360 ps
T1094 /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.848845115 Jun 26 08:11:43 PM PDT 24 Jun 26 08:14:48 PM PDT 24 2467307784 ps
T1095 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.2633937638 Jun 26 07:54:12 PM PDT 24 Jun 26 08:06:11 PM PDT 24 4630297416 ps
T1096 /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1627490307 Jun 26 08:22:16 PM PDT 24 Jun 26 08:29:32 PM PDT 24 4002176496 ps
T1097 /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.2288887833 Jun 26 07:56:10 PM PDT 24 Jun 26 08:24:43 PM PDT 24 12518124666 ps
T317 /workspace/coverage/default/2.chip_sw_entropy_src_csrng.874453105 Jun 26 08:15:17 PM PDT 24 Jun 26 08:36:58 PM PDT 24 5388593408 ps
T1098 /workspace/coverage/default/0.chip_sw_hmac_multistream.817970805 Jun 26 07:58:09 PM PDT 24 Jun 26 08:33:54 PM PDT 24 7903898584 ps
T339 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2562573926 Jun 26 08:19:18 PM PDT 24 Jun 26 08:30:34 PM PDT 24 4711515440 ps
T1099 /workspace/coverage/default/1.chip_sw_aes_enc.2957404931 Jun 26 08:04:29 PM PDT 24 Jun 26 08:09:52 PM PDT 24 3083192324 ps
T1100 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.1998539717 Jun 26 08:08:36 PM PDT 24 Jun 26 08:17:04 PM PDT 24 6420384264 ps
T1101 /workspace/coverage/default/2.chip_sw_otbn_smoketest.3116569470 Jun 26 08:19:34 PM PDT 24 Jun 26 08:36:56 PM PDT 24 6269415000 ps
T1102 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.3913072205 Jun 26 08:08:01 PM PDT 24 Jun 26 08:25:37 PM PDT 24 10217312543 ps
T1103 /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.1436232437 Jun 26 08:13:13 PM PDT 24 Jun 26 08:22:23 PM PDT 24 4618038952 ps
T1104 /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.1006881415 Jun 26 08:26:32 PM PDT 24 Jun 26 08:32:15 PM PDT 24 3834897796 ps
T260 /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.1447420350 Jun 26 08:00:16 PM PDT 24 Jun 26 08:10:39 PM PDT 24 4882025028 ps
T1105 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.398878070 Jun 26 07:56:51 PM PDT 24 Jun 26 08:36:58 PM PDT 24 11681395592 ps
T778 /workspace/coverage/default/40.chip_sw_all_escalation_resets.1967219603 Jun 26 08:25:31 PM PDT 24 Jun 26 08:35:24 PM PDT 24 4619884120 ps
T1106 /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.622829242 Jun 26 07:59:17 PM PDT 24 Jun 26 08:03:21 PM PDT 24 2900317200 ps
T1107 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.676141160 Jun 26 08:03:05 PM PDT 24 Jun 26 08:31:09 PM PDT 24 7152390206 ps
T146 /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.217171303 Jun 26 07:54:21 PM PDT 24 Jun 26 07:56:10 PM PDT 24 2191094513 ps
T199 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.2535554156 Jun 26 08:12:47 PM PDT 24 Jun 26 08:36:55 PM PDT 24 21266499992 ps
T1108 /workspace/coverage/default/74.chip_sw_all_escalation_resets.461396006 Jun 26 08:27:52 PM PDT 24 Jun 26 08:39:26 PM PDT 24 4888234760 ps
T1109 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.3190239743 Jun 26 08:14:45 PM PDT 24 Jun 26 08:28:04 PM PDT 24 5201464440 ps
T648 /workspace/coverage/default/1.chip_sw_edn_boot_mode.2762448462 Jun 26 08:03:44 PM PDT 24 Jun 26 08:14:28 PM PDT 24 2970466792 ps
T301 /workspace/coverage/default/24.chip_sw_all_escalation_resets.1531382193 Jun 26 08:24:17 PM PDT 24 Jun 26 08:35:03 PM PDT 24 4877634732 ps
T189 /workspace/coverage/default/2.chip_jtag_csr_rw.3773445136 Jun 26 08:09:39 PM PDT 24 Jun 26 08:29:58 PM PDT 24 11834752508 ps
T1110 /workspace/coverage/default/70.chip_sw_all_escalation_resets.3745579969 Jun 26 08:32:05 PM PDT 24 Jun 26 08:42:25 PM PDT 24 5889409862 ps
T777 /workspace/coverage/default/57.chip_sw_all_escalation_resets.1443060392 Jun 26 08:28:18 PM PDT 24 Jun 26 08:36:47 PM PDT 24 5783018528 ps
T1111 /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.394552275 Jun 26 07:53:58 PM PDT 24 Jun 26 08:21:46 PM PDT 24 9152946982 ps
T1112 /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.917932465 Jun 26 08:21:22 PM PDT 24 Jun 26 08:27:12 PM PDT 24 6274094526 ps
T1113 /workspace/coverage/default/2.chip_sw_hmac_oneshot.652773606 Jun 26 08:16:17 PM PDT 24 Jun 26 08:22:44 PM PDT 24 3184258472 ps
T1114 /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.2347267694 Jun 26 08:17:01 PM PDT 24 Jun 26 08:25:20 PM PDT 24 4423985608 ps
T720 /workspace/coverage/default/25.chip_sw_all_escalation_resets.189288897 Jun 26 08:25:10 PM PDT 24 Jun 26 08:36:02 PM PDT 24 5916182500 ps
T649 /workspace/coverage/default/0.chip_sw_edn_boot_mode.778375683 Jun 26 07:55:13 PM PDT 24 Jun 26 08:03:19 PM PDT 24 3041356856 ps
T693 /workspace/coverage/default/13.chip_sw_all_escalation_resets.302229825 Jun 26 08:23:37 PM PDT 24 Jun 26 08:32:30 PM PDT 24 5514117558 ps
T1115 /workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.2745481572 Jun 26 07:59:54 PM PDT 24 Jun 26 08:02:50 PM PDT 24 2811234976 ps
T1116 /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.16568005 Jun 26 08:00:41 PM PDT 24 Jun 26 08:03:58 PM PDT 24 3149801356 ps
T1117 /workspace/coverage/default/82.chip_sw_all_escalation_resets.3377706625 Jun 26 08:28:42 PM PDT 24 Jun 26 08:40:02 PM PDT 24 6203803266 ps
T1118 /workspace/coverage/default/0.chip_sw_otbn_randomness.2121754001 Jun 26 07:59:34 PM PDT 24 Jun 26 08:15:03 PM PDT 24 5892372960 ps
T328 /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.2415377942 Jun 26 08:12:36 PM PDT 24 Jun 26 08:23:46 PM PDT 24 4309834868 ps
T1119 /workspace/coverage/default/2.chip_sw_data_integrity_escalation.3570961588 Jun 26 08:10:52 PM PDT 24 Jun 26 08:23:21 PM PDT 24 6102825698 ps
T1120 /workspace/coverage/default/0.chip_sw_power_sleep_load.2967176483 Jun 26 07:57:59 PM PDT 24 Jun 26 08:03:28 PM PDT 24 4113481144 ps
T126 /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.3239929668 Jun 26 08:21:11 PM PDT 24 Jun 26 08:39:40 PM PDT 24 8872890264 ps
T793 /workspace/coverage/default/3.chip_sw_all_escalation_resets.405746334 Jun 26 08:19:31 PM PDT 24 Jun 26 08:31:19 PM PDT 24 5914224750 ps
T1121 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.2236733393 Jun 26 08:08:32 PM PDT 24 Jun 26 08:12:18 PM PDT 24 3051298108 ps
T718 /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.2042002591 Jun 26 08:27:04 PM PDT 24 Jun 26 08:34:23 PM PDT 24 3432000680 ps
T1122 /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.1999923671 Jun 26 08:24:24 PM PDT 24 Jun 26 08:30:56 PM PDT 24 4298484128 ps
T1123 /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2748044978 Jun 26 07:57:12 PM PDT 24 Jun 26 08:03:41 PM PDT 24 18173841262 ps
T1124 /workspace/coverage/default/1.chip_sw_aes_smoketest.177663828 Jun 26 08:10:13 PM PDT 24 Jun 26 08:14:11 PM PDT 24 3128982772 ps
T756 /workspace/coverage/default/89.chip_sw_all_escalation_resets.4032107672 Jun 26 08:31:52 PM PDT 24 Jun 26 08:40:55 PM PDT 24 5632157522 ps
T314 /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.1673656383 Jun 26 08:03:00 PM PDT 24 Jun 26 08:37:43 PM PDT 24 12723354472 ps
T1125 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.1308586870 Jun 26 08:12:08 PM PDT 24 Jun 26 08:23:19 PM PDT 24 4057175460 ps
T1126 /workspace/coverage/default/77.chip_sw_all_escalation_resets.18464240 Jun 26 08:29:06 PM PDT 24 Jun 26 08:40:30 PM PDT 24 4952885904 ps
T1127 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.1781656436 Jun 26 08:23:16 PM PDT 24 Jun 26 09:16:04 PM PDT 24 14889136012 ps
T294 /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1784121184 Jun 26 08:17:56 PM PDT 24 Jun 26 08:28:04 PM PDT 24 5419763034 ps
T1128 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.3183983809 Jun 26 08:04:49 PM PDT 24 Jun 26 09:20:17 PM PDT 24 16945858920 ps
T1129 /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.121512958 Jun 26 08:15:49 PM PDT 24 Jun 26 08:23:49 PM PDT 24 3817295332 ps
T1130 /workspace/coverage/default/1.chip_sw_kmac_smoketest.3106383848 Jun 26 08:10:31 PM PDT 24 Jun 26 08:15:20 PM PDT 24 3387303792 ps
T1131 /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.4270983232 Jun 26 08:19:27 PM PDT 24 Jun 26 08:26:49 PM PDT 24 3530005580 ps
T796 /workspace/coverage/default/19.chip_sw_all_escalation_resets.247087648 Jun 26 08:25:59 PM PDT 24 Jun 26 08:37:03 PM PDT 24 5989865206 ps
T499 /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.3070389580 Jun 26 08:15:24 PM PDT 24 Jun 26 08:28:23 PM PDT 24 4498093618 ps
T1132 /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.3542582918 Jun 26 08:07:44 PM PDT 24 Jun 26 08:27:06 PM PDT 24 7727044540 ps
T1133 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.365349321 Jun 26 08:11:47 PM PDT 24 Jun 26 08:20:14 PM PDT 24 3739740937 ps
T1134 /workspace/coverage/default/2.chip_sw_aon_timer_irq.3505510654 Jun 26 08:15:18 PM PDT 24 Jun 26 08:23:00 PM PDT 24 4049348952 ps
T1135 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.921220488 Jun 26 08:07:04 PM PDT 24 Jun 26 08:20:27 PM PDT 24 7770582208 ps
T1136 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.2540610928 Jun 26 08:03:18 PM PDT 24 Jun 26 09:07:03 PM PDT 24 16089179648 ps
T1137 /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2755545112 Jun 26 07:56:07 PM PDT 24 Jun 26 11:26:46 PM PDT 24 255683379930 ps
T1138 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.1402342590 Jun 26 08:15:02 PM PDT 24 Jun 26 08:20:31 PM PDT 24 3826059686 ps
T1139 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.3105810831 Jun 26 08:22:31 PM PDT 24 Jun 26 09:00:01 PM PDT 24 12861475110 ps
T1140 /workspace/coverage/default/81.chip_sw_all_escalation_resets.592535427 Jun 26 08:28:45 PM PDT 24 Jun 26 08:39:06 PM PDT 24 4287193700 ps
T789 /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.1871895359 Jun 26 08:25:35 PM PDT 24 Jun 26 08:33:37 PM PDT 24 3677245500 ps
T1141 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.2727131868 Jun 26 08:22:16 PM PDT 24 Jun 26 09:21:20 PM PDT 24 15178252000 ps
T1142 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.794756702 Jun 26 08:02:56 PM PDT 24 Jun 26 08:53:04 PM PDT 24 20853065754 ps
T1143 /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.1837326463 Jun 26 08:15:41 PM PDT 24 Jun 26 08:18:53 PM PDT 24 1979868094 ps
T1144 /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.56413009 Jun 26 08:24:51 PM PDT 24 Jun 26 08:34:51 PM PDT 24 3799771500 ps
T1145 /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.3968581699 Jun 26 08:13:00 PM PDT 24 Jun 26 08:52:43 PM PDT 24 26328283099 ps
T500 /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.2571555689 Jun 26 07:55:41 PM PDT 24 Jun 26 08:11:36 PM PDT 24 5142765480 ps
T1146 /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.2315358487 Jun 26 07:55:44 PM PDT 24 Jun 26 08:05:23 PM PDT 24 3936462664 ps
T653 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.3539734783 Jun 26 08:08:14 PM PDT 24 Jun 26 08:19:16 PM PDT 24 4907558897 ps
T1147 /workspace/coverage/default/2.chip_sw_flash_ctrl_access.1607044804 Jun 26 08:13:17 PM PDT 24 Jun 26 08:33:43 PM PDT 24 5021493304 ps
T1148 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2226556339 Jun 26 08:11:36 PM PDT 24 Jun 26 08:24:21 PM PDT 24 4781112568 ps
T1149 /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.2274319385 Jun 26 07:54:05 PM PDT 24 Jun 26 07:58:03 PM PDT 24 2907963500 ps
T1150 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.100786873 Jun 26 08:16:02 PM PDT 24 Jun 26 08:59:33 PM PDT 24 12169879350 ps
T97 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2664640544 Jun 26 08:08:33 PM PDT 24 Jun 26 08:40:05 PM PDT 24 24210948868 ps
T1151 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.2896171602 Jun 26 08:03:21 PM PDT 24 Jun 26 09:12:54 PM PDT 24 16054140358 ps
T1152 /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.1112891298 Jun 26 08:02:04 PM PDT 24 Jun 26 08:06:49 PM PDT 24 4484669980 ps
T1153 /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.2278168136 Jun 26 07:56:06 PM PDT 24 Jun 26 08:10:12 PM PDT 24 5403920600 ps
T1154 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.1473567318 Jun 26 07:54:17 PM PDT 24 Jun 26 08:05:40 PM PDT 24 6477350674 ps
T1155 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.999391209 Jun 26 08:22:56 PM PDT 24 Jun 26 09:09:42 PM PDT 24 15026926448 ps
T1156 /workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.902786735 Jun 26 07:55:30 PM PDT 24 Jun 26 09:29:16 PM PDT 24 26960514260 ps
T1157 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.2098087202 Jun 26 07:58:41 PM PDT 24 Jun 26 08:19:39 PM PDT 24 6246790528 ps
T222 /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.91281015 Jun 26 07:58:05 PM PDT 24 Jun 26 08:50:27 PM PDT 24 12817184872 ps
T315 /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.3388951098 Jun 26 07:55:16 PM PDT 24 Jun 26 08:23:41 PM PDT 24 15093531880 ps
T788 /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.117201940 Jun 26 08:27:19 PM PDT 24 Jun 26 08:33:38 PM PDT 24 4261993126 ps
T1158 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.535324099 Jun 26 08:09:42 PM PDT 24 Jun 26 08:15:26 PM PDT 24 2828230984 ps
T1159 /workspace/coverage/default/0.chip_tap_straps_prod.2498725362 Jun 26 07:56:13 PM PDT 24 Jun 26 08:05:05 PM PDT 24 5987847870 ps
T1160 /workspace/coverage/default/1.chip_sw_edn_kat.1421768812 Jun 26 08:05:27 PM PDT 24 Jun 26 08:16:23 PM PDT 24 3552082040 ps
T1161 /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.3019643082 Jun 26 08:18:05 PM PDT 24 Jun 26 08:25:07 PM PDT 24 3460340036 ps
T1162 /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.2882184371 Jun 26 08:05:37 PM PDT 24 Jun 26 08:08:47 PM PDT 24 2989298192 ps
T1163 /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.2880316348 Jun 26 08:23:04 PM PDT 24 Jun 26 08:37:07 PM PDT 24 10669466386 ps
T1164 /workspace/coverage/default/0.chip_sw_gpio_smoketest.3634620490 Jun 26 08:01:59 PM PDT 24 Jun 26 08:05:46 PM PDT 24 2830070877 ps
T1165 /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.2697774690 Jun 26 08:20:36 PM PDT 24 Jun 26 08:43:54 PM PDT 24 8647059310 ps
T1166 /workspace/coverage/default/1.rom_e2e_asm_init_dev.2657299562 Jun 26 08:14:29 PM PDT 24 Jun 26 09:18:05 PM PDT 24 16257491640 ps
T784 /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.1767867910 Jun 26 08:25:52 PM PDT 24 Jun 26 08:32:50 PM PDT 24 3679664850 ps
T1167 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1447063321 Jun 26 07:58:01 PM PDT 24 Jun 26 08:16:12 PM PDT 24 7475919718 ps
T1168 /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.3720847564 Jun 26 08:01:34 PM PDT 24 Jun 26 08:11:06 PM PDT 24 4418700280 ps
T219 /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.3324636564 Jun 26 07:56:07 PM PDT 24 Jun 26 08:18:15 PM PDT 24 7667630736 ps
T1169 /workspace/coverage/default/2.chip_sw_power_sleep_load.3282415824 Jun 26 08:19:22 PM PDT 24 Jun 26 08:28:46 PM PDT 24 10393186952 ps
T1170 /workspace/coverage/default/1.chip_sw_aes_entropy.2856248383 Jun 26 08:03:31 PM PDT 24 Jun 26 08:06:54 PM PDT 24 3070440614 ps
T719 /workspace/coverage/default/79.chip_sw_all_escalation_resets.3126992937 Jun 26 08:31:09 PM PDT 24 Jun 26 08:39:13 PM PDT 24 5794378232 ps
T1171 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3687985219 Jun 26 08:14:18 PM PDT 24 Jun 26 08:22:05 PM PDT 24 6734696200 ps
T1172 /workspace/coverage/default/92.chip_sw_all_escalation_resets.3629585447 Jun 26 08:29:27 PM PDT 24 Jun 26 08:38:44 PM PDT 24 5483465108 ps
T1173 /workspace/coverage/default/0.chip_sw_ast_clk_outputs.746702323 Jun 26 07:56:44 PM PDT 24 Jun 26 08:11:47 PM PDT 24 6905786728 ps
T1174 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.2186093711 Jun 26 07:54:12 PM PDT 24 Jun 26 08:13:07 PM PDT 24 8535744672 ps
T1175 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2618468089 Jun 26 07:55:29 PM PDT 24 Jun 26 08:16:25 PM PDT 24 11807734200 ps
T158 /workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.1862438702 Jun 26 07:56:38 PM PDT 24 Jun 26 08:05:24 PM PDT 24 4534002236 ps
T1176 /workspace/coverage/default/0.chip_sw_clkmgr_jitter.469954594 Jun 26 07:56:34 PM PDT 24 Jun 26 08:01:05 PM PDT 24 3182555016 ps
T1177 /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.1476788227 Jun 26 08:11:31 PM PDT 24 Jun 26 08:18:09 PM PDT 24 6948614825 ps
T1178 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.1471671117 Jun 26 08:04:17 PM PDT 24 Jun 26 09:19:03 PM PDT 24 16360465874 ps
T1179 /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.3908744022 Jun 26 08:21:01 PM PDT 24 Jun 26 09:01:07 PM PDT 24 13043600942 ps
T725 /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.260759300 Jun 26 08:27:21 PM PDT 24 Jun 26 08:34:05 PM PDT 24 3829101724 ps
T738 /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.1650798842 Jun 26 08:25:29 PM PDT 24 Jun 26 08:31:41 PM PDT 24 3811510552 ps
T232 /workspace/coverage/default/1.chip_sw_flash_init.4038816254 Jun 26 08:00:14 PM PDT 24 Jun 26 08:33:48 PM PDT 24 16821146339 ps
T1180 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.3823215839 Jun 26 07:55:55 PM PDT 24 Jun 26 08:24:33 PM PDT 24 6404229008 ps
T200 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.3201011119 Jun 26 08:14:07 PM PDT 24 Jun 26 08:18:59 PM PDT 24 2981697330 ps
T1181 /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.3858774963 Jun 26 08:13:37 PM PDT 24 Jun 26 08:23:44 PM PDT 24 5387554344 ps
T761 /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.1462657345 Jun 26 08:29:32 PM PDT 24 Jun 26 08:36:09 PM PDT 24 3903443800 ps
T1182 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2106801521 Jun 26 07:56:22 PM PDT 24 Jun 26 08:08:10 PM PDT 24 5249702232 ps
T1183 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3903337950 Jun 26 07:54:05 PM PDT 24 Jun 26 08:03:25 PM PDT 24 4391850261 ps
T148 /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1914869371 Jun 26 08:14:07 PM PDT 24 Jun 26 08:15:54 PM PDT 24 1753509609 ps
T1184 /workspace/coverage/default/3.chip_sw_uart_tx_rx.27139081 Jun 26 08:20:09 PM PDT 24 Jun 26 08:32:36 PM PDT 24 4995555216 ps
T1185 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2698267056 Jun 26 08:13:02 PM PDT 24 Jun 26 08:39:45 PM PDT 24 14479771534 ps
T1186 /workspace/coverage/default/54.chip_sw_all_escalation_resets.607199307 Jun 26 08:26:58 PM PDT 24 Jun 26 08:35:30 PM PDT 24 4144858200 ps
T73 /workspace/coverage/default/0.chip_sw_usbdev_pullup.1353620501 Jun 26 07:55:39 PM PDT 24 Jun 26 08:01:12 PM PDT 24 2822027380 ps
T1187 /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.3840903195 Jun 26 08:02:01 PM PDT 24 Jun 26 08:08:41 PM PDT 24 3524985857 ps
T1188 /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.1429543465 Jun 26 08:25:09 PM PDT 24 Jun 26 08:49:59 PM PDT 24 7998356440 ps
T1189 /workspace/coverage/default/1.chip_sw_aes_idle.1463464743 Jun 26 08:04:39 PM PDT 24 Jun 26 08:09:02 PM PDT 24 2975766312 ps
T1190 /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.2825391333 Jun 26 08:14:03 PM PDT 24 Jun 26 08:23:53 PM PDT 24 5103739127 ps
T1191 /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.1218926455 Jun 26 07:55:12 PM PDT 24 Jun 26 08:04:37 PM PDT 24 4684555000 ps
T1192 /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.3823136121 Jun 26 08:19:52 PM PDT 24 Jun 26 08:38:17 PM PDT 24 5757263480 ps
T1193 /workspace/coverage/default/33.chip_sw_all_escalation_resets.3958357040 Jun 26 08:25:52 PM PDT 24 Jun 26 08:36:22 PM PDT 24 4683005718 ps
T1194 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.725356147 Jun 26 07:54:27 PM PDT 24 Jun 26 08:08:51 PM PDT 24 4518198618 ps
T128 /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.117446989 Jun 26 08:20:14 PM PDT 24 Jun 26 08:30:25 PM PDT 24 3951775590 ps
T732 /workspace/coverage/default/31.chip_sw_all_escalation_resets.2091131642 Jun 26 08:26:00 PM PDT 24 Jun 26 08:37:31 PM PDT 24 5820925984 ps
T98 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1521068234 Jun 26 07:55:44 PM PDT 24 Jun 26 08:25:43 PM PDT 24 27238772776 ps
T770 /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3474024484 Jun 26 08:27:16 PM PDT 24 Jun 26 08:34:48 PM PDT 24 3484209432 ps
T190 /workspace/coverage/default/2.chip_jtag_mem_access.3812442978 Jun 26 08:09:49 PM PDT 24 Jun 26 08:39:28 PM PDT 24 13586860926 ps
T1195 /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.631511905 Jun 26 08:02:39 PM PDT 24 Jun 26 08:13:35 PM PDT 24 4816047150 ps
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