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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.14 95.59 93.98 95.45 94.77 97.53 99.53


Total test records in report: 2877
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T111 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.2486981095 Jun 27 08:31:29 PM PDT 24 Jun 27 09:18:55 PM PDT 24 16178390320 ps
T212 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.2183726941 Jun 27 08:36:17 PM PDT 24 Jun 27 08:47:21 PM PDT 24 4780983156 ps
T716 /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.4292964604 Jun 27 08:40:46 PM PDT 24 Jun 27 08:47:51 PM PDT 24 3716217064 ps
T879 /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.3224954505 Jun 27 08:36:53 PM PDT 24 Jun 27 08:54:11 PM PDT 24 5697246806 ps
T277 /workspace/coverage/default/3.chip_sw_data_integrity_escalation.57936914 Jun 27 08:44:15 PM PDT 24 Jun 27 08:58:05 PM PDT 24 4235153500 ps
T167 /workspace/coverage/default/63.chip_sw_all_escalation_resets.402057858 Jun 27 08:52:38 PM PDT 24 Jun 27 09:02:00 PM PDT 24 5103639864 ps
T152 /workspace/coverage/default/2.chip_sw_power_idle_load.769298592 Jun 27 08:41:28 PM PDT 24 Jun 27 08:53:02 PM PDT 24 4986426292 ps
T280 /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.3303486020 Jun 27 08:35:33 PM PDT 24 Jun 27 08:39:14 PM PDT 24 2923136080 ps
T281 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1208913692 Jun 27 08:24:10 PM PDT 24 Jun 27 08:41:30 PM PDT 24 14366848523 ps
T282 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3999308672 Jun 27 08:23:55 PM PDT 24 Jun 27 08:36:52 PM PDT 24 4946092836 ps
T229 /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.3933680625 Jun 27 08:38:28 PM PDT 24 Jun 27 08:59:03 PM PDT 24 7118851970 ps
T283 /workspace/coverage/default/8.chip_sw_all_escalation_resets.3714419849 Jun 27 08:47:14 PM PDT 24 Jun 27 08:57:58 PM PDT 24 5037745634 ps
T284 /workspace/coverage/default/0.chip_sw_aes_idle.324103414 Jun 27 08:17:41 PM PDT 24 Jun 27 08:21:42 PM PDT 24 2875086848 ps
T285 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.780296393 Jun 27 08:17:56 PM PDT 24 Jun 27 08:29:01 PM PDT 24 4295245486 ps
T880 /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.2294298327 Jun 27 08:26:07 PM PDT 24 Jun 27 09:23:44 PM PDT 24 15602771940 ps
T881 /workspace/coverage/default/2.chip_sw_example_concurrency.1762251974 Jun 27 08:33:24 PM PDT 24 Jun 27 08:37:59 PM PDT 24 2760252710 ps
T882 /workspace/coverage/default/1.chip_sw_otbn_smoketest.3974981319 Jun 27 08:32:29 PM PDT 24 Jun 27 08:52:06 PM PDT 24 5795818938 ps
T274 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.380240349 Jun 27 08:17:19 PM PDT 24 Jun 27 08:19:08 PM PDT 24 2798453141 ps
T883 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.3905700380 Jun 27 08:27:06 PM PDT 24 Jun 27 09:24:29 PM PDT 24 11224813868 ps
T384 /workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.3662480943 Jun 27 08:19:13 PM PDT 24 Jun 27 08:21:44 PM PDT 24 2555730050 ps
T143 /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.185887829 Jun 27 08:18:52 PM PDT 24 Jun 27 08:27:58 PM PDT 24 7200514595 ps
T747 /workspace/coverage/default/69.chip_sw_all_escalation_resets.1292796352 Jun 27 08:53:40 PM PDT 24 Jun 27 09:03:20 PM PDT 24 4562945600 ps
T705 /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.1916699803 Jun 27 08:46:39 PM PDT 24 Jun 27 08:54:59 PM PDT 24 4334963376 ps
T884 /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.3366799487 Jun 27 08:36:25 PM PDT 24 Jun 27 08:45:58 PM PDT 24 6674039192 ps
T289 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.376049069 Jun 27 08:18:26 PM PDT 24 Jun 27 08:27:05 PM PDT 24 4004051805 ps
T110 /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.449508058 Jun 27 08:20:39 PM PDT 24 Jun 27 08:31:32 PM PDT 24 18939713812 ps
T337 /workspace/coverage/default/4.chip_sw_uart_tx_rx.121066794 Jun 27 08:44:29 PM PDT 24 Jun 27 08:57:39 PM PDT 24 4754601654 ps
T885 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.2995783160 Jun 27 08:28:38 PM PDT 24 Jun 27 08:43:26 PM PDT 24 12255731227 ps
T168 /workspace/coverage/default/88.chip_sw_all_escalation_resets.3347215219 Jun 27 08:55:05 PM PDT 24 Jun 27 09:03:48 PM PDT 24 5431237480 ps
T717 /workspace/coverage/default/2.chip_sw_ast_clk_outputs.348777220 Jun 27 08:40:35 PM PDT 24 Jun 27 09:00:21 PM PDT 24 7918196446 ps
T310 /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.3809999789 Jun 27 08:48:45 PM PDT 24 Jun 27 09:14:47 PM PDT 24 8058317040 ps
T240 /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.4292444648 Jun 27 08:16:34 PM PDT 24 Jun 27 10:00:42 PM PDT 24 49186832724 ps
T715 /workspace/coverage/default/41.chip_sw_all_escalation_resets.3057916067 Jun 27 08:50:58 PM PDT 24 Jun 27 08:59:23 PM PDT 24 5345892852 ps
T886 /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.3377381721 Jun 27 08:47:41 PM PDT 24 Jun 27 09:32:16 PM PDT 24 11292029160 ps
T326 /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.391256615 Jun 27 08:47:17 PM PDT 24 Jun 27 09:13:32 PM PDT 24 8214792946 ps
T887 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1916183874 Jun 27 08:18:49 PM PDT 24 Jun 27 08:29:24 PM PDT 24 3955863784 ps
T314 /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.3914237129 Jun 27 08:29:15 PM PDT 24 Jun 27 09:01:51 PM PDT 24 13554741520 ps
T888 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.2437832386 Jun 27 08:40:42 PM PDT 24 Jun 27 08:47:21 PM PDT 24 3588333800 ps
T10 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.1582493442 Jun 27 08:33:02 PM PDT 24 Jun 27 09:04:48 PM PDT 24 22825701804 ps
T889 /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.3786982391 Jun 27 08:17:15 PM PDT 24 Jun 27 08:25:37 PM PDT 24 5712253812 ps
T144 /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.103141032 Jun 27 08:24:05 PM PDT 24 Jun 27 08:31:43 PM PDT 24 8688684192 ps
T890 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.2113951946 Jun 27 08:18:16 PM PDT 24 Jun 27 09:24:22 PM PDT 24 18119041852 ps
T230 /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.3105672304 Jun 27 08:18:38 PM PDT 24 Jun 27 08:46:39 PM PDT 24 9669143658 ps
T891 /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.3481860572 Jun 27 08:23:24 PM PDT 24 Jun 27 08:34:17 PM PDT 24 5915976304 ps
T160 /workspace/coverage/default/0.chip_plic_all_irqs_10.2367326346 Jun 27 08:20:59 PM PDT 24 Jun 27 08:30:47 PM PDT 24 3536775048 ps
T892 /workspace/coverage/default/2.chip_sw_aes_enc.198695258 Jun 27 08:36:56 PM PDT 24 Jun 27 08:41:16 PM PDT 24 3281208076 ps
T893 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.583481649 Jun 27 08:40:13 PM PDT 24 Jun 27 08:55:01 PM PDT 24 7417940022 ps
T9 /workspace/coverage/default/2.chip_jtag_csr_rw.2385386876 Jun 27 08:33:08 PM PDT 24 Jun 27 09:00:44 PM PDT 24 12509949900 ps
T402 /workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.3683187457 Jun 27 08:47:03 PM PDT 24 Jun 27 10:31:01 PM PDT 24 26124068648 ps
T403 /workspace/coverage/default/36.chip_sw_all_escalation_resets.778491098 Jun 27 08:50:17 PM PDT 24 Jun 27 08:59:03 PM PDT 24 4774280428 ps
T404 /workspace/coverage/default/1.chip_sw_csrng_kat_test.495023793 Jun 27 08:27:15 PM PDT 24 Jun 27 08:31:57 PM PDT 24 2588296120 ps
T405 /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.536181515 Jun 27 08:46:49 PM PDT 24 Jun 27 08:53:58 PM PDT 24 4381793040 ps
T11 /workspace/coverage/default/0.chip_sw_sleep_pin_retention.510348222 Jun 27 08:21:45 PM PDT 24 Jun 27 08:28:13 PM PDT 24 3989958450 ps
T406 /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.155022755 Jun 27 08:25:39 PM PDT 24 Jun 27 08:29:21 PM PDT 24 2473079940 ps
T407 /workspace/coverage/default/1.chip_sw_edn_kat.489691875 Jun 27 08:26:58 PM PDT 24 Jun 27 08:37:45 PM PDT 24 3527421500 ps
T408 /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.3004421667 Jun 27 08:49:32 PM PDT 24 Jun 27 08:56:20 PM PDT 24 3280786176 ps
T409 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.2526639290 Jun 27 08:22:09 PM PDT 24 Jun 27 08:53:43 PM PDT 24 8311563355 ps
T50 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.4204924911 Jun 27 08:18:48 PM PDT 24 Jun 27 08:27:23 PM PDT 24 6063918526 ps
T711 /workspace/coverage/default/40.chip_sw_all_escalation_resets.1214996719 Jun 27 08:51:10 PM PDT 24 Jun 27 09:01:00 PM PDT 24 5101346654 ps
T254 /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3853184278 Jun 27 08:53:33 PM PDT 24 Jun 27 09:00:21 PM PDT 24 4205124942 ps
T235 /workspace/coverage/default/0.chip_sw_alert_handler_escalation.3429921933 Jun 27 08:17:37 PM PDT 24 Jun 27 08:25:45 PM PDT 24 4031806040 ps
T533 /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.4132635628 Jun 27 08:18:02 PM PDT 24 Jun 27 08:38:39 PM PDT 24 11596713962 ps
T372 /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3865553627 Jun 27 08:41:26 PM PDT 24 Jun 27 08:49:19 PM PDT 24 5133678574 ps
T894 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.550592520 Jun 27 08:18:01 PM PDT 24 Jun 27 09:20:47 PM PDT 24 15717178040 ps
T188 /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.3505848054 Jun 27 08:30:45 PM PDT 24 Jun 27 08:36:39 PM PDT 24 3265354449 ps
T720 /workspace/coverage/default/47.chip_sw_all_escalation_resets.3034697478 Jun 27 08:52:01 PM PDT 24 Jun 27 09:00:39 PM PDT 24 4983244760 ps
T36 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.550602226 Jun 27 08:17:31 PM PDT 24 Jun 27 09:11:43 PM PDT 24 20401485510 ps
T771 /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.698837061 Jun 27 08:50:09 PM PDT 24 Jun 27 08:57:29 PM PDT 24 3581661980 ps
T895 /workspace/coverage/default/1.chip_sw_ast_clk_outputs.1218926094 Jun 27 08:29:46 PM PDT 24 Jun 27 08:41:47 PM PDT 24 7375485376 ps
T712 /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.504830024 Jun 27 08:50:28 PM PDT 24 Jun 27 08:57:09 PM PDT 24 3856621562 ps
T772 /workspace/coverage/default/31.chip_sw_all_escalation_resets.3686318316 Jun 27 08:51:04 PM PDT 24 Jun 27 09:03:47 PM PDT 24 5329068824 ps
T896 /workspace/coverage/default/2.chip_sw_alert_handler_escalation.1311399203 Jun 27 08:37:14 PM PDT 24 Jun 27 08:46:05 PM PDT 24 5670720852 ps
T239 /workspace/coverage/default/2.chip_sw_flash_init.2227427073 Jun 27 08:33:44 PM PDT 24 Jun 27 09:08:43 PM PDT 24 25570605258 ps
T897 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.2018539869 Jun 27 08:36:20 PM PDT 24 Jun 27 08:52:00 PM PDT 24 8805387800 ps
T898 /workspace/coverage/default/0.chip_sw_example_concurrency.25569700 Jun 27 08:16:19 PM PDT 24 Jun 27 08:19:52 PM PDT 24 2527028816 ps
T899 /workspace/coverage/default/1.rom_e2e_asm_init_prod.122331595 Jun 27 08:39:17 PM PDT 24 Jun 27 09:46:35 PM PDT 24 15192896224 ps
T155 /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.3725668908 Jun 27 08:25:08 PM PDT 24 Jun 27 11:29:24 PM PDT 24 59905199934 ps
T713 /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.1026081010 Jun 27 08:52:13 PM PDT 24 Jun 27 09:00:02 PM PDT 24 3702062862 ps
T900 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.995835633 Jun 27 08:21:36 PM PDT 24 Jun 27 08:31:54 PM PDT 24 4824951800 ps
T213 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.389171221 Jun 27 08:27:46 PM PDT 24 Jun 27 09:05:02 PM PDT 24 22079372450 ps
T901 /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.222737420 Jun 27 08:39:13 PM PDT 24 Jun 27 09:05:09 PM PDT 24 12454212900 ps
T902 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.2386146843 Jun 27 08:22:25 PM PDT 24 Jun 27 08:40:44 PM PDT 24 5914970785 ps
T732 /workspace/coverage/default/87.chip_sw_all_escalation_resets.2893549903 Jun 27 08:54:16 PM PDT 24 Jun 27 09:06:00 PM PDT 24 5229251310 ps
T903 /workspace/coverage/default/1.chip_sw_edn_sw_mode.2261396888 Jun 27 08:26:59 PM PDT 24 Jun 27 09:06:49 PM PDT 24 9251122470 ps
T318 /workspace/coverage/default/0.chip_sw_entropy_src_csrng.1253604602 Jun 27 08:25:06 PM PDT 24 Jun 27 08:51:40 PM PDT 24 6710436752 ps
T904 /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.1368329356 Jun 27 08:44:20 PM PDT 24 Jun 27 08:49:02 PM PDT 24 3390995060 ps
T905 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.1157113608 Jun 27 08:35:41 PM PDT 24 Jun 27 08:46:37 PM PDT 24 8223037408 ps
T906 /workspace/coverage/default/1.chip_sw_aes_idle.1243270819 Jun 27 08:26:59 PM PDT 24 Jun 27 08:30:58 PM PDT 24 2922685360 ps
T907 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.605523056 Jun 27 08:20:26 PM PDT 24 Jun 27 09:05:02 PM PDT 24 22255337387 ps
T214 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.4202389972 Jun 27 08:17:35 PM PDT 24 Jun 27 08:22:56 PM PDT 24 3542227946 ps
T12 /workspace/coverage/default/1.chip_sw_sleep_pin_retention.3618240258 Jun 27 08:22:05 PM PDT 24 Jun 27 08:27:50 PM PDT 24 4007521352 ps
T908 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1177528816 Jun 27 08:30:19 PM PDT 24 Jun 27 09:39:16 PM PDT 24 15419211688 ps
T909 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.107321370 Jun 27 08:18:52 PM PDT 24 Jun 27 08:27:43 PM PDT 24 7177879520 ps
T910 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.4148834655 Jun 27 08:19:32 PM PDT 24 Jun 27 08:52:16 PM PDT 24 9273160212 ps
T911 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.1225502785 Jun 27 08:38:44 PM PDT 24 Jun 27 08:43:53 PM PDT 24 2989443374 ps
T701 /workspace/coverage/default/11.chip_sw_all_escalation_resets.4247724409 Jun 27 08:48:01 PM PDT 24 Jun 27 08:59:21 PM PDT 24 5569690864 ps
T912 /workspace/coverage/default/0.chip_sw_hmac_enc_idle.4188572297 Jun 27 08:21:41 PM PDT 24 Jun 27 08:26:18 PM PDT 24 2603280560 ps
T145 /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.406423559 Jun 27 08:35:24 PM PDT 24 Jun 27 08:44:45 PM PDT 24 7276982388 ps
T913 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3978587362 Jun 27 08:44:22 PM PDT 24 Jun 27 08:51:04 PM PDT 24 4632952332 ps
T37 /workspace/coverage/default/0.chip_sw_usbdev_config_host.1188323116 Jun 27 08:17:41 PM PDT 24 Jun 27 08:41:52 PM PDT 24 7854994340 ps
T674 /workspace/coverage/default/22.chip_sw_all_escalation_resets.2196034722 Jun 27 08:49:17 PM PDT 24 Jun 27 09:03:47 PM PDT 24 5835252770 ps
T714 /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.2456761474 Jun 27 08:23:26 PM PDT 24 Jun 27 08:34:27 PM PDT 24 4399254968 ps
T914 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.3557677226 Jun 27 08:25:17 PM PDT 24 Jun 27 08:35:34 PM PDT 24 6500306362 ps
T275 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.176916294 Jun 27 08:36:17 PM PDT 24 Jun 27 08:38:35 PM PDT 24 2986856416 ps
T915 /workspace/coverage/default/1.chip_sw_uart_tx_rx.1838749821 Jun 27 08:24:57 PM PDT 24 Jun 27 08:35:39 PM PDT 24 4255566016 ps
T916 /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.2407739744 Jun 27 08:46:54 PM PDT 24 Jun 27 08:56:37 PM PDT 24 5403579244 ps
T696 /workspace/coverage/default/62.chip_sw_all_escalation_resets.3231391017 Jun 27 08:52:35 PM PDT 24 Jun 27 09:02:29 PM PDT 24 5041896024 ps
T917 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.2160693417 Jun 27 08:35:18 PM PDT 24 Jun 27 08:50:41 PM PDT 24 9102931960 ps
T918 /workspace/coverage/default/78.chip_sw_all_escalation_resets.3468465290 Jun 27 08:55:59 PM PDT 24 Jun 27 09:05:54 PM PDT 24 4563249576 ps
T130 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.1312627821 Jun 27 08:20:33 PM PDT 24 Jun 27 08:28:27 PM PDT 24 5678379912 ps
T919 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2842976530 Jun 27 08:20:03 PM PDT 24 Jun 27 08:29:14 PM PDT 24 5135868406 ps
T769 /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.1647516813 Jun 27 08:52:10 PM PDT 24 Jun 27 08:58:52 PM PDT 24 4362016756 ps
T760 /workspace/coverage/default/35.chip_sw_all_escalation_resets.734817192 Jun 27 08:53:37 PM PDT 24 Jun 27 09:02:38 PM PDT 24 5366871590 ps
T243 /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.4261301407 Jun 27 08:36:01 PM PDT 24 Jun 27 10:07:37 PM PDT 24 47222508680 ps
T259 /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.2330728925 Jun 27 08:32:58 PM PDT 24 Jun 27 08:37:18 PM PDT 24 2849416800 ps
T149 /workspace/coverage/default/0.chip_sw_usbdev_setuprx.4218783606 Jun 27 08:18:10 PM PDT 24 Jun 27 08:28:23 PM PDT 24 3393342400 ps
T194 /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.3762864770 Jun 27 08:38:51 PM PDT 24 Jun 27 08:55:52 PM PDT 24 9905162229 ps
T232 /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.4101305302 Jun 27 08:25:05 PM PDT 24 Jun 27 09:06:30 PM PDT 24 10148611290 ps
T920 /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.2566630351 Jun 27 08:48:42 PM PDT 24 Jun 27 08:58:50 PM PDT 24 5065890088 ps
T921 /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.449244822 Jun 27 08:17:35 PM PDT 24 Jun 27 08:47:24 PM PDT 24 8640704690 ps
T922 /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.509496671 Jun 27 08:24:56 PM PDT 24 Jun 27 08:41:58 PM PDT 24 5352301772 ps
T759 /workspace/coverage/default/50.chip_sw_all_escalation_resets.4073955047 Jun 27 08:51:12 PM PDT 24 Jun 27 09:00:46 PM PDT 24 5895587480 ps
T290 /workspace/coverage/default/4.chip_sw_data_integrity_escalation.3539320754 Jun 27 08:45:53 PM PDT 24 Jun 27 09:00:40 PM PDT 24 5617663284 ps
T923 /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.2549420399 Jun 27 08:22:59 PM PDT 24 Jun 27 08:27:32 PM PDT 24 2916954520 ps
T924 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.1140975838 Jun 27 08:30:50 PM PDT 24 Jun 27 09:06:22 PM PDT 24 8632707000 ps
T324 /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.381818246 Jun 27 08:47:05 PM PDT 24 Jun 27 09:27:21 PM PDT 24 13071847152 ps
T925 /workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.3623381702 Jun 27 08:37:26 PM PDT 24 Jun 27 09:07:40 PM PDT 24 7759865712 ps
T926 /workspace/coverage/default/2.chip_sw_otbn_smoketest.3588543267 Jun 27 08:43:11 PM PDT 24 Jun 27 09:19:57 PM PDT 24 11147110232 ps
T531 /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.2234015244 Jun 27 08:36:11 PM PDT 24 Jun 27 08:47:00 PM PDT 24 5070325900 ps
T927 /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.728844009 Jun 27 08:24:11 PM PDT 24 Jun 27 08:49:20 PM PDT 24 8541814634 ps
T928 /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2765228408 Jun 27 08:43:30 PM PDT 24 Jun 27 08:50:29 PM PDT 24 7138767200 ps
T242 /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.761537144 Jun 27 08:35:48 PM PDT 24 Jun 27 09:59:48 PM PDT 24 46300201132 ps
T929 /workspace/coverage/default/1.chip_sw_aes_smoketest.1741014231 Jun 27 08:32:58 PM PDT 24 Jun 27 08:37:11 PM PDT 24 2261456280 ps
T930 /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.1916615894 Jun 27 08:23:07 PM PDT 24 Jun 27 08:35:24 PM PDT 24 6724854720 ps
T719 /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.516504605 Jun 27 08:54:19 PM PDT 24 Jun 27 08:59:00 PM PDT 24 3484889222 ps
T931 /workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.4078386864 Jun 27 08:19:27 PM PDT 24 Jun 27 08:45:27 PM PDT 24 7322318400 ps
T932 /workspace/coverage/default/2.chip_sw_csrng_kat_test.72883002 Jun 27 08:40:46 PM PDT 24 Jun 27 08:46:36 PM PDT 24 2643270890 ps
T933 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3876628215 Jun 27 08:22:51 PM PDT 24 Jun 27 08:54:30 PM PDT 24 13144515196 ps
T699 /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.1354984521 Jun 27 08:50:45 PM PDT 24 Jun 27 08:56:58 PM PDT 24 3873059750 ps
T81 /workspace/coverage/default/1.chip_jtag_csr_rw.2955916762 Jun 27 08:22:45 PM PDT 24 Jun 27 08:51:33 PM PDT 24 14589082972 ps
T241 /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.2931194541 Jun 27 08:37:21 PM PDT 24 Jun 27 08:43:32 PM PDT 24 4950895121 ps
T269 /workspace/coverage/default/26.chip_sw_all_escalation_resets.1082782842 Jun 27 08:48:42 PM PDT 24 Jun 27 08:58:35 PM PDT 24 6378302740 ps
T934 /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.2282212884 Jun 27 08:47:23 PM PDT 24 Jun 27 09:00:17 PM PDT 24 11635856377 ps
T112 /workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.645788006 Jun 27 08:31:01 PM PDT 24 Jun 27 09:12:38 PM PDT 24 19313261646 ps
T336 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.885830664 Jun 27 08:22:48 PM PDT 24 Jun 27 08:32:18 PM PDT 24 3362342312 ps
T335 /workspace/coverage/default/0.chip_sival_flash_info_access.4227626809 Jun 27 08:18:11 PM PDT 24 Jun 27 08:21:59 PM PDT 24 2994072360 ps
T260 /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.3579683740 Jun 27 08:43:26 PM PDT 24 Jun 27 08:47:35 PM PDT 24 2973681800 ps
T935 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.3403480623 Jun 27 08:44:40 PM PDT 24 Jun 27 08:55:50 PM PDT 24 3957667732 ps
T88 /workspace/coverage/default/60.chip_sw_all_escalation_resets.3987175703 Jun 27 08:52:38 PM PDT 24 Jun 27 09:01:42 PM PDT 24 4766088350 ps
T93 /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.3441068082 Jun 27 08:54:29 PM PDT 24 Jun 27 09:01:55 PM PDT 24 3602274456 ps
T94 /workspace/coverage/default/0.chip_sw_example_flash.2183300276 Jun 27 08:16:56 PM PDT 24 Jun 27 08:20:53 PM PDT 24 2372477444 ps
T95 /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.2505232923 Jun 27 08:24:38 PM PDT 24 Jun 27 08:32:02 PM PDT 24 4179486006 ps
T96 /workspace/coverage/default/2.chip_sw_kmac_smoketest.3269156113 Jun 27 08:42:47 PM PDT 24 Jun 27 08:50:31 PM PDT 24 3377819392 ps
T97 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.474490929 Jun 27 08:47:08 PM PDT 24 Jun 27 09:42:48 PM PDT 24 14723977264 ps
T27 /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.4132749479 Jun 27 08:36:11 PM PDT 24 Jun 27 08:45:00 PM PDT 24 4381788149 ps
T98 /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.1091183988 Jun 27 08:28:45 PM PDT 24 Jun 27 08:40:40 PM PDT 24 7564215477 ps
T99 /workspace/coverage/default/1.chip_sw_csrng_smoketest.2730513080 Jun 27 08:33:08 PM PDT 24 Jun 27 08:38:43 PM PDT 24 2478357102 ps
T100 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2454032101 Jun 27 08:41:59 PM PDT 24 Jun 27 08:55:24 PM PDT 24 4585418244 ps
T936 /workspace/coverage/default/0.chip_sw_example_manufacturer.3692079854 Jun 27 08:17:39 PM PDT 24 Jun 27 08:22:09 PM PDT 24 2624505992 ps
T937 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.808907092 Jun 27 08:22:00 PM PDT 24 Jun 27 08:34:42 PM PDT 24 7594813200 ps
T247 /workspace/coverage/default/0.chip_sw_flash_init.2372844177 Jun 27 08:17:02 PM PDT 24 Jun 27 08:53:21 PM PDT 24 18403388755 ps
T141 /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1779861599 Jun 27 08:30:41 PM PDT 24 Jun 27 08:37:37 PM PDT 24 5336142184 ps
T938 /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.4139518519 Jun 27 08:30:49 PM PDT 24 Jun 27 08:33:27 PM PDT 24 3319035024 ps
T692 /workspace/coverage/default/1.chip_sw_power_sleep_load.4262338224 Jun 27 08:32:46 PM PDT 24 Jun 27 08:39:26 PM PDT 24 4668254856 ps
T939 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.2799664209 Jun 27 08:19:51 PM PDT 24 Jun 27 08:27:18 PM PDT 24 3452413940 ps
T940 /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.3975013058 Jun 27 08:17:06 PM PDT 24 Jun 27 08:35:26 PM PDT 24 5951732887 ps
T739 /workspace/coverage/default/89.chip_sw_all_escalation_resets.3601202924 Jun 27 08:54:45 PM PDT 24 Jun 27 09:04:43 PM PDT 24 4455953400 ps
T941 /workspace/coverage/default/2.chip_sw_edn_sw_mode.822963666 Jun 27 08:37:11 PM PDT 24 Jun 27 09:11:22 PM PDT 24 9781568390 ps
T942 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3613135339 Jun 27 08:43:02 PM PDT 24 Jun 27 08:49:32 PM PDT 24 3983365265 ps
T51 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2627022123 Jun 27 08:36:49 PM PDT 24 Jun 27 08:46:30 PM PDT 24 6857230160 ps
T740 /workspace/coverage/default/37.chip_sw_all_escalation_resets.3417193910 Jun 27 08:50:29 PM PDT 24 Jun 27 09:00:59 PM PDT 24 5975779940 ps
T943 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3031937321 Jun 27 08:17:41 PM PDT 24 Jun 27 08:26:24 PM PDT 24 6926050654 ps
T944 /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.2270868073 Jun 27 08:50:38 PM PDT 24 Jun 27 09:00:03 PM PDT 24 4480998152 ps
T945 /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.274170071 Jun 27 08:36:15 PM PDT 24 Jun 27 08:44:11 PM PDT 24 5388212490 ps
T946 /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.1937877023 Jun 27 08:44:24 PM PDT 24 Jun 27 08:49:05 PM PDT 24 2910791834 ps
T947 /workspace/coverage/default/0.chip_sw_alert_handler_entropy.18818503 Jun 27 08:18:22 PM PDT 24 Jun 27 08:25:47 PM PDT 24 3165942880 ps
T948 /workspace/coverage/default/0.chip_sw_csrng_kat_test.4140014292 Jun 27 08:19:12 PM PDT 24 Jun 27 08:22:00 PM PDT 24 2486521512 ps
T750 /workspace/coverage/default/44.chip_sw_all_escalation_resets.2919570907 Jun 27 08:50:26 PM PDT 24 Jun 27 08:59:39 PM PDT 24 4622276520 ps
T949 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.109866555 Jun 27 08:40:34 PM PDT 24 Jun 27 08:52:25 PM PDT 24 4448610808 ps
T206 /workspace/coverage/default/1.chip_jtag_mem_access.1180968338 Jun 27 08:22:37 PM PDT 24 Jun 27 08:46:51 PM PDT 24 13408222560 ps
T950 /workspace/coverage/default/16.chip_sw_all_escalation_resets.3124063982 Jun 27 08:48:46 PM PDT 24 Jun 27 08:59:02 PM PDT 24 6589093648 ps
T951 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.1382996646 Jun 27 08:56:44 PM PDT 24 Jun 27 10:06:38 PM PDT 24 15866154456 ps
T773 /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.2141861560 Jun 27 08:51:24 PM PDT 24 Jun 27 08:57:32 PM PDT 24 3342473900 ps
T952 /workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.3292975807 Jun 27 08:26:00 PM PDT 24 Jun 27 08:51:10 PM PDT 24 7274483756 ps
T953 /workspace/coverage/default/2.rom_e2e_asm_init_prod.3283619806 Jun 27 08:47:25 PM PDT 24 Jun 27 09:50:18 PM PDT 24 15668119864 ps
T954 /workspace/coverage/default/1.chip_sw_flash_ctrl_access.897147811 Jun 27 08:24:06 PM PDT 24 Jun 27 08:45:32 PM PDT 24 6269441490 ps
T707 /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.828537669 Jun 27 08:48:07 PM PDT 24 Jun 27 08:53:54 PM PDT 24 3026013208 ps
T955 /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.523667746 Jun 27 08:28:25 PM PDT 24 Jun 27 08:36:48 PM PDT 24 4249827112 ps
T956 /workspace/coverage/default/2.chip_sw_flash_ctrl_access.4213864735 Jun 27 08:36:12 PM PDT 24 Jun 27 08:54:35 PM PDT 24 5743033220 ps
T255 /workspace/coverage/default/86.chip_sw_all_escalation_resets.3775742614 Jun 27 08:54:03 PM PDT 24 Jun 27 09:03:34 PM PDT 24 5721848110 ps
T355 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.789138320 Jun 27 08:38:26 PM PDT 24 Jun 27 08:43:28 PM PDT 24 3133084031 ps
T957 /workspace/coverage/default/3.chip_tap_straps_rma.1306862179 Jun 27 08:43:51 PM PDT 24 Jun 27 08:58:31 PM PDT 24 9262534008 ps
T532 /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.1756071248 Jun 27 08:20:53 PM PDT 24 Jun 27 08:35:19 PM PDT 24 5064907380 ps
T958 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.852321203 Jun 27 08:30:06 PM PDT 24 Jun 27 08:58:56 PM PDT 24 11842695229 ps
T959 /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.1293715749 Jun 27 08:28:18 PM PDT 24 Jun 27 09:11:13 PM PDT 24 12830623880 ps
T276 /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.2446496335 Jun 27 08:38:45 PM PDT 24 Jun 27 08:50:14 PM PDT 24 8129252785 ps
T653 /workspace/coverage/default/2.chip_sw_edn_boot_mode.1328951427 Jun 27 08:41:58 PM PDT 24 Jun 27 08:49:11 PM PDT 24 3586210808 ps
T960 /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.3120109968 Jun 27 08:28:08 PM PDT 24 Jun 27 08:46:33 PM PDT 24 6622571488 ps
T961 /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.4043078977 Jun 27 08:45:17 PM PDT 24 Jun 27 08:50:46 PM PDT 24 5910989528 ps
T209 /workspace/coverage/default/1.chip_sw_inject_scramble_seed.3172630248 Jun 27 08:22:52 PM PDT 24 Jun 27 11:46:45 PM PDT 24 63537118849 ps
T962 /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.4211617455 Jun 27 08:34:05 PM PDT 24 Jun 27 08:43:01 PM PDT 24 5880596040 ps
T764 /workspace/coverage/default/17.chip_sw_all_escalation_resets.1464791698 Jun 27 08:48:04 PM PDT 24 Jun 27 09:00:36 PM PDT 24 6378566536 ps
T332 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4219674226 Jun 27 08:32:57 PM PDT 24 Jun 27 08:44:40 PM PDT 24 4536314419 ps
T963 /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.2092954527 Jun 27 08:20:17 PM PDT 24 Jun 27 08:40:29 PM PDT 24 10370861560 ps
T757 /workspace/coverage/default/5.chip_sw_all_escalation_resets.40895969 Jun 27 08:45:38 PM PDT 24 Jun 27 09:00:32 PM PDT 24 5445023452 ps
T964 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.1380791321 Jun 27 08:35:45 PM PDT 24 Jun 27 08:53:49 PM PDT 24 6895002288 ps
T89 /workspace/coverage/default/80.chip_sw_all_escalation_resets.1658451895 Jun 27 08:54:57 PM PDT 24 Jun 27 09:04:29 PM PDT 24 5548755000 ps
T965 /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.1423211417 Jun 27 08:42:44 PM PDT 24 Jun 27 08:49:06 PM PDT 24 3028811716 ps
T966 /workspace/coverage/default/3.chip_tap_straps_testunlock0.3808881145 Jun 27 08:43:33 PM PDT 24 Jun 27 08:59:09 PM PDT 24 9422798966 ps
T90 /workspace/coverage/default/70.chip_sw_all_escalation_resets.2291017 Jun 27 08:53:20 PM PDT 24 Jun 27 09:01:22 PM PDT 24 4298297830 ps
T743 /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.2855394589 Jun 27 08:55:31 PM PDT 24 Jun 27 09:02:29 PM PDT 24 3496338040 ps
T315 /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.3778930714 Jun 27 08:18:19 PM PDT 24 Jun 27 08:52:19 PM PDT 24 12060177356 ps
T967 /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.1637969081 Jun 27 08:47:56 PM PDT 24 Jun 27 08:55:45 PM PDT 24 3257465160 ps
T778 /workspace/coverage/default/0.chip_sw_all_escalation_resets.3487081434 Jun 27 08:17:14 PM PDT 24 Jun 27 08:26:13 PM PDT 24 4891358544 ps
T968 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.2589373111 Jun 27 08:26:24 PM PDT 24 Jun 27 09:32:55 PM PDT 24 15048168100 ps
T327 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.2222759739 Jun 27 08:23:11 PM PDT 24 Jun 27 08:40:45 PM PDT 24 4942181928 ps
T969 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.3824680826 Jun 27 08:37:03 PM PDT 24 Jun 27 09:21:55 PM PDT 24 12010783422 ps
T774 /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.1224630952 Jun 27 08:58:45 PM PDT 24 Jun 27 09:05:14 PM PDT 24 4029213990 ps
T970 /workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.1618518124 Jun 27 08:45:44 PM PDT 24 Jun 27 09:50:53 PM PDT 24 20677152490 ps
T432 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.1719617572 Jun 27 08:37:47 PM PDT 24 Jun 27 08:54:35 PM PDT 24 5715586544 ps
T278 /workspace/coverage/default/2.chip_sw_data_integrity_escalation.3361277303 Jun 27 08:32:53 PM PDT 24 Jun 27 08:46:06 PM PDT 24 6385491498 ps
T761 /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.850028575 Jun 27 08:56:43 PM PDT 24 Jun 27 09:04:30 PM PDT 24 3958722168 ps
T971 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.1154724062 Jun 27 08:17:06 PM PDT 24 Jun 27 08:27:03 PM PDT 24 6365375100 ps
T972 /workspace/coverage/default/1.chip_sw_plic_sw_irq.4215733585 Jun 27 08:29:00 PM PDT 24 Jun 27 08:33:37 PM PDT 24 2412958168 ps
T973 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.2366772434 Jun 27 08:35:58 PM PDT 24 Jun 27 08:48:08 PM PDT 24 4878574340 ps
T974 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.2033115554 Jun 27 08:36:01 PM PDT 24 Jun 27 08:50:04 PM PDT 24 8181029610 ps
T300 /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.4052959863 Jun 27 08:20:45 PM PDT 24 Jun 27 08:26:46 PM PDT 24 2612510288 ps
T975 /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1900422533 Jun 27 08:48:57 PM PDT 24 Jun 27 08:56:52 PM PDT 24 6634277497 ps
T976 /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.3420197914 Jun 27 08:42:01 PM PDT 24 Jun 27 08:48:17 PM PDT 24 5027496592 ps
T735 /workspace/coverage/default/75.chip_sw_all_escalation_resets.2911702361 Jun 27 08:56:52 PM PDT 24 Jun 27 09:08:35 PM PDT 24 5176911448 ps
T709 /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.3899827451 Jun 27 08:50:08 PM PDT 24 Jun 27 08:57:41 PM PDT 24 3493074096 ps
T382 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.334473982 Jun 27 08:26:17 PM PDT 24 Jun 27 10:05:01 PM PDT 24 24434770188 ps
T101 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3597094376 Jun 27 08:40:26 PM PDT 24 Jun 27 09:09:50 PM PDT 24 27224979498 ps
T977 /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.808391893 Jun 27 08:48:35 PM PDT 24 Jun 27 09:30:57 PM PDT 24 12633447612 ps
T978 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.1954366211 Jun 27 08:23:44 PM PDT 24 Jun 27 08:40:08 PM PDT 24 10794925940 ps
T344 /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.3486089882 Jun 27 08:18:45 PM PDT 24 Jun 27 08:22:16 PM PDT 24 2476570343 ps
T86 /workspace/coverage/default/2.chip_sw_gpio_smoketest.2922924493 Jun 27 08:42:37 PM PDT 24 Jun 27 08:45:53 PM PDT 24 2377085995 ps
T979 /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.547630298 Jun 27 08:32:52 PM PDT 24 Jun 27 08:37:13 PM PDT 24 2646077530 ps
T980 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.2531757809 Jun 27 08:42:52 PM PDT 24 Jun 27 08:47:37 PM PDT 24 3134770360 ps
T981 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.806983442 Jun 27 08:41:52 PM PDT 24 Jun 27 08:44:51 PM PDT 24 2964254681 ps
T704 /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1813521770 Jun 27 08:55:19 PM PDT 24 Jun 27 09:02:21 PM PDT 24 3360770888 ps
T982 /workspace/coverage/default/2.rom_e2e_smoke.1982192512 Jun 27 08:57:26 PM PDT 24 Jun 27 10:11:02 PM PDT 24 14748477980 ps
T983 /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.3124832363 Jun 27 08:26:09 PM PDT 24 Jun 27 08:30:50 PM PDT 24 3293982074 ps
T984 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.2594433966 Jun 27 08:55:37 PM PDT 24 Jun 27 09:06:32 PM PDT 24 4576867208 ps
T341 /workspace/coverage/default/93.chip_sw_all_escalation_resets.3645983815 Jun 27 08:55:38 PM PDT 24 Jun 27 09:03:54 PM PDT 24 4584623640 ps
T270 /workspace/coverage/default/57.chip_sw_all_escalation_resets.1671933524 Jun 27 08:52:21 PM PDT 24 Jun 27 08:59:48 PM PDT 24 4394100856 ps
T985 /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3967313306 Jun 27 08:46:05 PM PDT 24 Jun 27 09:25:40 PM PDT 24 13035234750 ps
T986 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1668106397 Jun 27 08:25:03 PM PDT 24 Jun 27 08:32:10 PM PDT 24 6639553384 ps
T987 /workspace/coverage/default/0.chip_tap_straps_dev.752966463 Jun 27 08:20:29 PM PDT 24 Jun 27 08:25:59 PM PDT 24 3963024784 ps
T988 /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.229921833 Jun 27 08:46:43 PM PDT 24 Jun 27 08:57:55 PM PDT 24 11465503026 ps
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