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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.14 95.59 93.98 95.45 94.77 97.53 99.53


Total test records in report: 2877
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T779 /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.29881621 Jun 27 08:49:26 PM PDT 24 Jun 27 08:55:48 PM PDT 24 3656715694 ps
T359 /workspace/coverage/default/33.chip_sw_all_escalation_resets.1885940504 Jun 27 08:51:46 PM PDT 24 Jun 27 09:04:00 PM PDT 24 4579592948 ps
T989 /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.3042894310 Jun 27 08:29:09 PM PDT 24 Jun 27 08:37:38 PM PDT 24 4126204942 ps
T990 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.170100095 Jun 27 08:34:21 PM PDT 24 Jun 27 08:45:08 PM PDT 24 4878602456 ps
T28 /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.2976341627 Jun 27 08:16:23 PM PDT 24 Jun 27 08:24:50 PM PDT 24 4750779424 ps
T991 /workspace/coverage/default/1.chip_sw_example_flash.407572895 Jun 27 08:24:10 PM PDT 24 Jun 27 08:28:09 PM PDT 24 3073052846 ps
T233 /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.1012662348 Jun 27 08:28:02 PM PDT 24 Jun 27 08:55:08 PM PDT 24 8508678628 ps
T754 /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3394860474 Jun 27 08:51:43 PM PDT 24 Jun 27 08:57:17 PM PDT 24 3072740400 ps
T992 /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.1381682808 Jun 27 08:25:42 PM PDT 24 Jun 27 09:19:42 PM PDT 24 10817560913 ps
T993 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.3142962479 Jun 27 08:19:36 PM PDT 24 Jun 27 08:28:59 PM PDT 24 6476152550 ps
T994 /workspace/coverage/default/4.chip_tap_straps_dev.3724682225 Jun 27 08:44:36 PM PDT 24 Jun 27 08:47:41 PM PDT 24 2448071328 ps
T995 /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.1156191625 Jun 27 08:48:59 PM PDT 24 Jun 27 08:54:42 PM PDT 24 3968171740 ps
T244 /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.3951869901 Jun 27 08:35:18 PM PDT 24 Jun 27 10:09:02 PM PDT 24 48029316132 ps
T781 /workspace/coverage/default/53.chip_sw_all_escalation_resets.2494717028 Jun 27 08:52:58 PM PDT 24 Jun 27 09:03:25 PM PDT 24 5296349100 ps
T996 /workspace/coverage/default/1.chip_tap_straps_prod.2134729276 Jun 27 08:31:23 PM PDT 24 Jun 27 08:34:24 PM PDT 24 2969994370 ps
T161 /workspace/coverage/default/1.chip_plic_all_irqs_10.3636473276 Jun 27 08:28:27 PM PDT 24 Jun 27 08:35:23 PM PDT 24 3940051836 ps
T770 /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.1279676121 Jun 27 08:52:06 PM PDT 24 Jun 27 08:57:31 PM PDT 24 4048876040 ps
T997 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.3311787129 Jun 27 08:55:34 PM PDT 24 Jun 27 09:06:27 PM PDT 24 4334403528 ps
T998 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.3004255160 Jun 27 08:44:11 PM PDT 24 Jun 27 09:13:06 PM PDT 24 9063660485 ps
T999 /workspace/coverage/default/2.chip_sw_hmac_oneshot.2476935782 Jun 27 08:38:33 PM PDT 24 Jun 27 08:43:42 PM PDT 24 2958395536 ps
T91 /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.464022361 Jun 27 08:52:14 PM PDT 24 Jun 27 08:57:28 PM PDT 24 4225759400 ps
T190 /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.3121450821 Jun 27 08:21:19 PM PDT 24 Jun 27 09:46:08 PM PDT 24 44677520810 ps
T744 /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.1975314587 Jun 27 08:52:58 PM PDT 24 Jun 27 08:59:49 PM PDT 24 3287678406 ps
T1000 /workspace/coverage/default/97.chip_sw_all_escalation_resets.2448826054 Jun 27 08:54:45 PM PDT 24 Jun 27 09:06:43 PM PDT 24 5577565320 ps
T1001 /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.428595785 Jun 27 08:22:26 PM PDT 24 Jun 27 08:28:00 PM PDT 24 2656655814 ps
T1002 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.2469867368 Jun 27 08:35:13 PM PDT 24 Jun 27 08:57:08 PM PDT 24 7482979604 ps
T391 /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.2118515464 Jun 27 08:32:47 PM PDT 24 Jun 27 08:38:24 PM PDT 24 5076642286 ps
T1003 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.2123064495 Jun 27 08:19:31 PM PDT 24 Jun 27 08:43:10 PM PDT 24 7179834528 ps
T433 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.3456666622 Jun 27 08:28:22 PM PDT 24 Jun 27 08:45:08 PM PDT 24 6335773656 ps
T1004 /workspace/coverage/default/1.chip_sw_kmac_smoketest.2598696814 Jun 27 08:32:23 PM PDT 24 Jun 27 08:37:36 PM PDT 24 2999405200 ps
T1005 /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.2878103270 Jun 27 08:39:47 PM PDT 24 Jun 27 08:48:24 PM PDT 24 4449920496 ps
T1006 /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.1909273894 Jun 27 08:17:39 PM PDT 24 Jun 27 08:27:30 PM PDT 24 5312829596 ps
T1007 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.3090487518 Jun 27 08:36:16 PM PDT 24 Jun 27 09:32:40 PM PDT 24 17486877772 ps
T748 /workspace/coverage/default/85.chip_sw_all_escalation_resets.1839815050 Jun 27 08:57:19 PM PDT 24 Jun 27 09:08:30 PM PDT 24 5869162922 ps
T1008 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.2040949398 Jun 27 08:24:43 PM PDT 24 Jun 27 08:37:00 PM PDT 24 5567084456 ps
T291 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.31097341 Jun 27 08:42:15 PM PDT 24 Jun 27 08:54:06 PM PDT 24 5768777406 ps
T737 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.516529815 Jun 27 08:26:58 PM PDT 24 Jun 27 08:33:31 PM PDT 24 3827565230 ps
T1009 /workspace/coverage/default/1.rom_e2e_smoke.2531130923 Jun 27 08:36:13 PM PDT 24 Jun 27 09:42:00 PM PDT 24 14320374504 ps
T1010 /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.2121702117 Jun 27 08:46:24 PM PDT 24 Jun 27 09:12:54 PM PDT 24 8453340260 ps
T1011 /workspace/coverage/default/0.chip_sw_data_integrity_escalation.3073986515 Jun 27 08:16:05 PM PDT 24 Jun 27 08:29:54 PM PDT 24 6069958190 ps
T1012 /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.4039869105 Jun 27 08:47:58 PM PDT 24 Jun 27 09:22:04 PM PDT 24 12896033250 ps
T1013 /workspace/coverage/default/1.chip_sw_kmac_idle.146418754 Jun 27 08:28:36 PM PDT 24 Jun 27 08:33:49 PM PDT 24 2860096488 ps
T1014 /workspace/coverage/default/0.rom_e2e_smoke.98744429 Jun 27 08:25:15 PM PDT 24 Jun 27 09:38:31 PM PDT 24 14957084454 ps
T1015 /workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.3818900396 Jun 27 08:53:51 PM PDT 24 Jun 27 10:14:28 PM PDT 24 17543337080 ps
T1016 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.11166334 Jun 27 08:36:43 PM PDT 24 Jun 27 09:17:42 PM PDT 24 23196241188 ps
T1017 /workspace/coverage/default/1.chip_sw_uart_smoketest.2757265349 Jun 27 08:32:41 PM PDT 24 Jun 27 08:37:47 PM PDT 24 2682233116 ps
T1018 /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.2622372594 Jun 27 08:31:09 PM PDT 24 Jun 27 08:41:45 PM PDT 24 3975385710 ps
T203 /workspace/coverage/default/1.chip_sw_spi_device_pass_through.1782883636 Jun 27 08:22:20 PM PDT 24 Jun 27 08:35:55 PM PDT 24 7435488937 ps
T1019 /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.3687784517 Jun 27 08:19:57 PM PDT 24 Jun 27 08:59:27 PM PDT 24 27727093384 ps
T215 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.3159916038 Jun 27 08:35:43 PM PDT 24 Jun 27 08:45:08 PM PDT 24 4973486869 ps
T1020 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.3360825765 Jun 27 08:17:50 PM PDT 24 Jun 27 08:35:44 PM PDT 24 8179843464 ps
T174 /workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.2441758019 Jun 27 08:40:50 PM PDT 24 Jun 27 08:49:56 PM PDT 24 4556375730 ps
T1021 /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.3723318394 Jun 27 08:51:05 PM PDT 24 Jun 27 08:59:29 PM PDT 24 3523332024 ps
T207 /workspace/coverage/default/0.chip_jtag_mem_access.3258473814 Jun 27 08:11:37 PM PDT 24 Jun 27 08:33:57 PM PDT 24 13514381035 ps
T1022 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.2895215952 Jun 27 08:24:32 PM PDT 24 Jun 27 09:24:15 PM PDT 24 18752744685 ps
T1023 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.904703675 Jun 27 08:28:59 PM PDT 24 Jun 27 08:40:38 PM PDT 24 5473040314 ps
T700 /workspace/coverage/default/73.chip_sw_all_escalation_resets.291902147 Jun 27 08:53:27 PM PDT 24 Jun 27 09:02:00 PM PDT 24 5017657696 ps
T61 /workspace/coverage/default/2.chip_sw_alert_test.1305917161 Jun 27 08:39:23 PM PDT 24 Jun 27 08:45:27 PM PDT 24 3384929680 ps
T1024 /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.3495767946 Jun 27 08:23:28 PM PDT 24 Jun 27 08:42:10 PM PDT 24 6150125894 ps
T1025 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.2028333025 Jun 27 08:31:00 PM PDT 24 Jun 27 08:39:14 PM PDT 24 5637630100 ps
T354 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.1129196484 Jun 27 08:36:21 PM PDT 24 Jun 27 08:48:11 PM PDT 24 3701655900 ps
T46 /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.1250375753 Jun 27 08:34:27 PM PDT 24 Jun 27 08:40:22 PM PDT 24 3192588982 ps
T698 /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.3883149023 Jun 27 08:54:03 PM PDT 24 Jun 27 09:00:24 PM PDT 24 3482319656 ps
T1026 /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.1202758424 Jun 27 08:45:27 PM PDT 24 Jun 27 08:57:53 PM PDT 24 5687515633 ps
T1027 /workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.2812733988 Jun 27 08:36:52 PM PDT 24 Jun 27 08:41:59 PM PDT 24 2846829529 ps
T311 /workspace/coverage/default/1.chip_plic_all_irqs_0.3159875098 Jun 27 08:29:32 PM PDT 24 Jun 27 08:53:33 PM PDT 24 5889127350 ps
T54 /workspace/coverage/default/0.chip_sw_spi_device_tpm.707472056 Jun 27 08:16:42 PM PDT 24 Jun 27 08:22:25 PM PDT 24 3054723748 ps
T1028 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.880420072 Jun 27 08:20:48 PM PDT 24 Jun 27 09:24:48 PM PDT 24 24657874967 ps
T1029 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.1829241751 Jun 27 08:29:50 PM PDT 24 Jun 27 08:37:59 PM PDT 24 3657043912 ps
T1030 /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.4112911339 Jun 27 08:29:59 PM PDT 24 Jun 27 08:38:19 PM PDT 24 3509187408 ps
T1031 /workspace/coverage/default/0.chip_sw_hmac_oneshot.367968788 Jun 27 08:20:16 PM PDT 24 Jun 27 08:25:12 PM PDT 24 2752964220 ps
T1032 /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.3042820696 Jun 27 08:51:28 PM PDT 24 Jun 27 08:59:52 PM PDT 24 3735862928 ps
T1033 /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.183642715 Jun 27 08:43:18 PM PDT 24 Jun 27 08:49:10 PM PDT 24 5016301770 ps
T1034 /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.4004434999 Jun 27 08:16:27 PM PDT 24 Jun 27 08:35:38 PM PDT 24 9694418678 ps
T1035 /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.273138166 Jun 27 08:17:15 PM PDT 24 Jun 27 08:24:01 PM PDT 24 3441276584 ps
T1036 /workspace/coverage/default/72.chip_sw_all_escalation_resets.3042883621 Jun 27 08:56:03 PM PDT 24 Jun 27 09:06:40 PM PDT 24 4377341512 ps
T1037 /workspace/coverage/default/2.chip_sw_otbn_randomness.1153626021 Jun 27 08:36:39 PM PDT 24 Jun 27 08:53:23 PM PDT 24 5769173012 ps
T1038 /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.3990792723 Jun 27 08:18:27 PM PDT 24 Jun 27 09:58:21 PM PDT 24 49405304216 ps
T13 /workspace/coverage/default/2.chip_sw_sleep_pin_retention.837304780 Jun 27 08:34:02 PM PDT 24 Jun 27 08:40:52 PM PDT 24 4116985716 ps
T730 /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.2593901029 Jun 27 08:53:01 PM PDT 24 Jun 27 08:58:38 PM PDT 24 3570736040 ps
T1039 /workspace/coverage/default/45.chip_sw_all_escalation_resets.3439230791 Jun 27 08:52:24 PM PDT 24 Jun 27 09:00:15 PM PDT 24 5108427504 ps
T1040 /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.1081876476 Jun 27 08:19:00 PM PDT 24 Jun 27 08:27:43 PM PDT 24 4310168520 ps
T1041 /workspace/coverage/default/1.rom_keymgr_functest.2741249128 Jun 27 08:33:04 PM PDT 24 Jun 27 08:44:12 PM PDT 24 5474750460 ps
T765 /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.1578950727 Jun 27 08:54:33 PM PDT 24 Jun 27 09:01:49 PM PDT 24 3797981840 ps
T1042 /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.710523165 Jun 27 08:48:23 PM PDT 24 Jun 27 09:32:00 PM PDT 24 13182867076 ps
T156 /workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.3012981194 Jun 27 08:34:10 PM PDT 24 Jun 27 11:17:05 PM PDT 24 58160992575 ps
T1043 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.1591509039 Jun 27 08:18:17 PM PDT 24 Jun 27 08:45:57 PM PDT 24 6970412190 ps
T245 /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.3885117222 Jun 27 08:24:40 PM PDT 24 Jun 27 09:52:57 PM PDT 24 48803867688 ps
T374 /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.1838275007 Jun 27 08:57:39 PM PDT 24 Jun 27 09:05:13 PM PDT 24 4305095610 ps
T775 /workspace/coverage/default/96.chip_sw_all_escalation_resets.1039405508 Jun 27 08:55:53 PM PDT 24 Jun 27 09:04:22 PM PDT 24 6075742358 ps
T1044 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.2097866508 Jun 27 08:17:43 PM PDT 24 Jun 27 08:24:13 PM PDT 24 4097439256 ps
T392 /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.3911282017 Jun 27 08:19:12 PM PDT 24 Jun 27 08:24:47 PM PDT 24 3103894824 ps
T1045 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.2136420583 Jun 27 08:36:18 PM PDT 24 Jun 27 09:04:21 PM PDT 24 25081618942 ps
T417 /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3008766045 Jun 27 08:56:10 PM PDT 24 Jun 27 09:02:21 PM PDT 24 3524385752 ps
T763 /workspace/coverage/default/81.chip_sw_all_escalation_resets.97291499 Jun 27 08:56:52 PM PDT 24 Jun 27 09:08:35 PM PDT 24 5456358940 ps
T1046 /workspace/coverage/default/0.chip_tap_straps_rma.3538927984 Jun 27 08:18:53 PM PDT 24 Jun 27 08:24:19 PM PDT 24 4303463803 ps
T1047 /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.1365179366 Jun 27 08:17:24 PM PDT 24 Jun 27 08:24:06 PM PDT 24 3088966996 ps
T1048 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.3084298518 Jun 27 08:35:39 PM PDT 24 Jun 27 09:32:05 PM PDT 24 15231077148 ps
T1049 /workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.4195039840 Jun 27 08:46:53 PM PDT 24 Jun 27 09:38:40 PM PDT 24 16189562168 ps
T1050 /workspace/coverage/default/2.chip_sival_flash_info_access.754828554 Jun 27 08:34:54 PM PDT 24 Jun 27 08:40:24 PM PDT 24 2579577668 ps
T1051 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.2620576141 Jun 27 08:18:35 PM PDT 24 Jun 27 08:23:47 PM PDT 24 2823402974 ps
T356 /workspace/coverage/default/2.chip_sw_hmac_enc.832600933 Jun 27 08:37:10 PM PDT 24 Jun 27 08:40:53 PM PDT 24 3032836500 ps
T180 /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.200028669 Jun 27 08:18:29 PM PDT 24 Jun 27 08:21:01 PM PDT 24 3087176853 ps
T375 /workspace/coverage/default/48.chip_sw_all_escalation_resets.3261136876 Jun 27 08:51:16 PM PDT 24 Jun 27 08:59:29 PM PDT 24 4405535490 ps
T271 /workspace/coverage/default/51.chip_sw_all_escalation_resets.992086466 Jun 27 08:52:48 PM PDT 24 Jun 27 09:01:41 PM PDT 24 4113890660 ps
T1052 /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.1274815522 Jun 27 08:48:36 PM PDT 24 Jun 27 09:02:34 PM PDT 24 10020066891 ps
T1053 /workspace/coverage/default/1.chip_sw_clkmgr_jitter.2254171117 Jun 27 08:29:44 PM PDT 24 Jun 27 08:34:22 PM PDT 24 3120796761 ps
T246 /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.3948293353 Jun 27 08:49:30 PM PDT 24 Jun 27 09:18:03 PM PDT 24 24520887372 ps
T1054 /workspace/coverage/default/0.chip_sw_flash_ctrl_access.3989276675 Jun 27 08:17:13 PM PDT 24 Jun 27 08:35:25 PM PDT 24 5693361558 ps
T1055 /workspace/coverage/default/0.chip_sw_hmac_enc.799081927 Jun 27 08:19:59 PM PDT 24 Jun 27 08:23:49 PM PDT 24 3486133910 ps
T1056 /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.755280565 Jun 27 08:21:56 PM PDT 24 Jun 27 08:30:04 PM PDT 24 3875790748 ps
T1057 /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.207130448 Jun 27 08:45:39 PM PDT 24 Jun 27 08:56:48 PM PDT 24 6050210490 ps
T1058 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.421532997 Jun 27 08:39:12 PM PDT 24 Jun 27 08:50:25 PM PDT 24 4874911160 ps
T724 /workspace/coverage/default/32.chip_sw_all_escalation_resets.124935206 Jun 27 08:49:18 PM PDT 24 Jun 27 09:00:08 PM PDT 24 5642063016 ps
T1059 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.624469417 Jun 27 08:36:09 PM PDT 24 Jun 27 08:40:21 PM PDT 24 2355079696 ps
T1060 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.2745042062 Jun 27 08:27:50 PM PDT 24 Jun 27 10:35:15 PM PDT 24 24395724764 ps
T312 /workspace/coverage/default/2.chip_plic_all_irqs_0.3930125526 Jun 27 08:39:30 PM PDT 24 Jun 27 09:02:40 PM PDT 24 5474679676 ps
T1061 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.1612329449 Jun 27 08:30:16 PM PDT 24 Jun 27 08:33:24 PM PDT 24 3080976921 ps
T1062 /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.2528102199 Jun 27 08:24:36 PM PDT 24 Jun 27 08:32:29 PM PDT 24 4300269200 ps
T1063 /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.1173662344 Jun 27 08:37:59 PM PDT 24 Jun 27 08:46:59 PM PDT 24 5264956100 ps
T1064 /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.297159160 Jun 27 08:17:01 PM PDT 24 Jun 27 08:29:46 PM PDT 24 11112243438 ps
T1065 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.2659558296 Jun 27 08:25:46 PM PDT 24 Jun 27 09:29:06 PM PDT 24 15282679552 ps
T1066 /workspace/coverage/default/0.chip_sw_edn_sw_mode.712035388 Jun 27 08:23:14 PM PDT 24 Jun 27 09:00:48 PM PDT 24 9155323752 ps
T1067 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.474438754 Jun 27 08:37:51 PM PDT 24 Jun 27 08:53:42 PM PDT 24 6614490706 ps
T342 /workspace/coverage/default/52.chip_sw_all_escalation_resets.635595319 Jun 27 08:51:55 PM PDT 24 Jun 27 09:03:28 PM PDT 24 5628067480 ps
T1068 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.2081870157 Jun 27 08:17:08 PM PDT 24 Jun 27 09:52:46 PM PDT 24 48676026580 ps
T1069 /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.3326520471 Jun 27 08:23:05 PM PDT 24 Jun 27 08:28:33 PM PDT 24 3491587880 ps
T722 /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.2419412788 Jun 27 08:53:37 PM PDT 24 Jun 27 08:57:57 PM PDT 24 3863323222 ps
T321 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.2810944691 Jun 27 08:24:18 PM PDT 24 Jun 27 08:40:12 PM PDT 24 4875800962 ps
T729 /workspace/coverage/default/68.chip_sw_all_escalation_resets.4108195904 Jun 27 08:54:40 PM PDT 24 Jun 27 09:05:02 PM PDT 24 6494201984 ps
T1070 /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.139466726 Jun 27 08:23:36 PM PDT 24 Jun 27 08:28:36 PM PDT 24 3033686712 ps
T1071 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.3511322693 Jun 27 08:55:21 PM PDT 24 Jun 27 10:02:14 PM PDT 24 15503784638 ps
T661 /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.523633504 Jun 27 08:20:28 PM PDT 24 Jun 27 08:29:31 PM PDT 24 4792278941 ps
T1072 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.443400375 Jun 27 08:17:00 PM PDT 24 Jun 27 08:27:28 PM PDT 24 4163928448 ps
T741 /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.2646060556 Jun 27 08:54:18 PM PDT 24 Jun 27 09:00:19 PM PDT 24 3702303878 ps
T1073 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.3237275935 Jun 27 08:27:03 PM PDT 24 Jun 27 09:33:23 PM PDT 24 15203256040 ps
T1074 /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.852681826 Jun 27 08:19:35 PM PDT 24 Jun 27 11:51:11 PM PDT 24 255845579700 ps
T1075 /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.3356375287 Jun 27 08:35:30 PM PDT 24 Jun 27 09:07:38 PM PDT 24 29370920556 ps
T1076 /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.2351140843 Jun 27 08:54:36 PM PDT 24 Jun 27 09:01:50 PM PDT 24 4321680840 ps
T1077 /workspace/coverage/default/1.chip_sw_flash_init.862084741 Jun 27 08:22:33 PM PDT 24 Jun 27 08:56:57 PM PDT 24 21392844972 ps
T736 /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.3311190759 Jun 27 08:49:12 PM PDT 24 Jun 27 08:55:51 PM PDT 24 4133700780 ps
T1078 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.4074281504 Jun 27 08:20:46 PM PDT 24 Jun 27 08:24:47 PM PDT 24 2219633254 ps
T131 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.514672442 Jun 27 08:19:07 PM PDT 24 Jun 27 08:25:34 PM PDT 24 5828816570 ps
T1079 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.2107142401 Jun 27 08:38:25 PM PDT 24 Jun 27 08:50:17 PM PDT 24 4135905964 ps
T1080 /workspace/coverage/default/0.chip_sw_power_idle_load.2053819245 Jun 27 08:22:22 PM PDT 24 Jun 27 08:36:09 PM PDT 24 3649887428 ps
T1081 /workspace/coverage/default/82.chip_sw_all_escalation_resets.3369950100 Jun 27 08:54:45 PM PDT 24 Jun 27 09:03:38 PM PDT 24 4890214794 ps
T1082 /workspace/coverage/default/1.chip_sw_hmac_enc.755401185 Jun 27 08:28:31 PM PDT 24 Jun 27 08:33:40 PM PDT 24 2905523494 ps
T1083 /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.2247420488 Jun 27 08:32:06 PM PDT 24 Jun 27 08:36:03 PM PDT 24 2795035894 ps
T785 /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.2323359769 Jun 27 08:46:54 PM PDT 24 Jun 27 08:54:15 PM PDT 24 3589983520 ps
T132 /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.1424391441 Jun 27 08:45:00 PM PDT 24 Jun 27 08:57:16 PM PDT 24 4882035878 ps
T1084 /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.665926838 Jun 27 08:37:34 PM PDT 24 Jun 28 12:11:49 AM PDT 24 255477146880 ps
T758 /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.884418100 Jun 27 08:54:32 PM PDT 24 Jun 27 08:59:34 PM PDT 24 3360884760 ps
T38 /workspace/coverage/default/2.chip_sw_gpio.489526760 Jun 27 08:34:37 PM PDT 24 Jun 27 08:43:32 PM PDT 24 3718097960 ps
T1085 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.287427418 Jun 27 08:38:39 PM PDT 24 Jun 27 09:04:15 PM PDT 24 16509792105 ps
T169 /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.673980201 Jun 27 08:16:59 PM PDT 24 Jun 27 08:29:12 PM PDT 24 6051756956 ps
T663 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1597635638 Jun 27 08:23:28 PM PDT 24 Jun 27 08:25:14 PM PDT 24 1918501039 ps
T752 /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.3338913502 Jun 27 08:53:33 PM PDT 24 Jun 27 09:00:02 PM PDT 24 3883538180 ps
T1086 /workspace/coverage/default/1.chip_sw_example_rom.390670671 Jun 27 08:20:39 PM PDT 24 Jun 27 08:23:02 PM PDT 24 2849958156 ps
T710 /workspace/coverage/default/92.chip_sw_all_escalation_resets.2019921096 Jun 27 08:54:38 PM PDT 24 Jun 27 09:06:01 PM PDT 24 5969843544 ps
T102 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3393883360 Jun 27 08:30:15 PM PDT 24 Jun 27 08:39:32 PM PDT 24 7663752254 ps
T345 /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.1025878248 Jun 27 08:39:16 PM PDT 24 Jun 27 08:43:06 PM PDT 24 2908430940 ps
T394 /workspace/coverage/default/2.chip_sw_kmac_app_rom.1085232322 Jun 27 08:39:15 PM PDT 24 Jun 27 08:44:28 PM PDT 24 3065470116 ps
T1087 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.419015516 Jun 27 08:33:49 PM PDT 24 Jun 27 08:45:11 PM PDT 24 4927639770 ps
T1088 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.814269990 Jun 27 08:21:13 PM PDT 24 Jun 27 08:30:01 PM PDT 24 4144201270 ps
T746 /workspace/coverage/default/61.chip_sw_all_escalation_resets.49988600 Jun 27 08:53:42 PM PDT 24 Jun 27 09:01:53 PM PDT 24 5025605300 ps
T1089 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.2626510220 Jun 27 08:23:47 PM PDT 24 Jun 27 09:10:00 PM PDT 24 11041687908 ps
T742 /workspace/coverage/default/19.chip_sw_all_escalation_resets.1030501522 Jun 27 08:49:14 PM PDT 24 Jun 27 08:58:23 PM PDT 24 5358371422 ps
T1090 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.3332982716 Jun 27 08:39:15 PM PDT 24 Jun 27 09:26:30 PM PDT 24 20234827609 ps
T762 /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.2820953285 Jun 27 08:54:16 PM PDT 24 Jun 27 08:58:37 PM PDT 24 3857735168 ps
T1091 /workspace/coverage/default/2.rom_e2e_asm_init_rma.3174904165 Jun 27 08:47:20 PM PDT 24 Jun 27 09:43:42 PM PDT 24 14532633516 ps
T1092 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.3050049190 Jun 27 08:26:47 PM PDT 24 Jun 27 09:32:04 PM PDT 24 15020662936 ps
T383 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.757983417 Jun 27 08:27:45 PM PDT 24 Jun 27 09:46:14 PM PDT 24 17917666564 ps
T725 /workspace/coverage/default/14.chip_sw_all_escalation_resets.2619137061 Jun 27 08:47:19 PM PDT 24 Jun 27 08:58:11 PM PDT 24 5232017282 ps
T24 /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3151827287 Jun 27 08:16:32 PM PDT 24 Jun 27 08:21:25 PM PDT 24 3203631029 ps
T1093 /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.1799881789 Jun 27 08:50:02 PM PDT 24 Jun 27 08:57:09 PM PDT 24 3824195504 ps
T776 /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.145047713 Jun 27 08:52:16 PM PDT 24 Jun 27 08:58:55 PM PDT 24 4031097440 ps
T1094 /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.1531331807 Jun 27 08:26:07 PM PDT 24 Jun 27 08:30:29 PM PDT 24 3005847960 ps
T353 /workspace/coverage/default/0.chip_sw_aon_timer_irq.4171565657 Jun 27 08:19:41 PM PDT 24 Jun 27 08:26:46 PM PDT 24 4734673880 ps
T1095 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.3245113248 Jun 27 08:22:18 PM PDT 24 Jun 27 08:33:42 PM PDT 24 4628203208 ps
T272 /workspace/coverage/default/95.chip_sw_all_escalation_resets.588512508 Jun 27 08:55:34 PM PDT 24 Jun 27 09:05:19 PM PDT 24 5045265000 ps
T1096 /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.609403293 Jun 27 08:36:58 PM PDT 24 Jun 27 09:10:03 PM PDT 24 12426128136 ps
T346 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.980756009 Jun 27 08:20:34 PM PDT 24 Jun 27 08:34:52 PM PDT 24 5184805924 ps
T1097 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.448364001 Jun 27 08:22:35 PM PDT 24 Jun 27 08:28:20 PM PDT 24 3481362744 ps
T1098 /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.994273462 Jun 27 08:20:19 PM PDT 24 Jun 27 08:33:08 PM PDT 24 5146786458 ps
T1099 /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.2748071275 Jun 27 08:51:13 PM PDT 24 Jun 27 08:59:57 PM PDT 24 4173732208 ps
T1100 /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.2062507441 Jun 27 08:30:36 PM PDT 24 Jun 27 08:51:38 PM PDT 24 9646627164 ps
T1101 /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.3194488864 Jun 27 08:35:05 PM PDT 24 Jun 27 09:11:06 PM PDT 24 24776989300 ps
T1102 /workspace/coverage/default/1.chip_sw_hmac_multistream.2844926869 Jun 27 08:28:06 PM PDT 24 Jun 27 08:59:45 PM PDT 24 8886158640 ps
T1103 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.1800813289 Jun 27 08:39:48 PM PDT 24 Jun 27 08:50:21 PM PDT 24 5024634209 ps
T1104 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2711285757 Jun 27 08:21:13 PM PDT 24 Jun 27 08:34:33 PM PDT 24 4199250704 ps
T1105 /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.1124477409 Jun 27 08:44:46 PM PDT 24 Jun 27 08:48:30 PM PDT 24 2189225110 ps
T1106 /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.4226806917 Jun 27 08:38:42 PM PDT 24 Jun 27 08:45:41 PM PDT 24 4582596708 ps
T330 /workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.4133402436 Jun 27 08:40:36 PM PDT 24 Jun 27 08:49:46 PM PDT 24 3398213346 ps
T782 /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.1513934071 Jun 27 08:52:05 PM PDT 24 Jun 27 08:58:29 PM PDT 24 3807967060 ps
T749 /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.3931253223 Jun 27 08:54:08 PM PDT 24 Jun 27 09:02:05 PM PDT 24 3798265972 ps
T1107 /workspace/coverage/default/1.chip_sw_power_idle_load.519901262 Jun 27 08:32:13 PM PDT 24 Jun 27 08:43:32 PM PDT 24 4194233584 ps
T783 /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2824179064 Jun 27 08:49:10 PM PDT 24 Jun 27 08:57:07 PM PDT 24 3806785940 ps
T14 /workspace/coverage/default/0.chip_sw_sleep_pin_wake.2426194028 Jun 27 08:16:04 PM PDT 24 Jun 27 08:25:27 PM PDT 24 7153542310 ps
T1108 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.1673375368 Jun 27 08:37:53 PM PDT 24 Jun 27 08:41:51 PM PDT 24 3019236238 ps
T682 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.3914067702 Jun 27 08:17:22 PM PDT 24 Jun 27 08:21:21 PM PDT 24 3383113456 ps
T1109 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.2523288582 Jun 27 08:20:04 PM PDT 24 Jun 27 08:24:45 PM PDT 24 3201100971 ps
T1110 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.2165729759 Jun 27 08:21:24 PM PDT 24 Jun 27 08:50:26 PM PDT 24 8939370260 ps
T1111 /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.3386636154 Jun 27 08:35:10 PM PDT 24 Jun 27 08:39:57 PM PDT 24 3309838636 ps
T135 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3562309601 Jun 27 08:39:10 PM PDT 24 Jun 27 08:48:24 PM PDT 24 5259871192 ps
T1112 /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.3574800349 Jun 27 08:39:15 PM PDT 24 Jun 27 08:49:18 PM PDT 24 5472161340 ps
T1113 /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.351584972 Jun 27 08:35:23 PM PDT 24 Jun 27 08:59:37 PM PDT 24 8341366528 ps
T1114 /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.3012615618 Jun 27 08:16:49 PM PDT 24 Jun 27 08:24:56 PM PDT 24 3786659448 ps
T1115 /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.595729827 Jun 27 08:38:18 PM PDT 24 Jun 27 08:42:13 PM PDT 24 2919299052 ps
T751 /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.3633679326 Jun 27 08:50:51 PM PDT 24 Jun 27 08:58:43 PM PDT 24 4065525870 ps
T1116 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.653249333 Jun 27 08:27:24 PM PDT 24 Jun 27 08:45:27 PM PDT 24 6810323896 ps
T664 /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.303014684 Jun 27 08:36:12 PM PDT 24 Jun 27 08:38:43 PM PDT 24 3383141099 ps
T731 /workspace/coverage/default/20.chip_sw_all_escalation_resets.2700134299 Jun 27 08:49:54 PM PDT 24 Jun 27 09:00:41 PM PDT 24 5778184014 ps
T1117 /workspace/coverage/default/1.chip_sw_aes_enc.346988959 Jun 27 08:35:00 PM PDT 24 Jun 27 08:40:43 PM PDT 24 3417485202 ps
T39 /workspace/coverage/default/0.chip_sw_gpio.2403141549 Jun 27 08:19:09 PM PDT 24 Jun 27 08:27:55 PM PDT 24 3597595000 ps
T1118 /workspace/coverage/default/1.rom_e2e_asm_init_rma.1979485046 Jun 27 08:38:08 PM PDT 24 Jun 27 09:35:25 PM PDT 24 13992213484 ps
T1119 /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.2975696419 Jun 27 08:20:42 PM PDT 24 Jun 27 08:26:06 PM PDT 24 3039598632 ps
T1120 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.3430954270 Jun 27 08:23:19 PM PDT 24 Jun 27 08:48:22 PM PDT 24 8947485024 ps
T1121 /workspace/coverage/default/0.rom_e2e_asm_init_prod.1533788689 Jun 27 08:26:27 PM PDT 24 Jun 27 09:30:15 PM PDT 24 15506952283 ps
T1122 /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.893762451 Jun 27 08:26:15 PM PDT 24 Jun 27 08:31:33 PM PDT 24 3360860098 ps
T1123 /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.1542164067 Jun 27 08:39:31 PM PDT 24 Jun 27 09:21:12 PM PDT 24 31262464542 ps
T1124 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2234832467 Jun 27 08:18:11 PM PDT 24 Jun 27 08:30:39 PM PDT 24 4377064728 ps
T721 /workspace/coverage/default/54.chip_sw_all_escalation_resets.102650179 Jun 27 08:51:15 PM PDT 24 Jun 27 09:02:07 PM PDT 24 5224044500 ps
T1125 /workspace/coverage/default/0.chip_sw_kmac_entropy.3290959123 Jun 27 08:19:13 PM PDT 24 Jun 27 08:23:39 PM PDT 24 3141507854 ps
T780 /workspace/coverage/default/34.chip_sw_all_escalation_resets.4243351006 Jun 27 08:53:51 PM PDT 24 Jun 27 09:02:22 PM PDT 24 6106525560 ps
T1126 /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.227419601 Jun 27 08:30:25 PM PDT 24 Jun 27 08:34:16 PM PDT 24 2412495970 ps
T1127 /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.3218930483 Jun 27 08:21:57 PM PDT 24 Jun 27 08:44:20 PM PDT 24 8635449817 ps
T665 /workspace/coverage/default/0.rom_volatile_raw_unlock.203869427 Jun 27 08:26:40 PM PDT 24 Jun 27 08:28:53 PM PDT 24 2722177991 ps
T338 /workspace/coverage/default/2.chip_sw_pattgen_ios.3134355944 Jun 27 08:32:47 PM PDT 24 Jun 27 08:37:27 PM PDT 24 2181635040 ps
T1128 /workspace/coverage/default/0.chip_sw_aes_entropy.1410113842 Jun 27 08:18:11 PM PDT 24 Jun 27 08:22:37 PM PDT 24 2681952264 ps
T1129 /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.650136282 Jun 27 08:23:11 PM PDT 24 Jun 27 08:30:58 PM PDT 24 3776360800 ps
T236 /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.4055774633 Jun 27 08:28:15 PM PDT 24 Jun 27 09:32:01 PM PDT 24 16903696408 ps
T1130 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1692144271 Jun 27 08:19:38 PM PDT 24 Jun 27 08:53:53 PM PDT 24 13232592865 ps
T1131 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.1067321165 Jun 27 08:34:25 PM PDT 24 Jun 27 09:19:39 PM PDT 24 20540533404 ps
T1132 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.2710800761 Jun 27 08:23:17 PM PDT 24 Jun 27 08:48:55 PM PDT 24 8469528416 ps
T16 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.2757037937 Jun 27 08:39:58 PM PDT 24 Jun 27 09:07:10 PM PDT 24 21222567984 ps
T1133 /workspace/coverage/default/0.chip_sw_rv_timer_irq.434037916 Jun 27 08:18:25 PM PDT 24 Jun 27 08:21:39 PM PDT 24 2858266512 ps
T279 /workspace/coverage/default/1.chip_sw_data_integrity_escalation.3625354463 Jun 27 08:24:30 PM PDT 24 Jun 27 08:36:36 PM PDT 24 4939507412 ps
T1134 /workspace/coverage/default/1.chip_sival_flash_info_access.2421683884 Jun 27 08:27:38 PM PDT 24 Jun 27 08:34:35 PM PDT 24 3280477400 ps
T1135 /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.3598940699 Jun 27 08:30:20 PM PDT 24 Jun 27 09:03:29 PM PDT 24 18136944681 ps
T755 /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.1883393597 Jun 27 08:51:53 PM PDT 24 Jun 27 08:57:46 PM PDT 24 3971529644 ps
T1136 /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.3319767701 Jun 27 08:18:10 PM PDT 24 Jun 27 08:58:29 PM PDT 24 31995014643 ps
T1137 /workspace/coverage/default/1.chip_sw_hmac_smoketest.3928349417 Jun 27 08:31:39 PM PDT 24 Jun 27 08:38:14 PM PDT 24 2970901520 ps
T1138 /workspace/coverage/default/46.chip_sw_all_escalation_resets.2985703785 Jun 27 08:51:46 PM PDT 24 Jun 27 09:00:00 PM PDT 24 4712302240 ps
T1139 /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.169695694 Jun 27 08:27:04 PM PDT 24 Jun 27 11:58:32 PM PDT 24 255552229404 ps
T331 /workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.1191475027 Jun 27 08:30:37 PM PDT 24 Jun 27 08:38:12 PM PDT 24 3403348402 ps
T1140 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.1771759563 Jun 27 08:34:33 PM PDT 24 Jun 27 08:48:08 PM PDT 24 4156962428 ps
T1141 /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.4196923498 Jun 27 08:46:44 PM PDT 24 Jun 27 08:52:26 PM PDT 24 2800423052 ps
T1142 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.2644507411 Jun 27 08:31:36 PM PDT 24 Jun 27 08:42:45 PM PDT 24 7185375656 ps
T1143 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3225411001 Jun 27 08:21:06 PM PDT 24 Jun 27 08:30:23 PM PDT 24 4682672440 ps
T702 /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.3359244403 Jun 27 08:53:30 PM PDT 24 Jun 27 08:58:49 PM PDT 24 3257662200 ps
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