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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.14 95.59 93.98 95.45 94.77 97.53 99.53


Total test records in report: 2877
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T1144 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2237861228 Jun 27 08:37:46 PM PDT 24 Jun 27 08:57:53 PM PDT 24 9404692386 ps
T1145 /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.842670904 Jun 27 08:16:58 PM PDT 24 Jun 27 08:21:46 PM PDT 24 2978818412 ps
T301 /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.1214853747 Jun 27 08:20:15 PM PDT 24 Jun 27 08:25:48 PM PDT 24 3553184948 ps
T1146 /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.1992379581 Jun 27 08:36:49 PM PDT 24 Jun 27 09:17:27 PM PDT 24 10873381330 ps
T166 /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2883784274 Jun 27 08:16:39 PM PDT 24 Jun 27 08:20:32 PM PDT 24 2355085387 ps
T1147 /workspace/coverage/default/1.rom_e2e_static_critical.3742747929 Jun 27 08:38:05 PM PDT 24 Jun 27 09:40:10 PM PDT 24 16775883408 ps
T1148 /workspace/coverage/default/28.chip_sw_all_escalation_resets.3085909852 Jun 27 08:50:06 PM PDT 24 Jun 27 08:59:45 PM PDT 24 5100232424 ps
T157 /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.1868028228 Jun 27 08:16:52 PM PDT 24 Jun 27 11:21:45 PM PDT 24 59199807085 ps
T395 /workspace/coverage/default/13.chip_sw_all_escalation_resets.1788363359 Jun 27 08:48:34 PM PDT 24 Jun 27 08:57:48 PM PDT 24 4844936422 ps
T1149 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2638696520 Jun 27 08:44:09 PM PDT 24 Jun 27 08:52:58 PM PDT 24 4111534760 ps
T1150 /workspace/coverage/default/5.chip_sw_data_integrity_escalation.676194434 Jun 27 08:45:53 PM PDT 24 Jun 27 08:58:49 PM PDT 24 6728257780 ps
T1151 /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.2872520874 Jun 27 08:25:49 PM PDT 24 Jun 27 08:34:34 PM PDT 24 7352820177 ps
T1152 /workspace/coverage/default/2.chip_sw_rv_timer_irq.1601644454 Jun 27 08:36:20 PM PDT 24 Jun 27 08:40:10 PM PDT 24 3304468808 ps
T777 /workspace/coverage/default/9.chip_sw_all_escalation_resets.1483824360 Jun 27 08:47:30 PM PDT 24 Jun 27 09:00:01 PM PDT 24 5773030748 ps
T40 /workspace/coverage/default/1.chip_sw_gpio.3953755096 Jun 27 08:24:29 PM PDT 24 Jun 27 08:33:38 PM PDT 24 3651411920 ps
T1153 /workspace/coverage/default/7.chip_sw_all_escalation_resets.2523976 Jun 27 08:46:17 PM PDT 24 Jun 27 08:57:41 PM PDT 24 6101399096 ps
T1154 /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.284641938 Jun 27 08:19:24 PM PDT 24 Jun 27 09:04:04 PM PDT 24 24032942702 ps
T1155 /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.1667875660 Jun 27 08:33:13 PM PDT 24 Jun 27 08:42:26 PM PDT 24 4292434972 ps
T1156 /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.100088715 Jun 27 08:25:55 PM PDT 24 Jun 27 08:29:58 PM PDT 24 2432935720 ps
T373 /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2566097045 Jun 27 08:31:17 PM PDT 24 Jun 27 08:40:47 PM PDT 24 6874526364 ps
T1157 /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1918915347 Jun 27 08:25:54 PM PDT 24 Jun 27 08:33:55 PM PDT 24 19616757436 ps
T136 /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.3191676784 Jun 27 08:57:00 PM PDT 24 Jun 27 09:15:30 PM PDT 24 7586092020 ps
T414 /workspace/coverage/default/0.rom_e2e_jtag_inject_rma.2009912066 Jun 27 08:21:39 PM PDT 24 Jun 27 09:04:27 PM PDT 24 31943768391 ps
T319 /workspace/coverage/default/2.chip_sw_entropy_src_csrng.3829461108 Jun 27 08:38:14 PM PDT 24 Jun 27 09:03:45 PM PDT 24 6998403304 ps
T1158 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3523574693 Jun 27 08:30:51 PM PDT 24 Jun 27 08:50:30 PM PDT 24 7534560228 ps
T1159 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3052234235 Jun 27 08:36:40 PM PDT 24 Jun 27 08:45:26 PM PDT 24 6262150600 ps
T1160 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.3797871441 Jun 27 08:17:34 PM PDT 24 Jun 27 08:19:29 PM PDT 24 2545660779 ps
T1161 /workspace/coverage/default/0.chip_sw_ast_clk_outputs.2056008158 Jun 27 08:20:27 PM PDT 24 Jun 27 08:36:40 PM PDT 24 7569230606 ps
T1162 /workspace/coverage/default/66.chip_sw_all_escalation_resets.3772942467 Jun 27 08:55:16 PM PDT 24 Jun 27 09:05:50 PM PDT 24 6304360776 ps
T727 /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.804354536 Jun 27 08:54:33 PM PDT 24 Jun 27 09:01:24 PM PDT 24 3385433432 ps
T1163 /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.2645956510 Jun 27 08:47:46 PM PDT 24 Jun 27 10:18:52 PM PDT 24 26709584318 ps
T1164 /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.2241636230 Jun 27 08:24:27 PM PDT 24 Jun 27 08:27:51 PM PDT 24 2716950510 ps
T767 /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.3369807496 Jun 27 08:53:51 PM PDT 24 Jun 27 09:00:19 PM PDT 24 3477732320 ps
T369 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.551486907 Jun 27 08:25:11 PM PDT 24 Jun 27 08:41:15 PM PDT 24 5788682272 ps
T1165 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.66469615 Jun 27 08:18:33 PM PDT 24 Jun 27 08:41:32 PM PDT 24 8266395712 ps
T1166 /workspace/coverage/default/2.chip_sw_hmac_multistream.3499562931 Jun 27 08:39:13 PM PDT 24 Jun 27 09:14:54 PM PDT 24 8118912848 ps
T1167 /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.281847463 Jun 27 08:26:40 PM PDT 24 Jun 27 08:31:41 PM PDT 24 3167972976 ps
T1168 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.4205287879 Jun 27 08:19:50 PM PDT 24 Jun 27 08:51:47 PM PDT 24 21447053128 ps
T1169 /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.309330144 Jun 27 08:19:45 PM PDT 24 Jun 27 08:41:07 PM PDT 24 5622069456 ps
T1170 /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.1938986633 Jun 27 08:33:33 PM PDT 24 Jun 27 08:42:15 PM PDT 24 3951894312 ps
T411 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1298600133 Jun 27 08:29:40 PM PDT 24 Jun 27 09:01:45 PM PDT 24 24438335424 ps
T662 /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.1569564189 Jun 27 08:40:21 PM PDT 24 Jun 27 08:48:21 PM PDT 24 4781450928 ps
T15 /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.147067290 Jun 27 08:40:30 PM PDT 24 Jun 27 08:46:29 PM PDT 24 3759545974 ps
T192 /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.3946956008 Jun 27 08:34:44 PM PDT 24 Jun 27 10:01:43 PM PDT 24 43829988660 ps
T1171 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.409658267 Jun 27 08:17:32 PM PDT 24 Jun 27 08:32:58 PM PDT 24 8446712900 ps
T1172 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.1666047398 Jun 27 08:33:50 PM PDT 24 Jun 27 08:45:15 PM PDT 24 4741636872 ps
T1173 /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.1114339947 Jun 27 08:22:48 PM PDT 24 Jun 27 08:26:11 PM PDT 24 2736971860 ps
T734 /workspace/coverage/default/24.chip_sw_all_escalation_resets.3182484657 Jun 27 08:49:04 PM PDT 24 Jun 27 08:58:12 PM PDT 24 5086326400 ps
T1174 /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.4264425426 Jun 27 08:35:14 PM PDT 24 Jun 27 08:42:09 PM PDT 24 2936134168 ps
T1175 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3406653753 Jun 27 08:36:08 PM PDT 24 Jun 27 09:25:32 PM PDT 24 38146412664 ps
T768 /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.1918992516 Jun 27 08:48:42 PM PDT 24 Jun 27 08:55:38 PM PDT 24 3802592580 ps
T1176 /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.2108123594 Jun 27 08:38:04 PM PDT 24 Jun 27 08:44:55 PM PDT 24 3080073670 ps
T1177 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1742967505 Jun 27 08:28:32 PM PDT 24 Jun 27 10:15:15 PM PDT 24 24182469656 ps
T1178 /workspace/coverage/default/2.chip_sw_example_rom.2648801582 Jun 27 08:32:53 PM PDT 24 Jun 27 08:35:06 PM PDT 24 2230885200 ps
T1179 /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.4144686143 Jun 27 08:45:03 PM PDT 24 Jun 27 09:09:56 PM PDT 24 8464386664 ps
T1180 /workspace/coverage/default/2.chip_sw_kmac_entropy.2412012562 Jun 27 08:34:03 PM PDT 24 Jun 27 08:37:41 PM PDT 24 2647883016 ps
T1181 /workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.4280319769 Jun 27 08:30:48 PM PDT 24 Jun 27 08:35:39 PM PDT 24 3420827800 ps
T25 /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.56371162 Jun 27 08:22:19 PM PDT 24 Jun 27 08:28:53 PM PDT 24 2768847611 ps
T1182 /workspace/coverage/default/2.chip_sw_flash_crash_alert.2525385084 Jun 27 08:41:25 PM PDT 24 Jun 27 08:53:09 PM PDT 24 4623475008 ps
T1183 /workspace/coverage/default/2.rom_e2e_asm_init_dev.2925589911 Jun 27 08:47:38 PM PDT 24 Jun 27 09:56:21 PM PDT 24 15651029480 ps
T1184 /workspace/coverage/default/0.chip_sw_uart_tx_rx.334045617 Jun 27 08:16:55 PM PDT 24 Jun 27 08:28:10 PM PDT 24 4486158774 ps
T306 /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1273652358 Jun 27 08:30:23 PM PDT 24 Jun 27 08:39:48 PM PDT 24 4076593784 ps
T1185 /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.3077541600 Jun 27 08:24:53 PM PDT 24 Jun 27 08:48:28 PM PDT 24 9167712142 ps
T1186 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.1732756026 Jun 27 08:27:33 PM PDT 24 Jun 27 09:05:21 PM PDT 24 11177934020 ps
T1187 /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.2640245062 Jun 27 08:24:08 PM PDT 24 Jun 27 08:28:12 PM PDT 24 2890705672 ps
T1188 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.3850378189 Jun 27 08:36:51 PM PDT 24 Jun 27 09:33:14 PM PDT 24 14343947698 ps
T1189 /workspace/coverage/default/1.chip_sw_kmac_app_rom.3346013006 Jun 27 08:28:21 PM PDT 24 Jun 27 08:33:19 PM PDT 24 2859811162 ps
T1190 /workspace/coverage/default/0.rom_e2e_asm_init_dev.2431983484 Jun 27 08:27:42 PM PDT 24 Jun 27 09:39:00 PM PDT 24 15327048552 ps
T753 /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.4009514455 Jun 27 08:52:26 PM PDT 24 Jun 27 08:58:22 PM PDT 24 3835089528 ps
T1191 /workspace/coverage/default/0.chip_sw_inject_scramble_seed.1552346062 Jun 27 08:17:07 PM PDT 24 Jun 27 11:54:19 PM PDT 24 64494769563 ps
T1192 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2565522739 Jun 27 08:42:06 PM PDT 24 Jun 27 09:00:18 PM PDT 24 7866768046 ps
T1193 /workspace/coverage/default/0.chip_sw_hmac_multistream.1374754860 Jun 27 08:19:36 PM PDT 24 Jun 27 08:55:59 PM PDT 24 7525020980 ps
T1194 /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.2198748681 Jun 27 08:54:00 PM PDT 24 Jun 27 09:00:18 PM PDT 24 3549731518 ps
T1195 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2366825071 Jun 27 08:18:59 PM PDT 24 Jun 27 09:11:09 PM PDT 24 42190844640 ps
T1196 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.646228255 Jun 27 08:17:12 PM PDT 24 Jun 27 08:46:53 PM PDT 24 17306625675 ps
T92 /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.2039363001 Jun 27 08:51:43 PM PDT 24 Jun 27 08:59:42 PM PDT 24 4401836066 ps
T1197 /workspace/coverage/default/2.chip_sw_power_sleep_load.2164404028 Jun 27 08:41:56 PM PDT 24 Jun 27 08:49:42 PM PDT 24 9741444890 ps
T1198 /workspace/coverage/default/0.rom_keymgr_functest.484768714 Jun 27 08:21:19 PM PDT 24 Jun 27 08:27:35 PM PDT 24 3969430696 ps
T1199 /workspace/coverage/default/42.chip_sw_all_escalation_resets.40429639 Jun 27 08:50:17 PM PDT 24 Jun 27 09:03:08 PM PDT 24 5141616152 ps
T1200 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2393397456 Jun 27 08:28:55 PM PDT 24 Jun 27 08:38:55 PM PDT 24 4116600598 ps
T1201 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.330693539 Jun 27 08:28:54 PM PDT 24 Jun 27 08:56:21 PM PDT 24 10160008216 ps
T1202 /workspace/coverage/default/0.rom_e2e_static_critical.140639776 Jun 27 08:26:25 PM PDT 24 Jun 27 09:56:16 PM PDT 24 16789639560 ps
T1203 /workspace/coverage/default/1.chip_sw_aes_masking_off.3514924897 Jun 27 08:25:06 PM PDT 24 Jun 27 08:30:45 PM PDT 24 3341689855 ps
T1204 /workspace/coverage/default/2.chip_sw_aes_entropy.526922999 Jun 27 08:39:19 PM PDT 24 Jun 27 08:42:37 PM PDT 24 2970277568 ps
T766 /workspace/coverage/default/55.chip_sw_all_escalation_resets.3113401871 Jun 27 08:51:43 PM PDT 24 Jun 27 09:00:35 PM PDT 24 4718157320 ps
T1205 /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.2032222287 Jun 27 08:29:41 PM PDT 24 Jun 27 08:35:31 PM PDT 24 4459648776 ps
T1206 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.311217789 Jun 27 08:24:50 PM PDT 24 Jun 27 09:23:07 PM PDT 24 17223024334 ps
T1207 /workspace/coverage/default/2.chip_sw_csrng_smoketest.3059385065 Jun 27 08:43:34 PM PDT 24 Jun 27 08:47:13 PM PDT 24 2756237360 ps
T1208 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.3550434186 Jun 27 08:37:08 PM PDT 24 Jun 27 09:06:08 PM PDT 24 7281482132 ps
T1209 /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.3554838353 Jun 27 08:18:27 PM PDT 24 Jun 27 08:20:46 PM PDT 24 3265418231 ps
T412 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.1332928040 Jun 27 08:19:52 PM PDT 24 Jun 27 08:42:19 PM PDT 24 19890603000 ps
T1210 /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.255699630 Jun 27 08:21:28 PM PDT 24 Jun 27 08:27:55 PM PDT 24 6120362100 ps
T738 /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.3654647714 Jun 27 08:51:30 PM PDT 24 Jun 27 08:59:19 PM PDT 24 3664315400 ps
T191 /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.3491885588 Jun 27 08:16:35 PM PDT 24 Jun 27 09:38:16 PM PDT 24 45065166089 ps
T784 /workspace/coverage/default/67.chip_sw_all_escalation_resets.810592863 Jun 27 08:53:44 PM PDT 24 Jun 27 09:04:31 PM PDT 24 4795283400 ps
T1211 /workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.2243972187 Jun 27 08:18:13 PM PDT 24 Jun 27 08:22:37 PM PDT 24 2897291947 ps
T1212 /workspace/coverage/default/0.chip_sw_edn_kat.2770461011 Jun 27 08:21:33 PM PDT 24 Jun 27 08:32:34 PM PDT 24 3456381280 ps
T1213 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3901985856 Jun 27 08:30:47 PM PDT 24 Jun 27 08:35:58 PM PDT 24 3074952160 ps
T1214 /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.3406603000 Jun 27 08:24:35 PM PDT 24 Jun 27 08:32:17 PM PDT 24 4425702624 ps
T1215 /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.3400704835 Jun 27 08:26:56 PM PDT 24 Jun 27 08:33:47 PM PDT 24 6423244690 ps
T1216 /workspace/coverage/default/2.chip_tap_straps_prod.606090475 Jun 27 08:40:59 PM PDT 24 Jun 27 09:12:22 PM PDT 24 17674184068 ps
T1217 /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.1616794595 Jun 27 08:43:57 PM PDT 24 Jun 27 08:47:31 PM PDT 24 2838094540 ps
T138 /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.2129700709 Jun 27 08:18:50 PM PDT 24 Jun 27 08:25:45 PM PDT 24 5032812492 ps
T302 /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.3793087338 Jun 27 08:46:05 PM PDT 24 Jun 27 08:50:31 PM PDT 24 2500401560 ps
T294 /workspace/coverage/default/98.chip_sw_all_escalation_resets.1666344517 Jun 27 08:55:36 PM PDT 24 Jun 27 09:05:53 PM PDT 24 4499228252 ps
T47 /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.4089389421 Jun 27 08:16:59 PM PDT 24 Jun 27 08:22:40 PM PDT 24 3450122464 ps
T1218 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2204013192 Jun 27 08:21:25 PM PDT 24 Jun 27 08:40:31 PM PDT 24 7109403694 ps
T1219 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.1994276219 Jun 27 08:25:19 PM PDT 24 Jun 27 08:30:16 PM PDT 24 3266190174 ps
T1220 /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.1233294421 Jun 27 08:53:44 PM PDT 24 Jun 27 09:01:59 PM PDT 24 4158095844 ps
T376 /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.893206491 Jun 27 08:56:04 PM PDT 24 Jun 27 09:02:24 PM PDT 24 4017072184 ps
T1221 /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.2022987429 Jun 27 08:23:33 PM PDT 24 Jun 28 12:08:10 AM PDT 24 78241546950 ps
T745 /workspace/coverage/default/25.chip_sw_all_escalation_resets.3130889501 Jun 27 08:48:57 PM PDT 24 Jun 27 09:00:57 PM PDT 24 4729276416 ps
T1222 /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.44181348 Jun 27 08:22:15 PM PDT 24 Jun 27 08:26:10 PM PDT 24 2783915436 ps
T1223 /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.2901982644 Jun 27 08:22:11 PM PDT 24 Jun 27 08:30:03 PM PDT 24 3834965870 ps
T1224 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.369128411 Jun 27 08:27:34 PM PDT 24 Jun 27 10:16:32 PM PDT 24 23492216128 ps
T1225 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.1859034885 Jun 27 08:28:25 PM PDT 24 Jun 27 08:34:16 PM PDT 24 2842719867 ps
T1226 /workspace/coverage/default/2.chip_sw_example_manufacturer.2076090061 Jun 27 08:34:28 PM PDT 24 Jun 27 08:39:30 PM PDT 24 3568857296 ps
T756 /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.514644143 Jun 27 08:54:25 PM PDT 24 Jun 27 08:59:45 PM PDT 24 3583244672 ps
T1227 /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.721978679 Jun 27 08:43:42 PM PDT 24 Jun 27 08:53:16 PM PDT 24 3695287624 ps
T1228 /workspace/coverage/default/94.chip_sw_all_escalation_resets.36957011 Jun 27 08:55:30 PM PDT 24 Jun 27 09:04:41 PM PDT 24 5744163000 ps
T1229 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.175989522 Jun 27 08:28:39 PM PDT 24 Jun 27 09:36:10 PM PDT 24 14478119596 ps
T1230 /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.1870140315 Jun 27 08:46:14 PM PDT 24 Jun 27 09:18:18 PM PDT 24 9481756352 ps
T1231 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1075965080 Jun 27 08:27:44 PM PDT 24 Jun 27 09:09:12 PM PDT 24 21373993651 ps
T1232 /workspace/coverage/default/4.chip_tap_straps_prod.3595390306 Jun 27 08:56:08 PM PDT 24 Jun 27 09:15:23 PM PDT 24 13063590607 ps
T62 /workspace/coverage/default/1.chip_sw_alert_test.2318227903 Jun 27 08:25:59 PM PDT 24 Jun 27 08:32:21 PM PDT 24 3456001164 ps
T1233 /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.2284837782 Jun 27 08:19:49 PM PDT 24 Jun 27 08:23:37 PM PDT 24 2740454744 ps
T1234 /workspace/coverage/default/0.chip_sw_usbdev_vbus.690828175 Jun 27 08:18:07 PM PDT 24 Jun 27 08:22:38 PM PDT 24 2542649944 ps
T1235 /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.2419901964 Jun 27 08:46:26 PM PDT 24 Jun 27 08:52:24 PM PDT 24 3386119224 ps
T1236 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.4201447010 Jun 27 08:27:18 PM PDT 24 Jun 27 08:33:47 PM PDT 24 3386858900 ps
T1237 /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.636246860 Jun 27 08:44:37 PM PDT 24 Jun 27 08:53:35 PM PDT 24 6575144440 ps
T1238 /workspace/coverage/default/43.chip_sw_all_escalation_resets.3969133896 Jun 27 08:51:47 PM PDT 24 Jun 27 09:00:59 PM PDT 24 5819801708 ps
T316 /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.2521845708 Jun 27 08:35:23 PM PDT 24 Jun 27 09:03:23 PM PDT 24 13550733656 ps
T1239 /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.3459695949 Jun 27 08:45:57 PM PDT 24 Jun 27 08:52:11 PM PDT 24 5735256091 ps
T1240 /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.684718121 Jun 27 08:17:40 PM PDT 24 Jun 27 08:28:30 PM PDT 24 8247972611 ps
T1241 /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2578780574 Jun 27 08:52:42 PM PDT 24 Jun 27 08:58:40 PM PDT 24 3668108024 ps
T1242 /workspace/coverage/default/2.chip_sw_clkmgr_jitter.563926401 Jun 27 08:40:43 PM PDT 24 Jun 27 08:44:24 PM PDT 24 2547732451 ps
T1243 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.3495531451 Jun 27 08:46:17 PM PDT 24 Jun 27 09:15:41 PM PDT 24 8223744305 ps
T1244 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.2882499543 Jun 27 08:38:03 PM PDT 24 Jun 27 09:46:01 PM PDT 24 14310504628 ps
T1245 /workspace/coverage/default/0.chip_sw_kmac_smoketest.2788612157 Jun 27 08:21:11 PM PDT 24 Jun 27 08:27:04 PM PDT 24 3118001864 ps
T307 /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1788075564 Jun 27 08:41:43 PM PDT 24 Jun 27 08:52:38 PM PDT 24 5363033734 ps
T1246 /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.2595792324 Jun 27 08:49:34 PM PDT 24 Jun 27 09:00:28 PM PDT 24 4214113544 ps
T1247 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.569977431 Jun 27 08:39:04 PM PDT 24 Jun 27 08:45:49 PM PDT 24 3980630965 ps
T1248 /workspace/coverage/default/1.chip_sw_rv_timer_irq.1082473763 Jun 27 08:24:16 PM PDT 24 Jun 27 08:27:28 PM PDT 24 2638442580 ps
T370 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1329862381 Jun 27 08:17:11 PM PDT 24 Jun 27 08:28:34 PM PDT 24 4756917240 ps
T204 /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.827661635 Jun 27 08:23:01 PM PDT 24 Jun 27 08:30:56 PM PDT 24 4162917131 ps
T1249 /workspace/coverage/default/1.chip_tap_straps_testunlock0.3718366659 Jun 27 08:31:57 PM PDT 24 Jun 27 08:35:45 PM PDT 24 3121638544 ps
T237 /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.2818632970 Jun 27 08:39:23 PM PDT 24 Jun 27 09:43:09 PM PDT 24 14724359698 ps
T1250 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2738334739 Jun 27 08:30:52 PM PDT 24 Jun 27 09:08:16 PM PDT 24 13680226855 ps
T1251 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.2480007457 Jun 27 08:40:29 PM PDT 24 Jun 27 08:48:49 PM PDT 24 5292948792 ps
T1252 /workspace/coverage/default/71.chip_sw_all_escalation_resets.122132093 Jun 27 08:54:04 PM PDT 24 Jun 27 09:03:40 PM PDT 24 5458412904 ps
T1253 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.2771248661 Jun 27 08:25:04 PM PDT 24 Jun 27 08:43:50 PM PDT 24 6097096030 ps
T162 /workspace/coverage/default/2.chip_plic_all_irqs_10.994105211 Jun 27 08:39:27 PM PDT 24 Jun 27 08:50:24 PM PDT 24 4378663152 ps
T1254 /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.3705888839 Jun 27 08:49:00 PM PDT 24 Jun 27 09:24:06 PM PDT 24 13202655138 ps
T320 /workspace/coverage/default/1.chip_sw_entropy_src_csrng.3302545634 Jun 27 08:28:54 PM PDT 24 Jun 27 08:55:07 PM PDT 24 6222656920 ps
T726 /workspace/coverage/default/79.chip_sw_all_escalation_resets.2259907178 Jun 27 08:53:57 PM PDT 24 Jun 27 09:06:04 PM PDT 24 5362517682 ps
T1255 /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.2929821449 Jun 27 08:56:38 PM PDT 24 Jun 27 09:03:00 PM PDT 24 3429922404 ps
T1256 /workspace/coverage/default/0.chip_sw_aes_smoketest.2588019730 Jun 27 08:23:44 PM PDT 24 Jun 27 08:27:59 PM PDT 24 3327440836 ps
T1257 /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.168026715 Jun 27 08:34:58 PM PDT 24 Jun 27 08:42:46 PM PDT 24 4013381416 ps
T1258 /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.555663630 Jun 27 08:16:41 PM PDT 24 Jun 28 01:00:39 AM PDT 24 77556953672 ps
T1259 /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.364252025 Jun 27 08:46:06 PM PDT 24 Jun 27 08:53:51 PM PDT 24 5046064086 ps
T208 /workspace/coverage/default/0.chip_jtag_csr_rw.3687969067 Jun 27 08:11:32 PM PDT 24 Jun 27 08:35:41 PM PDT 24 12319434232 ps
T1260 /workspace/coverage/default/2.chip_sw_all_escalation_resets.4234743634 Jun 27 08:36:21 PM PDT 24 Jun 27 08:48:34 PM PDT 24 5540343170 ps
T1261 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.2690421949 Jun 27 08:17:19 PM PDT 24 Jun 27 08:42:38 PM PDT 24 9527032750 ps
T1262 /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.3152713119 Jun 27 08:56:38 PM PDT 24 Jun 27 10:08:42 PM PDT 24 15495912286 ps
T1263 /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.37552784 Jun 27 08:33:10 PM PDT 24 Jun 28 12:42:19 AM PDT 24 78739336104 ps
T1264 /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.2624791734 Jun 27 08:41:09 PM PDT 24 Jun 27 08:47:58 PM PDT 24 3711128870 ps
T697 /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.1773709282 Jun 27 08:48:59 PM PDT 24 Jun 27 08:57:09 PM PDT 24 4572267528 ps
T728 /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.837844007 Jun 27 08:49:00 PM PDT 24 Jun 27 08:55:50 PM PDT 24 3864670664 ps
T1265 /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.825738647 Jun 27 08:20:24 PM PDT 24 Jun 27 08:28:00 PM PDT 24 3866729938 ps
T1266 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2768223281 Jun 27 08:26:20 PM PDT 24 Jun 27 08:39:07 PM PDT 24 4618248064 ps
T1267 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.2349614082 Jun 27 08:18:01 PM PDT 24 Jun 27 09:05:19 PM PDT 24 13576629746 ps
T1268 /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.3815205231 Jun 27 08:44:48 PM PDT 24 Jun 27 08:51:49 PM PDT 24 3587842628 ps
T1269 /workspace/coverage/default/2.chip_sw_uart_tx_rx.3693258424 Jun 27 08:33:26 PM PDT 24 Jun 27 08:45:07 PM PDT 24 4584205000 ps
T1270 /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.2449764611 Jun 27 08:50:02 PM PDT 24 Jun 27 08:58:04 PM PDT 24 3784315320 ps
T234 /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.4072776857 Jun 27 08:41:13 PM PDT 24 Jun 27 09:19:17 PM PDT 24 13048737168 ps
T1271 /workspace/coverage/default/0.chip_sw_hmac_smoketest.2115384092 Jun 27 08:26:04 PM PDT 24 Jun 27 08:30:51 PM PDT 24 2405348052 ps
T1272 /workspace/coverage/default/0.chip_sw_otbn_randomness.2715656410 Jun 27 08:21:19 PM PDT 24 Jun 27 08:37:53 PM PDT 24 6331491400 ps
T1273 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.882282050 Jun 27 08:22:17 PM PDT 24 Jun 27 08:46:55 PM PDT 24 11732534862 ps
T706 /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.1539587304 Jun 27 08:50:35 PM PDT 24 Jun 27 08:56:56 PM PDT 24 3507571134 ps
T348 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.2386529282 Jun 27 08:35:52 PM PDT 24 Jun 27 08:49:46 PM PDT 24 5098058072 ps
T1274 /workspace/coverage/default/1.chip_sw_edn_auto_mode.514200876 Jun 27 08:28:28 PM PDT 24 Jun 27 08:57:51 PM PDT 24 6276209660 ps
T1275 /workspace/coverage/default/1.chip_sw_aon_timer_irq.2855660434 Jun 27 08:28:10 PM PDT 24 Jun 27 08:34:21 PM PDT 24 3908208784 ps
T1276 /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.504448332 Jun 27 08:37:52 PM PDT 24 Jun 27 08:40:31 PM PDT 24 3235492410 ps
T1277 /workspace/coverage/default/3.chip_tap_straps_dev.2124604925 Jun 27 08:43:49 PM PDT 24 Jun 27 09:09:27 PM PDT 24 13883539069 ps
T1278 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.1269745157 Jun 27 08:20:17 PM PDT 24 Jun 27 08:52:53 PM PDT 24 8219416588 ps
T1279 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.186064380 Jun 27 08:42:00 PM PDT 24 Jun 27 08:54:05 PM PDT 24 4129195748 ps
T1280 /workspace/coverage/default/0.chip_sw_edn_auto_mode.2805822261 Jun 27 08:18:27 PM PDT 24 Jun 27 08:51:38 PM PDT 24 6260079244 ps
T1281 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.3091375407 Jun 27 08:31:01 PM PDT 24 Jun 27 08:35:36 PM PDT 24 3247699271 ps
T1282 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.2422295040 Jun 27 08:34:20 PM PDT 24 Jun 27 08:35:57 PM PDT 24 2559329457 ps
T1283 /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.418104335 Jun 27 08:28:43 PM PDT 24 Jun 27 08:41:01 PM PDT 24 9210831941 ps
T1284 /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.1100079802 Jun 27 08:47:51 PM PDT 24 Jun 27 08:56:09 PM PDT 24 4616150192 ps
T1285 /workspace/coverage/default/1.rom_volatile_raw_unlock.3245369365 Jun 27 08:35:08 PM PDT 24 Jun 27 08:37:08 PM PDT 24 2297533077 ps
T1286 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1516893165 Jun 27 08:29:22 PM PDT 24 Jun 27 08:40:29 PM PDT 24 4110087246 ps
T205 /workspace/coverage/default/0.chip_sw_spi_device_pass_through.4190766794 Jun 27 08:18:10 PM PDT 24 Jun 27 08:29:30 PM PDT 24 6407875236 ps
T695 /workspace/coverage/default/0.chip_sw_pattgen_ios.1139406192 Jun 27 08:15:58 PM PDT 24 Jun 27 08:20:49 PM PDT 24 3503849616 ps
T217 /workspace/coverage/default/2.chip_sw_sleep_pin_wake.2886466073 Jun 27 08:33:24 PM PDT 24 Jun 27 08:38:51 PM PDT 24 2914446760 ps
T1287 /workspace/coverage/default/65.chip_sw_all_escalation_resets.4048281383 Jun 27 08:54:33 PM PDT 24 Jun 27 09:05:58 PM PDT 24 5212902216 ps
T1288 /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.861218028 Jun 27 08:26:12 PM PDT 24 Jun 27 08:37:25 PM PDT 24 5086378220 ps
T1289 /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.1542723719 Jun 27 08:37:51 PM PDT 24 Jun 27 08:47:15 PM PDT 24 5153415976 ps
T1290 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.3173041392 Jun 27 08:44:39 PM PDT 24 Jun 27 08:55:59 PM PDT 24 4589947268 ps
T1291 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.1713280769 Jun 27 08:38:54 PM PDT 24 Jun 27 08:51:01 PM PDT 24 6998337720 ps
T1292 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.863278331 Jun 27 08:43:59 PM PDT 24 Jun 27 08:55:37 PM PDT 24 3850606762 ps
T1293 /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.242791948 Jun 27 08:47:17 PM PDT 24 Jun 27 08:59:17 PM PDT 24 3804970690 ps
T1294 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.1411092068 Jun 27 08:35:57 PM PDT 24 Jun 27 08:40:40 PM PDT 24 3087059740 ps
T238 /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.380104261 Jun 27 08:18:17 PM PDT 24 Jun 27 09:21:02 PM PDT 24 13425889864 ps
T1295 /workspace/coverage/default/27.chip_sw_all_escalation_resets.3416846546 Jun 27 08:49:13 PM PDT 24 Jun 27 09:00:26 PM PDT 24 5576457936 ps
T1296 /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1556069828 Jun 27 08:36:59 PM PDT 24 Jun 27 08:46:25 PM PDT 24 18770819864 ps
T1297 /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3404729068 Jun 27 08:38:58 PM PDT 24 Jun 27 08:45:05 PM PDT 24 6512852782 ps
T328 /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.762626864 Jun 27 08:34:31 PM PDT 24 Jun 27 08:45:51 PM PDT 24 3850183272 ps
T1298 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.2378157671 Jun 27 08:42:05 PM PDT 24 Jun 27 08:47:10 PM PDT 24 3515258060 ps
T1299 /workspace/coverage/default/2.chip_sw_aes_smoketest.997388749 Jun 27 08:43:12 PM PDT 24 Jun 27 08:47:02 PM PDT 24 2321158248 ps
T1300 /workspace/coverage/default/1.chip_tap_straps_dev.2223313836 Jun 27 08:29:31 PM PDT 24 Jun 27 08:51:40 PM PDT 24 13192568248 ps
T75 /workspace/coverage/default/0.chip_sw_usbdev_pincfg.2148349868 Jun 27 08:16:20 PM PDT 24 Jun 27 10:08:45 PM PDT 24 31724952066 ps
T1301 /workspace/coverage/default/0.chip_sw_gpio_smoketest.8625178 Jun 27 08:22:58 PM PDT 24 Jun 27 08:27:23 PM PDT 24 3002606462 ps
T1302 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.957119993 Jun 27 08:40:07 PM PDT 24 Jun 27 08:50:19 PM PDT 24 3531863560 ps
T413 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1471843022 Jun 27 08:20:00 PM PDT 24 Jun 27 08:50:00 PM PDT 24 23294053160 ps
T1303 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2654197993 Jun 27 08:44:58 PM PDT 24 Jun 27 08:51:57 PM PDT 24 4101645285 ps
T1304 /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.1409015840 Jun 27 08:26:24 PM PDT 24 Jun 27 08:35:16 PM PDT 24 4488799608 ps
T1305 /workspace/coverage/default/1.rom_e2e_asm_init_dev.384791877 Jun 27 08:37:23 PM PDT 24 Jun 27 09:50:04 PM PDT 24 14926297448 ps
T1306 /workspace/coverage/default/0.chip_sw_aes_enc.3767162828 Jun 27 08:17:59 PM PDT 24 Jun 27 08:21:00 PM PDT 24 3094438484 ps
T137 /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.3538296496 Jun 27 08:39:05 PM PDT 24 Jun 27 08:47:23 PM PDT 24 3885960898 ps
T1307 /workspace/coverage/default/2.chip_sw_inject_scramble_seed.2033484378 Jun 27 08:33:46 PM PDT 24 Jun 27 11:45:51 PM PDT 24 64793427899 ps
T1308 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.1472606395 Jun 27 08:20:27 PM PDT 24 Jun 27 08:44:41 PM PDT 24 7507160967 ps
T733 /workspace/coverage/default/30.chip_sw_all_escalation_resets.3162411123 Jun 27 08:48:56 PM PDT 24 Jun 27 08:56:48 PM PDT 24 5342415840 ps
T703 /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.3533857557 Jun 27 08:53:21 PM PDT 24 Jun 27 09:00:34 PM PDT 24 3941740600 ps
T1309 /workspace/coverage/default/1.chip_sw_example_concurrency.4291115945 Jun 27 08:23:16 PM PDT 24 Jun 27 08:29:03 PM PDT 24 3055832444 ps
T76 /workspace/coverage/cover_reg_top/37.xbar_smoke_large_delays.1952092660 Jun 27 07:55:45 PM PDT 24 Jun 27 07:57:20 PM PDT 24 8659727482 ps
T77 /workspace/coverage/cover_reg_top/35.xbar_smoke_large_delays.1805101747 Jun 27 07:55:11 PM PDT 24 Jun 27 07:56:39 PM PDT 24 8845484207 ps
T78 /workspace/coverage/cover_reg_top/42.xbar_error_random.832540206 Jun 27 07:57:28 PM PDT 24 Jun 27 07:57:38 PM PDT 24 68838665 ps
T82 /workspace/coverage/cover_reg_top/99.xbar_access_same_device_slow_rsp.3495718308 Jun 27 08:09:16 PM PDT 24 Jun 27 08:52:02 PM PDT 24 143738622611 ps
T158 /workspace/coverage/cover_reg_top/36.xbar_random_zero_delays.690825191 Jun 27 07:55:28 PM PDT 24 Jun 27 07:56:03 PM PDT 24 394195021 ps
T225 /workspace/coverage/cover_reg_top/91.xbar_smoke_large_delays.2539045091 Jun 27 08:07:44 PM PDT 24 Jun 27 08:09:27 PM PDT 24 9303803590 ps
T256 /workspace/coverage/cover_reg_top/82.xbar_smoke_slow_rsp.2388349113 Jun 27 08:06:18 PM PDT 24 Jun 27 08:07:20 PM PDT 24 3658510629 ps
T423 /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_error.3844409120 Jun 27 08:09:03 PM PDT 24 Jun 27 08:13:23 PM PDT 24 7183344575 ps
T146 /workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.200564776 Jun 27 07:46:33 PM PDT 24 Jun 27 09:04:23 PM PDT 24 30111579712 ps
T147 /workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.1413634376 Jun 27 07:47:38 PM PDT 24 Jun 27 08:55:46 PM PDT 24 30934095722 ps
T435 /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_error.3991821536 Jun 27 08:06:40 PM PDT 24 Jun 27 08:07:49 PM PDT 24 883943145 ps
T540 /workspace/coverage/cover_reg_top/94.xbar_smoke_large_delays.1926124364 Jun 27 08:08:16 PM PDT 24 Jun 27 08:09:45 PM PDT 24 8965103814 ps
T538 /workspace/coverage/cover_reg_top/63.xbar_random_slow_rsp.954649887 Jun 27 08:02:12 PM PDT 24 Jun 27 08:10:35 PM PDT 24 29736352156 ps
T501 /workspace/coverage/cover_reg_top/94.xbar_random.916908383 Jun 27 08:08:15 PM PDT 24 Jun 27 08:09:02 PM PDT 24 475943986 ps
T541 /workspace/coverage/cover_reg_top/48.xbar_unmapped_addr.2945484323 Jun 27 07:59:05 PM PDT 24 Jun 27 08:00:03 PM PDT 24 1310779142 ps
T148 /workspace/coverage/cover_reg_top/6.chip_same_csr_outstanding.315057939 Jun 27 07:43:02 PM PDT 24 Jun 27 08:19:14 PM PDT 24 16457422012 ps
T545 /workspace/coverage/cover_reg_top/24.xbar_random_large_delays.621217585 Jun 27 07:51:40 PM PDT 24 Jun 27 07:52:42 PM PDT 24 5996672825 ps
T1310 /workspace/coverage/cover_reg_top/80.xbar_smoke.3664059686 Jun 27 08:05:45 PM PDT 24 Jun 27 08:05:52 PM PDT 24 33337398 ps
T546 /workspace/coverage/cover_reg_top/58.xbar_smoke_large_delays.3877296898 Jun 27 08:00:56 PM PDT 24 Jun 27 08:02:40 PM PDT 24 10360492282 ps
T675 /workspace/coverage/cover_reg_top/28.xbar_access_same_device.2407485602 Jun 27 07:53:01 PM PDT 24 Jun 27 07:53:40 PM PDT 24 923386529 ps
T548 /workspace/coverage/cover_reg_top/22.xbar_smoke_zero_delays.2647740008 Jun 27 07:50:53 PM PDT 24 Jun 27 07:51:01 PM PDT 24 39767270 ps
T534 /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_error.2690163245 Jun 27 08:04:25 PM PDT 24 Jun 27 08:08:47 PM PDT 24 6878496867 ps
T547 /workspace/coverage/cover_reg_top/65.xbar_smoke_large_delays.849816644 Jun 27 08:02:31 PM PDT 24 Jun 27 08:03:32 PM PDT 24 5447960603 ps
T535 /workspace/coverage/cover_reg_top/28.chip_tl_errors.283771470 Jun 27 07:52:57 PM PDT 24 Jun 27 07:57:19 PM PDT 24 3459887305 ps
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