Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1053961	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

30754172

1

T4

119757

T6

15211

T20

16870

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	21659693	1			T4	106596		T6	10929		T20	12889
values[0x0]	9093613	1			T4	13161		T6	4282		T20	3981
values[0x1]	1054827	1			T4	7		T6	2828		T20	3686

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8529	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

31799604

1

T4

119764

T6

18039

T20

20556

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15890855	1			T4	59882		T6	9020		T20	10278
valid_sources[0x01]	15889798	1			T4	59882		T6	9019		T20	10278
valid_sources[0x02]	368	1			T60	36		T62	16		T63	106
valid_sources[0x03]	360	1			T60	22		T61	16		T64	59
valid_sources[0x04]	280	1			T169	4		T60	48		T62	16
valid_sources[0x05]	286	1			T24	2		T168	2		T60	43
valid_sources[0x06]	214	1			T168	1		T60	47		T61	16
valid_sources[0x07]	292	1			T169	1		T60	73		T63	50
valid_sources[0x08]	320	1			T24	1		T254	3		T60	57
valid_sources[0x09]	250	1			T60	56		T63	8		T64	53
valid_sources[0x0a]	276	1			T168	2		T60	82		T63	12
valid_sources[0x0b]	3184	1			T60	35		T63	15		T64	50
valid_sources[0x0c]	225	1			T168	2		T60	30		T63	47
valid_sources[0x0d]	242	1			T24	1		T168	3		T60	47
valid_sources[0x0e]	341	1			T24	1		T28	39		T168	4
valid_sources[0x0f]	325	1			T24	1		T60	51		T61	16
valid_sources[0x10]	202	1			T24	2		T168	1		T254	1
valid_sources[0x11]	521	1			T60	60		T63	42		T64	34
valid_sources[0x12]	291	1			T168	1		T254	1		T60	51
valid_sources[0x13]	1928	1			T60	53		T63	84		T64	54
valid_sources[0x14]	315	1			T254	2		T60	46		T62	94
valid_sources[0x15]	303	1			T168	1		T60	30		T63	80
valid_sources[0x16]	226	1			T254	2		T60	64		T63	22
valid_sources[0x17]	199	1			T24	1		T60	26		T62	16
valid_sources[0x18]	259	1			T24	2		T168	2		T60	25
valid_sources[0x19]	283	1			T168	2		T169	4		T60	46
valid_sources[0x1a]	339	1			T60	52		T63	95		T64	47
valid_sources[0x1b]	255	1			T168	2		T254	1		T60	49
valid_sources[0x1c]	332	1			T60	37		T63	78		T64	40
valid_sources[0x1d]	285	1			T23	39		T168	1		T60	51
valid_sources[0x1e]	334	1			T24	1		T254	1		T60	41
valid_sources[0x1f]	458	1			T60	47		T61	32		T62	149
valid_sources[0x20]	354	1			T24	4		T169	6		T60	59

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

21659693

1

T4

106596

T6

10929

T20

12889

values[0x0]

all_enables

biggest_size

9089294

1

T4

13161

T6

4282

T20

3981

values[0x1]

all_enables

biggest_size

5185

1

T23

19

T24

20

T28

21