Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	470097304	53233230	0	0
DepthKnown_A	470097304	469992619	0	0
RvalidKnown_A	470097304	469992619	0	0
WreadyKnown_A	470097304	469992619	0	0
gen_passthru_fifo.paramCheckPass	992	992	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470097304	53233230	0	0
T4	134245	147460	0	0
T5	41365	0	0	0
T6	197158	22260	0	0
T17	221235	29123	0	0
T18	219998	19888	0	0
T19	261468	34336	0	0
T20	218705	22122	0	0
T21	663418	59288	0	0
T31	0	34329	0	0
T91	217010	40536	0	0
T132	212915	21370	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470097304	469992619	0	0
T4	134245	134240	0	0
T5	41365	41314	0	0
T6	197158	197107	0	0
T17	221235	221111	0	0
T18	219998	219892	0	0
T19	261468	261362	0	0
T20	218705	218643	0	0
T21	663418	663356	0	0
T91	217010	216952	0	0
T132	212915	212853	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470097304	469992619	0	0
T4	134245	134240	0	0
T5	41365	41314	0	0
T6	197158	197107	0	0
T17	221235	221111	0	0
T18	219998	219892	0	0
T19	261468	261362	0	0
T20	218705	218643	0	0
T21	663418	663356	0	0
T91	217010	216952	0	0
T132	212915	212853	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470097304	469992619	0	0
T4	134245	134240	0	0
T5	41365	41314	0	0
T6	197158	197107	0	0
T17	221235	221111	0	0
T18	219998	219892	0	0
T19	261468	261362	0	0
T20	218705	218643	0	0
T21	663418	663356	0	0
T91	217010	216952	0	0
T132	212915	212853	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	992	992	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T91	1	1	0	0
T132	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	470097304	40767560	0	0
DepthKnown_A	470097304	469992619	0	0
RvalidKnown_A	470097304	469992619	0	0
WreadyKnown_A	470097304	469992619	0	0
gen_passthru_fifo.paramCheckPass	992	992	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470097304	40767560	0	0
T4	134245	128462	0	0
T5	41365	0	0	0
T6	197158	18336	0	0
T17	221235	19481	0	0
T18	219998	15623	0	0
T19	261468	24743	0	0
T20	218705	18202	0	0
T21	663418	55307	0	0
T31	0	24738	0	0
T91	217010	30536	0	0
T132	212915	17466	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470097304	469992619	0	0
T4	134245	134240	0	0
T5	41365	41314	0	0
T6	197158	197107	0	0
T17	221235	221111	0	0
T18	219998	219892	0	0
T19	261468	261362	0	0
T20	218705	218643	0	0
T21	663418	663356	0	0
T91	217010	216952	0	0
T132	212915	212853	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470097304	469992619	0	0
T4	134245	134240	0	0
T5	41365	41314	0	0
T6	197158	197107	0	0
T17	221235	221111	0	0
T18	219998	219892	0	0
T19	261468	261362	0	0
T20	218705	218643	0	0
T21	663418	663356	0	0
T91	217010	216952	0	0
T132	212915	212853	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470097304	469992619	0	0
T4	134245	134240	0	0
T5	41365	41314	0	0
T6	197158	197107	0	0
T17	221235	221111	0	0
T18	219998	219892	0	0
T19	261468	261362	0	0
T20	218705	218643	0	0
T21	663418	663356	0	0
T91	217010	216952	0	0
T132	212915	212853	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	992	992	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T91	1	1	0	0
T132	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	470097304	37010784	0	0
DepthKnown_A	470097304	469992619	0	0
RvalidKnown_A	470097304	469992619	0	0
WreadyKnown_A	470097304	469992619	0	0
gen_passthru_fifo.paramCheckPass	992	992	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470097304	37010784	0	0
T4	134245	181582	0	0
T5	41365	0	0	0
T6	197158	18244	0	0
T17	221235	13748	0	0
T18	219998	11407	0	0
T19	261468	17589	0	0
T20	218705	20761	0	0
T21	663418	71668	0	0
T31	0	17602	0	0
T91	217010	24279	0	0
T132	212915	20212	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470097304	469992619	0	0
T4	134245	134240	0	0
T5	41365	41314	0	0
T6	197158	197107	0	0
T17	221235	221111	0	0
T18	219998	219892	0	0
T19	261468	261362	0	0
T20	218705	218643	0	0
T21	663418	663356	0	0
T91	217010	216952	0	0
T132	212915	212853	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470097304	469992619	0	0
T4	134245	134240	0	0
T5	41365	41314	0	0
T6	197158	197107	0	0
T17	221235	221111	0	0
T18	219998	219892	0	0
T19	261468	261362	0	0
T20	218705	218643	0	0
T21	663418	663356	0	0
T91	217010	216952	0	0
T132	212915	212853	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470097304	469992619	0	0
T4	134245	134240	0	0
T5	41365	41314	0	0
T6	197158	197107	0	0
T17	221235	221111	0	0
T18	219998	219892	0	0
T19	261468	261362	0	0
T20	218705	218643	0	0
T21	663418	663356	0	0
T91	217010	216952	0	0
T132	212915	212853	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	992	992	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T91	1	1	0	0
T132	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	470097304	31846110	0	0
DepthKnown_A	470097304	469992619	0	0
RvalidKnown_A	470097304	469992619	0	0
WreadyKnown_A	470097304	469992619	0	0
gen_passthru_fifo.paramCheckPass	992	992	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470097304	31846110	0	0
T4	134245	119764	0	0
T5	41365	0	0	0
T6	197158	18039	0	0
T17	221235	13365	0	0
T18	219998	11162	0	0
T19	261468	17206	0	0
T20	218705	20556	0	0
T21	663418	71462	0	0
T31	0	17220	0	0
T91	217010	23736	0	0
T132	212915	20007	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470097304	469992619	0	0
T4	134245	134240	0	0
T5	41365	41314	0	0
T6	197158	197107	0	0
T17	221235	221111	0	0
T18	219998	219892	0	0
T19	261468	261362	0	0
T20	218705	218643	0	0
T21	663418	663356	0	0
T91	217010	216952	0	0
T132	212915	212853	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470097304	469992619	0	0
T4	134245	134240	0	0
T5	41365	41314	0	0
T6	197158	197107	0	0
T17	221235	221111	0	0
T18	219998	219892	0	0
T19	261468	261362	0	0
T20	218705	218643	0	0
T21	663418	663356	0	0
T91	217010	216952	0	0
T132	212915	212853	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470097304	469992619	0	0
T4	134245	134240	0	0
T5	41365	41314	0	0
T6	197158	197107	0	0
T17	221235	221111	0	0
T18	219998	219892	0	0
T19	261468	261362	0	0
T20	218705	218643	0	0
T21	663418	663356	0	0
T91	217010	216952	0	0
T132	212915	212853	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	992	992	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T91	1	1	0	0
T132	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	470097304	64024	0	0
DepthKnown_A	470097304	469992619	0	0
RvalidKnown_A	470097304	469992619	0	0
WreadyKnown_A	470097304	469992619	0	0
gen_passthru_fifo.paramCheckPass	992	992	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470097304	64024	0	0
T4	134245	34	0	0
T5	41365	0	0	0
T6	197158	53	0	0
T17	221235	155	0	0
T18	219998	30	0	0
T19	261468	151	0	0
T20	218705	53	0	0
T21	663418	53	0	0
T31	0	151	0	0
T91	217010	15	0	0
T132	212915	53	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470097304	469992619	0	0
T4	134245	134240	0	0
T5	41365	41314	0	0
T6	197158	197107	0	0
T17	221235	221111	0	0
T18	219998	219892	0	0
T19	261468	261362	0	0
T20	218705	218643	0	0
T21	663418	663356	0	0
T91	217010	216952	0	0
T132	212915	212853	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470097304	469992619	0	0
T4	134245	134240	0	0
T5	41365	41314	0	0
T6	197158	197107	0	0
T17	221235	221111	0	0
T18	219998	219892	0	0
T19	261468	261362	0	0
T20	218705	218643	0	0
T21	663418	663356	0	0
T91	217010	216952	0	0
T132	212915	212853	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470097304	469992619	0	0
T4	134245	134240	0	0
T5	41365	41314	0	0
T6	197158	197107	0	0
T17	221235	221111	0	0
T18	219998	219892	0	0
T19	261468	261362	0	0
T20	218705	218643	0	0
T21	663418	663356	0	0
T91	217010	216952	0	0
T132	212915	212853	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	992	992	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T91	1	1	0	0
T132	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	470097304	64023	0	0
DepthKnown_A	470097304	469992619	0	0
RvalidKnown_A	470097304	469992619	0	0
WreadyKnown_A	470097304	469992619	0	0
gen_passthru_fifo.paramCheckPass	992	992	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470097304	64023	0	0
T4	134245	34	0	0
T5	41365	0	0	0
T6	197158	53	0	0
T17	221235	155	0	0
T18	219998	30	0	0
T19	261468	151	0	0
T20	218705	53	0	0
T21	663418	53	0	0
T31	0	151	0	0
T91	217010	15	0	0
T132	212915	53	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470097304	469992619	0	0
T4	134245	134240	0	0
T5	41365	41314	0	0
T6	197158	197107	0	0
T17	221235	221111	0	0
T18	219998	219892	0	0
T19	261468	261362	0	0
T20	218705	218643	0	0
T21	663418	663356	0	0
T91	217010	216952	0	0
T132	212915	212853	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470097304	469992619	0	0
T4	134245	134240	0	0
T5	41365	41314	0	0
T6	197158	197107	0	0
T17	221235	221111	0	0
T18	219998	219892	0	0
T19	261468	261362	0	0
T20	218705	218643	0	0
T21	663418	663356	0	0
T91	217010	216952	0	0
T132	212915	212853	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470097304	469992619	0	0
T4	134245	134240	0	0
T5	41365	41314	0	0
T6	197158	197107	0	0
T17	221235	221111	0	0
T18	219998	219892	0	0
T19	261468	261362	0	0
T20	218705	218643	0	0
T21	663418	663356	0	0
T91	217010	216952	0	0
T132	212915	212853	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	992	992	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T91	1	1	0	0
T132	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	470097304	51282	0	0
DepthKnown_A	470097304	469992619	0	0
RvalidKnown_A	470097304	469992619	0	0
WreadyKnown_A	470097304	469992619	0	0
gen_passthru_fifo.paramCheckPass	992	992	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470097304	51282	0	0
T4	134245	5	0	0
T5	41365	0	0	0
T6	197158	52	0	0
T17	221235	96	0	0
T18	219998	28	0	0
T19	261468	95	0	0
T20	218705	52	0	0
T21	663418	52	0	0
T31	0	95	0	0
T91	217010	12	0	0
T132	212915	52	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470097304	469992619	0	0
T4	134245	134240	0	0
T5	41365	41314	0	0
T6	197158	197107	0	0
T17	221235	221111	0	0
T18	219998	219892	0	0
T19	261468	261362	0	0
T20	218705	218643	0	0
T21	663418	663356	0	0
T91	217010	216952	0	0
T132	212915	212853	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470097304	469992619	0	0
T4	134245	134240	0	0
T5	41365	41314	0	0
T6	197158	197107	0	0
T17	221235	221111	0	0
T18	219998	219892	0	0
T19	261468	261362	0	0
T20	218705	218643	0	0
T21	663418	663356	0	0
T91	217010	216952	0	0
T132	212915	212853	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470097304	469992619	0	0
T4	134245	134240	0	0
T5	41365	41314	0	0
T6	197158	197107	0	0
T17	221235	221111	0	0
T18	219998	219892	0	0
T19	261468	261362	0	0
T20	218705	218643	0	0
T21	663418	663356	0	0
T91	217010	216952	0	0
T132	212915	212853	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	992	992	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T91	1	1	0	0
T132	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	470097304	51281	0	0
DepthKnown_A	470097304	469992619	0	0
RvalidKnown_A	470097304	469992619	0	0
WreadyKnown_A	470097304	469992619	0	0
gen_passthru_fifo.paramCheckPass	992	992	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470097304	51281	0	0
T4	134245	5	0	0
T5	41365	0	0	0
T6	197158	52	0	0
T17	221235	96	0	0
T18	219998	28	0	0
T19	261468	95	0	0
T20	218705	52	0	0
T21	663418	52	0	0
T31	0	95	0	0
T91	217010	12	0	0
T132	212915	52	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470097304	469992619	0	0
T4	134245	134240	0	0
T5	41365	41314	0	0
T6	197158	197107	0	0
T17	221235	221111	0	0
T18	219998	219892	0	0
T19	261468	261362	0	0
T20	218705	218643	0	0
T21	663418	663356	0	0
T91	217010	216952	0	0
T132	212915	212853	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470097304	469992619	0	0
T4	134245	134240	0	0
T5	41365	41314	0	0
T6	197158	197107	0	0
T17	221235	221111	0	0
T18	219998	219892	0	0
T19	261468	261362	0	0
T20	218705	218643	0	0
T21	663418	663356	0	0
T91	217010	216952	0	0
T132	212915	212853	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470097304	469992619	0	0
T4	134245	134240	0	0
T5	41365	41314	0	0
T6	197158	197107	0	0
T17	221235	221111	0	0
T18	219998	219892	0	0
T19	261468	261362	0	0
T20	218705	218643	0	0
T21	663418	663356	0	0
T91	217010	216952	0	0
T132	212915	212853	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	992	992	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T91	1	1	0	0
T132	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	470097304	12742	0	0
DepthKnown_A	470097304	469992619	0	0
RvalidKnown_A	470097304	469992619	0	0
WreadyKnown_A	470097304	469992619	0	0
gen_passthru_fifo.paramCheckPass	992	992	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470097304	12742	0	0
T4	134245	29	0	0
T5	41365	0	0	0
T6	197158	1	0	0
T17	221235	59	0	0
T18	219998	2	0	0
T19	261468	56	0	0
T20	218705	1	0	0
T21	663418	1	0	0
T31	0	56	0	0
T91	217010	3	0	0
T132	212915	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470097304	469992619	0	0
T4	134245	134240	0	0
T5	41365	41314	0	0
T6	197158	197107	0	0
T17	221235	221111	0	0
T18	219998	219892	0	0
T19	261468	261362	0	0
T20	218705	218643	0	0
T21	663418	663356	0	0
T91	217010	216952	0	0
T132	212915	212853	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470097304	469992619	0	0
T4	134245	134240	0	0
T5	41365	41314	0	0
T6	197158	197107	0	0
T17	221235	221111	0	0
T18	219998	219892	0	0
T19	261468	261362	0	0
T20	218705	218643	0	0
T21	663418	663356	0	0
T91	217010	216952	0	0
T132	212915	212853	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470097304	469992619	0	0
T4	134245	134240	0	0
T5	41365	41314	0	0
T6	197158	197107	0	0
T17	221235	221111	0	0
T18	219998	219892	0	0
T19	261468	261362	0	0
T20	218705	218643	0	0
T21	663418	663356	0	0
T91	217010	216952	0	0
T132	212915	212853	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	992	992	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T91	1	1	0	0
T132	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	470097304	12742	0	0
DepthKnown_A	470097304	469992619	0	0
RvalidKnown_A	470097304	469992619	0	0
WreadyKnown_A	470097304	469992619	0	0
gen_passthru_fifo.paramCheckPass	992	992	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470097304	12742	0	0
T4	134245	29	0	0
T5	41365	0	0	0
T6	197158	1	0	0
T17	221235	59	0	0
T18	219998	2	0	0
T19	261468	56	0	0
T20	218705	1	0	0
T21	663418	1	0	0
T31	0	56	0	0
T91	217010	3	0	0
T132	212915	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470097304	469992619	0	0
T4	134245	134240	0	0
T5	41365	41314	0	0
T6	197158	197107	0	0
T17	221235	221111	0	0
T18	219998	219892	0	0
T19	261468	261362	0	0
T20	218705	218643	0	0
T21	663418	663356	0	0
T91	217010	216952	0	0
T132	212915	212853	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470097304	469992619	0	0
T4	134245	134240	0	0
T5	41365	41314	0	0
T6	197158	197107	0	0
T17	221235	221111	0	0
T18	219998	219892	0	0
T19	261468	261362	0	0
T20	218705	218643	0	0
T21	663418	663356	0	0
T91	217010	216952	0	0
T132	212915	212853	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470097304	469992619	0	0
T4	134245	134240	0	0
T5	41365	41314	0	0
T6	197158	197107	0	0
T17	221235	221111	0	0
T18	219998	219892	0	0
T19	261468	261362	0	0
T20	218705	218643	0	0
T21	663418	663356	0	0
T91	217010	216952	0	0
T132	212915	212853	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	992	992	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T91	1	1	0	0
T132	1	1	0	0